JPH0863534A - Weighting adding circuit - Google Patents

Abstract

PURPOSE: To provide a weighting adding circuit capable of the weighting addition of arithmetic accuracy in a small scale. CONSTITUTION: The circuit is provided with plural parallelly connected input resistances R1 to R3 one ends of which input voltage V1 to V3 are respectively applied to and the other ends of which are set to be a common output and an amplifier circuit connected to the common output of these input resistances. Then, the amplifier circuit is provided with inverters INV 1 to INV 3 which are directly connected by odd number stages and a feedback resistance Ro feeding the output of the last inverter back to the input of the first inverter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a weighted addition circuit for adding, amplifying and outputting a plurality of analog or multi-valued input voltages.

[0002]

2. Description of the Related Art Conventionally, as a weighted addition circuit,
Digital type and analog type adder circuits are used.

[0003]

However, the digital type adder circuit has a large circuit scale, and the analog type weighted adder circuit has a problem that the calculation accuracy is low.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a weighted addition circuit which is small in scale and is capable of performing weighted addition with high calculation accuracy.

[0005]

In order to achieve the above object, an adder circuit according to the present invention has a plurality of input resistances connected in parallel, each of which has an input voltage applied to one end and a common output at the other end. And an amplifier circuit connected to a common output of these input resistances, and the amplifier circuit feeds back the output of the inverter of the odd stage directly and the output of the inverter of the final stage to the input of the inverter of the first stage. And a feedback resistance.

[0006]

Embodiments of the adder circuit according to the present invention will be described below. First Embodiment FIG. 1 is a circuit diagram showing a weighted addition circuit according to a first embodiment of the present invention.

The weighted adder circuit of the embodiment has a plurality of, in this example, three input resistances R1 connected in parallel,
It has R2 and R3. Input voltages V1, V2, and V3 are input to these input resistances, respectively, and output sides thereof are connected together and input to the amplifier circuit Amp.

The amplifier circuit Amp has an odd number of stages, 3 in this example.
Inverters INV1, INV2, IN connected in series
V3 and a feedback resistance Ro for feeding back the output of the final stage inverter INV3 to the input of the first stage inverter INV1. Also,
A capacitance CL having a low-pass characteristic is connected to the output side of the final stage inverter with one end grounded to prevent oscillation.

Assuming that the impedance of the amplifier circuit Amp is infinite, the balanced voltage at the resistance common output connected in parallel is V4, the output voltage of the Amp is Vo1, and the currents flowing through the resistances R1, R2, R3, and R0 are I1. ,
When I2, I3, and I4 are set, the following equations (1) to (5) are established.

[0010]

[Equation 1]

In reality, when the impedance of Amp is sufficiently high, the above equations (1) to (5) are approximately valid and the output voltage Vo1 is given as follows.

[Equation 2]

The result of the weighted addition is amplified and output by the amplifier circuit, and its amplification factor can be arbitrarily set by the resistance value of the feedback resistance Ro.

In the first embodiment, the input voltage is set to three systems, but the invention is not limited to this embodiment, and if there are two or more systems, the resistances of a number corresponding to the number of input systems are connected in parallel. By connecting them, weighted addition of input voltage is possible. By generalizing equation (6) and adding an offset term, the following equation (7) is obtained. Here, V4 is a constant, and normally V4 = Vdd / 2.

[0014]

(Equation 3)

FIG. 2 is a circuit diagram showing a second embodiment of the weighted addition circuit of the present invention. Similar to the circuit shown in FIG. 1, this adder circuit has three input resistances R1 connected in parallel with one end to which input voltages V1, V2 and V3 to be added are applied and the other end being a common output. , R2, R
3 and the first amplifier circuit Amp1 connected to the common output of these input resistances, and the output of the first amplifier circuit Amp1 and the input voltage V5 to be subtracted are applied to one end of each and the other end. Has two common resistances R4 and R5 connected in parallel and a second amplifier circuit Amp2 connected to the common output of these middle resistances R4 and R5.

The first amplifier circuit Amp1 has the inverters INV1, INV2, INV3 directly connected to the three stages and the output of the final stage inverter INV3 and the first stage inverter I.
And a feedback resistance R0 that feeds back to the input of NV1.

Similarly, the second amplifier circuit Amp2 has three stages of inverters INV4, INV5, INV6 connected in series.
And a feedback resistance R6.

Further, capacitors CL1 and CL2 having low-pass characteristics are connected to the output side of the final stage inverter of each amplifier circuit with one end grounded to prevent oscillation.

The output voltage Vo2 of the second amplifier circuit Amp2 is
It is expressed by the following equation (8).

[0020]

[Equation 4]

Here, the input voltage of Amp1 and Amp2 is Voff, and R6 = R4, R6 / R5 = Ro (1 / R1 + 1 /
R2 + 1 / R3). Furthermore, when substituting the equation (6) into Vo1 of the equation (8),

(Equation 5) Is obtained.

Further, if the condition of R6 / R5 relating to the equation (8) is changed to the equation (10), the above Vof can be canceled out, and the equation (9) can be simplified as follows.

(Equation 6)

The offset voltage is precisely controlled in the LSI, and the calculation based on the equation (9) is sufficiently practical. As described above, VOff is normally set to Vdd / 2.

From the expressions (9) and (10), it can be understood that the output voltage Vo2 is a value obtained by subtracting the voltage V5 to be subtracted from the sum of the input voltages V1, V2 and V3 to be added.

3, 4 and 5 are amplifier circuits of the circuit of FIG.
Alternatively, a modified example of the first and second amplifier circuits Amp1 and Amp2 in FIG. 2 is shown. In the circuit of FIG. 3, the first stage inverter I
Balance resistances Ra and Rb are provided between NV1 and the second-stage inverter INV2. In the example of FIG. 4, in addition to this, the second-stage inverter INV2 and the third-stage inverter INV3 are connected. Balance resistance Rc, Rd
Is provided. In the example of FIG. 6, R is provided between the second-stage inverter INV2 and the third-stage inverter INV3.
Only c and Rd are provided.

In theory, one of the low-pass characteristic capacitance CL1 and the balance resistance can prevent oscillation, but when only the capacitance CL1 is provided, the capacitance becomes excessive, and on the contrary, the balance resistance R11, When only R12 is provided, there is a problem that the linear characteristic is deteriorated, so both of them are provided in the circuits of FIGS.

[0027]

As described above, according to the present invention, since the balanced voltage of the resistances connected in parallel is amplified by the amplifier circuit and output, the circuit scale is small but the analog type is highly accurate. It is possible to perform weighted addition of and to cope with an input of an arbitrary number of systems with a simple configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a weighted addition circuit of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the weighted addition circuit of the present invention.

FIG. 3 is a circuit diagram showing a modification of the amplifier circuit used in the above embodiment.

FIG. 4 is a circuit diagram showing another modification of the amplifier circuit used in the above embodiment.

FIG. 5 is a circuit diagram showing still another modification of the amplifier circuit used in the above embodiment.

[Explanation of symbols]

 R1, R2, R3 Input resistance Ro Feedback resistance INV1, INV2, INV3 Inverter CL Low pass characteristic capacitance V1, V2, V3 Input voltage Vo Output voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd.

Claims (6)

[Claims] 1. A plurality of input resistances connected in parallel, each having an input voltage applied to one end and a common output at the other end, and an amplifier circuit connected to a common output of the input resistances, The amplifier circuit has a weighted adder circuit having an inverter directly connected to an odd number of stages and a feedback resistance for feeding back an output of the final stage inverter to an input of the first stage inverter. 2. The weighted adder circuit according to claim 1, wherein the amplifier circuit has a capacitance having one end connected to the output of the final stage inverter and the other end grounded. 3. The weighted adder circuit according to claim 1, wherein the inverters of the amplifier circuit are connected in series in three stages. 4. A plurality of parallel-connected input resistances, one end of which is applied with an input voltage to be added and the other end of which is a common output, and a first amplification connected to a common output of the input resistances. Circuit, two intermediate resistances connected in parallel with one end to which the output of the first amplifier circuit and the input voltage to be subtracted are applied, and the other end being a common output, and a common output of the intermediate resistances. A second amplifier circuit connected to the first and second amplifier circuits, wherein the first and second amplifier circuits respectively connect the output of the inverter of the odd stage to the input of the inverter of the last stage. A weighted adder circuit having a feedback resistance for feedback. 5. The weighted adder circuit according to claim 4, wherein the inverters of the first and second amplifier circuits are connected in series in three stages. 6. The ratio of the combined resistance of the input resistance and the feedback resistance in the first amplifier circuit, and the ratio of the combined resistance of the intermediate resistance to which the input voltage to be subtracted is connected and the feedback resistance in the second amplifier circuit. Is set so that the value obtained by adding 1 to the latter becomes substantially equal to the former, the weighted addition circuit according to claim 4.