JPH0855920A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is possible to form line & space patterns with a pitch narrower than the minimum pitch determined by PEP.
To provide a method for manufacturing a semiconductor device that can contribute to miniaturization and high integration of elements. In a method of manufacturing a semiconductor device having a plurality of parallel stripe-shaped conductive film patterns on a semiconductor substrate, a polycrystalline silicon film 15 is formed on a silicon substrate 11 via a gate insulating film 14, and then a polycrystalline silicon film 15 is formed. Crystalline silicon film 1
5, a CVD silicon oxide film 16 is formed, then the oxide film 16 is patterned into a stripe shape, then a CVD silicon nitride film 19 is formed on the polycrystalline silicon film 15 and the oxide film 16, and then a nitride film 19 is formed. The entire surface is etched to leave only the side wall of the stripe pattern, the oxide film 16 is removed, and then the polycrystalline silicon film 15 is selectively etched using the nitride film 19 as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device suitable for manufacturing a device having a fine pitch stripe pattern such as a control gate of a NAND cell type EEPROM. Regarding

[0002]

2. Description of the Related Art In recent years, as an electrically rewritable and highly-integrated EEPROM, a memory cell in which a plurality of memory cells are connected in series to form a NAND cell is known. FIG. 8 is a plan view showing one NAND cell of such an EEPROM, and FIGS. 9 (a) and 9 (b) are respectively A- of FIG.
A'and BB 'cross sections are shown. p-type silicon substrate (or wafer in which p-type well is formed on n-type silicon substrate) 1
In this example, NAND cells having eight memory cells M1 to M8 and two select gate transistors S1 and S2 are arrayed in a region surrounded by the element isolation insulating film 2.

A memory cell forming a NAND cell has a floating gate 4 (4 ₁ , 4 _{1) formed of} a first-layer polycrystalline silicon film on a substrate 1 with a first gate insulating film 3 made of a thermal oxide film interposed therebetween.
_2, ...) are formed, and further the control gate 6 by the second layer polycrystalline silicon film via a second gate insulating film 5 made of oxide film (6 _1, 6 _2, ...) are formed. The gate insulating films of the select gate transistors S1 and S2 are formed at the same time as the gate insulating film 5, and their gate electrodes 8 ₁ , 8 are formed.
₂ is formed at the same time as the control gate 6. The control gate 6 of each memory cell is continuously formed in the row direction to form a word line. An n-type diffusion layer 7 serving as a source and a drain is formed between the memory cells, and the source and the drain are connected in series so that adjacent ones are connected in series to form a NAND cell.

In forming such a NAND cell,
The floating gate and the control gate are patterned in a self-aligned manner. The process will be briefly described. First, a first-layer polycrystalline silicon film is deposited on a substrate via a first gate insulating film. In order to separate the floating gates of the memory cells arranged in the word line direction in the first-layer polycrystalline silicon film, an isolation groove located in the element region is formed, and then a second gate insulating film is formed over the isolation groove. Deposit a layer of polycrystalline silicon film. Then, a resist pattern is formed by the PEP process, and using this as a mask, the second pattern is formed by reactive ion etching.
The control gate and the floating gate are separately formed by sequentially selectively etching the layer polysilicon film, the second gate insulating film and the first layer polysilicon film.

Writing and erasing operations of this NAND cell type EEPROM are performed by exchanging charges by a tunnel current between the substrate 1 and the floating gate 4. For example, in the batch erase method, a high potential is applied to the control gates and select gates of all the memory cells, and the bit line connected to the drains of the NAND cells and the common source line of the NAND cells are grounded.
As a result, electrons are injected from the substrate to the floating gate in all memory cells, and a state "1" in which the threshold value moves in the positive direction is obtained. For writing, the memory cell M on the source side
It is performed in order from 8.

First, the control gate of the memory cell M8, the shared source and the source-side selection gate are grounded, and a photopotential is applied to the remaining control gate and drain (ie, bit line).
As a result, the high potential of the bit line is transmitted to the drain of the memory cell M8, and in the memory cell M8, electrons in the floating gate are emitted to the drain diffusion layer and the threshold value moves in the negative direction. That is, "0" is written. Thereafter, data writing is performed in the order of the memory cells M7, M6, .... The data reading is performed by grounding the control gate and the common source line of the selected memory cell, applying a power supply potential to the remaining control gate and selection gate, and detecting the presence or absence of current.

This NAND cell type EEPROM has the advantages that the number of contacts is greatly reduced and high integration is possible as compared with the conventional NOR type. However, there are still problems when trying to further increase the degree of integration. That is, the control gate and the floating gate must be independently patterned for each memory cell. Therefore, a space is always required between the memory cells, and a source / drain diffusion layer shared by the memory cells adjacent to this portion is formed. In the conventional patterning process of the control gate and the floating gate, the pitch between the control gates is determined by the exposure technique of the PEP stepper, and it is impossible to obtain a fine pitch exceeding the processing limit.

A similar problem is the control gate type EEPRO.
Not limited to M, NAND using MNOS type memory cell
There is also a cell type EEPROM. Further, not only the EEPROM but also a so-called mask ROM in which a MOS transistor in which information is fixedly written by channel ion implantation or the like is used as a memory cell has a similar problem when the NAND cell configuration is adopted.

[0009]

As described above, the conventional N
In the manufacturing process of the AND cell type EEPROM, there is a problem that the pitch between control gates cannot be made sufficiently small, which hinders further high integration. Also,
The above problem is not limited to the EEPROM, and can be similarly applied to the manufacture of various semiconductor devices having a narrow pitch line & space pattern.

The present invention has been made in consideration of the above circumstances, and an object thereof is to form a line & space pattern having a pitch narrower than a minimum pitch determined by ordinary lithography (PEP). An object of the present invention is to provide a method of manufacturing a semiconductor device that can be manufactured and can contribute to miniaturization and high integration of elements.

[0011]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention is a method for manufacturing a semiconductor device having a plurality of parallel stripe-shaped conductive film patterns on a semiconductor substrate,
After forming a conductive film on a semiconductor substrate, a first mask material film is formed on the conductive film, and then the first mask material film is patterned into a stripe shape. Then, the conductive film and the first mask material are formed. A second mask material film different from these is formed on the film, then the second mask material film is entirely etched and left only on the sidewalls of the stripe pattern, and then the first mask material film is removed. The conductive film is selectively etched using the second mask material film as a mask.

Further, according to the present invention, a NAND cell is formed by serially connecting a plurality of nonvolatile memory cells each having a floating gate and a control gate laminated on a semiconductor substrate to form a NAND cell. In the device manufacturing method, a first-layer polycrystalline silicon film to be a floating gate is formed on a semiconductor substrate via a first gate insulating film, and then the first-layer polycrystalline silicon film is adjacent in the word line direction. After processing so as to separate the elements, a second-layer polycrystalline silicon film serving as a control gate is formed on the entire surface of the substrate through a second gate insulating film, and then a first polycrystalline silicon film is formed on the second-layer polycrystalline silicon film. Of the mask material film, the first mask material film is patterned into a stripe shape, and then the second-layer polycrystalline silicon film and the second mask material made of a material different from that of the first mask material film are formed on the entire surface of the substrate. A second mask material film is formed, and then the second mask material film is entirely etched to leave only the side wall portion of the stripe pattern, and then the first mask material film is removed. Then, the second mask material film is used as a mask. The second polycrystalline silicon film, the second gate insulating film, and the first polycrystalline silicon film are sequentially etched.

[0013]

According to the present invention, the width of the second mask material film left on the side wall of the first mask material film can be made smaller than the minimum size determined by the normal PEP, and the adjacent second mask material film can be formed. The distance between the material films can also be smaller than the minimum size determined by PEP. Therefore, by etching the conductive film using the second mask material film, the pitch of the lines and spaces of the conductive film can be made extremely narrow, which allows high integration of the semiconductor device.

In particular, when applied to the gate processing of the NAND cell type EEPROM, the space between the gates can be made finer than the processing limit of the PEP, so that the NAND cell type EEPROM can be highly integrated. Becomes

[0015]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the case where the invention is applied to the EEPROM will be described, but it goes without saying that the present invention is not limited to this and can be applied to various semiconductor devices.

1 to 6 are views showing a manufacturing process of a NAND cell type EEPROM according to the first embodiment of the present invention. In these figures, (a) is a sectional view,
(B) is a plan view.

First, as shown in FIG. 1A, a thermal oxide film (tunnel oxide film) 12 having a thickness of about 10 nm is formed on the surface of an element formation region on a silicon substrate 11, and a floating gate and a tunnel gate film are formed thereon. Then, the first-layer polycrystalline silicon film 13 is deposited. Isolation trenches are formed in the first-layer polycrystalline silicon film 13 to isolate floating gates of memory cells in the word line direction. Then, 25 to 15 in terms of silicon thermal oxide film
A second gate insulating film 14 having a thickness of about nm is formed, and a second-layer polycrystalline silicon film 15 serving as a control gate is deposited on the second gate insulating film 14. Furthermore, a CVD silicon oxide film (or CVD
A silicon nitride film 16 is deposited and formed, and the CVD silicon oxide film 16 is patterned in stripes using the resist pattern 17 as a mask. This striped pattern
For example, the line width is 0.3 μm and the line interval is 1.1 μm.

Incidentally, FIG. 1B shows a state in which the resist pattern 17 is removed after the patterning of the oxide film 16 described above. Reference numeral 18 in the figure denotes an element region surrounded by an element isolation oxide film.

Next, as shown in FIG. 2A, a CVD silicon nitride film (or CVD silicon oxide film) 19 is deposited on the entire surface of the substrate. Thereafter, as shown in FIG. 2B, a resist 21 is formed so as to cover both ends of the stripe pattern of the CVD silicon oxide film 16. Also,
FIG. 3 shows a sectional structure taken along the line AA ′ of FIG. 2B in this state. Reference numeral 22 in the drawing is an element isolation oxide film.

Then, as shown in FIG.
The silicon nitride film 19 is entirely etched by reactive ion etching to leave the CVD silicon nitride film 19 only on the sidewalls of the stripe pattern of the CVD silicon oxide film 16. CVD remaining on the side wall of the CVD silicon oxide film 16
The width of the silicon nitride film 19 is, eg, 0.4 μm.
Here, as shown in FIG. 4B, the portion of the CVD silicon nitride film 19 covered with the resist 21 also remains.

Next, after removing the CVD silicon oxide film 16 by etching, a photoresist 23 is applied to the entire surface as shown in FIG. 5 (a). Then, this is exposed and drawn to form an opening 24 in the resist 23, as shown in FIG. Then, the CVD silicon nitride film 19 exposed in the opening 24 of the resist is etched, and then the resist 23 is removed. Note that reference numeral 25 in the figure denotes a contact region of the control gate.

In FIG. 5, a CVD silicon nitride film 19 is formed.
The reason why the resist 23 is used as a mask to etch only a specific portion is as follows. In the figure, the CVD silicon nitride film 19 is attached to the side wall of the stripe pattern of the CVD silicon oxide film 16, but C deposited on the side wall via the edge portion of the pattern of the CVD silicon oxide film 16
The VD silicon nitride film 19 is connected to both sides of the pattern of the CVD silicon oxide film 16. Therefore, the second-layer polycrystalline silicon layer (used as a control gate), which is etched by using the CVD silicon nitride film 19 as a mask, is also short-circuited between adjacent lines. To avoid this, the resist 23 is used to form the CVD silicon nitride film 1 at the edge portion.
Only 9 is etched.

Next, as shown in FIG. 6A, CVD
Using the silicon nitride film 19 as a mask, the second-layer polycrystalline silicon film 15, the second gate insulating film 14, and the first-layer polycrystalline silicon film 13 are simultaneously etched by reactive ion etching. As a result, the control gates and floating gates of the plurality of memory cells in the NAND cell are formed in a self-aligned manner. Note that FIG. 6B shows a control gate pattern made of the second-layer polycrystalline silicon 15 formed by the above process.

As described above, according to this embodiment, the CVD silicon nitride film 19 is left on the side wall of the stripe pattern of the CVD silicon oxide film 16 by self-alignment, and this CVD is performed.
With the silicon nitride film 19 as a mask, the polycrystalline silicon film 15,
By selectively etching 13, the polycrystalline silicon films 15 and 13 can be patterned with a narrower pitch than before.

Specifically, using a lithographic stepper having a line width of the photoresist 17 and a gap of 0.3 μm and a pitch of 1.4 μm of 1.1 μm, the gate length and the gap between the gates are 0.4 μm, respectively. And a gate pattern with a pitch of 0.7 μm can be formed. Therefore, control gate and floating gate in EEPROM are
It is possible to form a pitch narrower than the minimum pitch determined by EP, and it is possible to realize high integration of the EEPROM by making the memory cell interval forming the NAND cell fine.

The present invention is not limited to the above embodiments. In the embodiment, the CVD silicon nitride film 19 is used as a mask material at the time of etching the first and second layer polycrystalline silicon films 13 and 15 and the second gate insulating film 14, but a CVD silicon oxide film is used instead. Good. In this case, the CVD silicon oxide film 16 may be a CVD silicon nitride film.

Further, as shown in FIG. 7A, another mask material 31 having etching resistance is previously formed under the film of the CVD silicon nitride film 19 and is masked with the CVD silicon nitride film 19. The material 31 is patterned. Then, as shown in FIG. 7B, the CVD silicon nitride film 1 is formed.
After removing only 9, the first and second mask materials 31 are used.
Polycrystalline silicon films 13 and 15 and second gate insulating film 14
May be selectively etched.

Further, in the embodiment, the NAND cell type EEPR is used.
Although the gate pattern formation of the OM has been described, the present invention can be applied to the manufacture of various semiconductor devices having a fine pitch line & space pattern. In addition, various modifications can be made without departing from the scope of the present invention.

[0029]

As described in detail above, according to the present invention, the second mask is formed on the side wall of the first mask material film formed on the stripe.
The mask material film of No. 2 is left by self-alignment, and the conductive film is selectively etched by using this second mask material film as a mask to form a line & space pattern having a pitch narrower than the minimum pitch determined by ordinary lithography (PEP). It can be formed and can contribute to miniaturization and high integration of the device.

Particularly, by utilizing it for the processing of the gate pattern of the NAND cell type EEPROM, the interval between the memory cells forming the NAND cell is made fine and the EEP
It is possible to realize high integration of the ROM.

[Brief description of drawings]

FIG. 1 is a sectional view and a plan view showing a manufacturing process of a NAND cell part according to an embodiment of the present invention.

2A and 2B are a sectional view and a plan view showing a manufacturing process of a NAND cell portion according to an embodiment of the present invention.

FIG. 3 is a sectional view taken along the line AA ′ of FIG.

FIG. 4 is a sectional view and a plan view showing a manufacturing process of a NAND cell part according to an embodiment of the present invention.

5A and 5B are a sectional view and a plan view showing a manufacturing process of a NAND cell portion according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a NAND cell part according to another embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of a NAND cell part according to another embodiment of the present invention.

FIG. 8 is a plan view showing one NAND cell structure of the EEPROM.

9 is a sectional view taken along line AA ′ and BB ′ of FIG.

[Explanation of symbols]

 11 ... Silicon substrate 12 ... Second gate insulating film 13 ... First layer polycrystalline silicon film (floating gate) 14 ... Second gate insulating film 15 ... Second layer polycrystalline silicon film (control gate) 16 ... CVD silicon oxide film (First mask material film) 17, 21 and 23 ... Photoresist 18 ... Element region 19 ... CVD silicon nitride film (second mask material film) 22 ... Element isolation oxide film 24 ... Resist opening 25 ... Contact region 31 ... Mask material

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a plurality of parallel stripe-shaped conductive film patterns on a semiconductor substrate, the method comprising: forming a conductive film on the semiconductor substrate; and forming a first mask on the conductive film. A step of forming a material film, a step of patterning the first mask material film in a stripe shape, and a step of forming a second mask material film different from these on the conductive film and the first mask material film. A step of completely etching the second mask material film to leave the second mask material film only on the side wall of the stripe pattern, a step of removing the first mask material film, and a second mask material film. And a step of selectively etching the conductive film using the mask as a mask. 2. A plurality of nonvolatile memory cells, each having a floating gate and a control gate laminated on a semiconductor substrate, are connected in series to form an NA.
In a method for manufacturing a semiconductor device that constitutes an ND cell and is configured by arranging a plurality of NAND cells, a first-layer polycrystalline silicon film to be a floating gate is formed on a semiconductor substrate via a first gate insulating film. And the first step
A step of processing the multi-layered polycrystalline silicon film so as to separate the elements adjacent to each other in the word line direction;
Forming a second-layer polycrystalline silicon film to serve as a control gate through the gate insulating film, and forming a first mask material film on the second-layer polycrystalline silicon film, and forming the first mask material film. A step of patterning into a stripe shape, a step of forming a second layer polycrystalline silicon film and a second mask material film of a material different from the first mask material film on the entire surface of the substrate, and a second mask material film Etching the entire surface to leave the second mask material film only on the side wall of the stripe pattern, and then removing the first mask material film,
Then, a step of sequentially etching the second polycrystalline silicon film, the second gate insulating film, and the first polycrystalline silicon film by using the second mask material film as a mask is included.