JPH0850797A - Sample & hold circuit - Google Patents

Abstract

PURPOSE:To obtain a sample & hold circuit in which generation of refresh noise is prevented by providing a pair of sample & hold circuits and a multiplexer. CONSTITUTION:The sample & hold circuit comprises a first sample & hold circuit SH1, a second sample & hold circuit SH2, and a multiplexer MUX, wherein an input voltage Vin is fed to the first sample & hold circuit SH1. The second sample & hold circuit is fed with an output from the first sample & hold circuit SH1 and the multiplexer MUX selects the output from the first and second sample & hold circuits alternatively. Since the sample & hold circuit SH1 receives an output from the sample & hold circuit SH1, the input voltage Vin is taken in with a lag corresponding to a single sample & hold timing. The lag is used in the multiplexer MUX for outputting a data from the SH2 at the time of refreshing the hold circuit of the SH1 and a switching is made again to the output from the SH1 upon finishing the refresh thus eliminating the influence of refresh noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit used for holding a required analog voltage at a predetermined timing or transferring it to a predetermined position in analog or multi-value calculation.

[0002]

BACKGROUND OF THE INVENTION The inventors of the present invention have filed Japanese Patent Application No. 05-045.
No. 900 proposes this type of sample and hold circuit. As shown in FIG. 10, this sample-hold circuit includes a sample circuit S1 in which the input and output of odd-numbered series MOS inverters INV1 are connected by a feedback capacitance CF1, and the sample circuit S1.
To the switch SW1 for connecting the input voltage Vin via the coupling capacitance CC1 and the odd-numbered series M
A hold circuit H1 in which the input and output of the OS inverter INV2 are connected by a feedback capacitance CF2
And a coupling capacitance CC2 for connecting the output of the sample circuit S1 to the input of the hold circuit H1, the coupling capacitance CC2 and the sample circuit S1.
And a switch SW2 for opening and closing, and holding the charge in the capacitances CF1, CF2, CC1, and CC2 to store data.

In such a configuration, charges may remain in the MOS, capacitance, etc. If left unattended, the offset of output data increases. In order to eliminate this offset, it is necessary to short-circuit the input and output of the sample circuit S1 and the hold circuit H1 to perform so-called refresh, but at this time, refresh noise is generated in the output of the sample hold circuit.

[0004]

SUMMARY OF THE INVENTION The present invention was devised to solve such conventional problems, and an object of the present invention is to provide a sample hold circuit capable of preventing refresh noise.

[0005]

A sample and hold circuit according to the present invention is provided with a pair of sample and hold circuits and selects the outputs of these sample and hold circuits by a multiplexer, and refreshes the first sample and hold circuit. The output of the second sample-and-hold circuit is adopted during the operation.

[0006]

According to such a sample hold circuit, refresh noise can be effectively prevented.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one of the sample and hold circuits according to the present invention will be described.
An embodiment will be described with reference to the drawings.

In FIG. 1, the sample and hold circuit has a first sample and hold circuit SH1, a second sample and hold circuit SH2 and a multiplexer MUX, and an input voltage Vin is input to the first sample and hold circuit SH1. The output of the first sample-and-hold circuit SH1 is input to the second sample-and-hold circuit SH2, and the multiplexer MUX selectively selects the output of the first and second sample-and-hold circuits. The sample hold circuit SH1 has
Further, the sample signal Ss, the hold signal Sh, the first refresh signal Rf1, and the second refresh signal Rf2 are input, and the sample signal Ss and the first refresh signal Rf1 are input to the sample hold circuit SH2.

The sample signal Ss causes sampling in the sample-hold circuits SH1 and SH2 (corresponding to the data holding in S1 of the conventional example), and the hold signal Sh holds in the sample-hold circuit SH1 (H1 of the conventional example). (Corresponding to data retention in) is executed. Here, since the output of the sample hold circuit SH1 is input to the sample hold circuit SH2, the input voltage Vi
n is fetched with a delay of one sample hold timing. By utilizing this delay, when the hold circuit of SH1 is refreshed by the multiplexer MUX, data is output from SH2, and after the refresh is completed, the output from SH1 is switched again to erase the influence of refresh noise.

FIG. 2 is a block diagram showing the sample and hold circuit SH1, in which the input voltage Vin is switched to the switch SW1.
1. Connected to the sample circuit S11 via the coupling capacitance CC11 in sequence, and the sample circuit S11
Is connected to the hold circuit H11 through the switch SW12 and the coupling capacitance CC12 in sequence.

The sample circuit S11 is a three-stage series MOS
The final stage outputs of the inverters INV11 to INV13 (FIG. 5) are connected to the first stage input via the feedback capacitance Cf11, and due to the amplification performance of the INV11 to INV13, the inversion of Vin (power supply voltage −Vin) in good linear characteristics Occurs at the output of S11. On the other hand, the hold circuit H11 is a three-stage series MOS similar to S11.
The final stage outputs of the inverters INV11 to INV13 (FIG. 5) are connected to the first stage input via the feedback capacitance Cf12, and when the switch SW12 is closed, the output of S11 is inverted, that is, Vin itself becomes H.
11 output.

Further, the sample hold circuit SH1 includes capacitances CC11, CC12, Cf11, Cf12.
Switches SW13 to SW16 for refreshing
When the switches SW15 and SW16 are closed, the same potential is applied to both ends of the capacitances Cf11 and Cf12, and refresh is performed. Switch S
W13 and SW14 are connected to CC11 and CC12 with a reference voltage (here, a voltage Vdd that is ½ of the MOS drain voltage Vdd).
/ 2) is applied, and the inputs of S11 and H11 are returned to the reference voltage.

Switch SW11 and capacitance CC1
1 is connected to one end of an additional capacitance Cad11 for increasing the charge retention capability of the sample circuit S11, and the other end of Cad11 is connected to the reference voltage generation circuit Gstd. On the other hand, between the switch SW12 and the capacitance CC12, one end of an additional capacitance Cad12 for increasing the charge holding capacity of the hold circuit H11 is connected, and the other end of the Cad12 is connected to the reference voltage generation circuit Gstd. The switch SW1
3, when SW14 is closed, Cad11, Ca
The d12 is refreshed by applying an equal charge to both ends.

The sample signal Ss and the hold signal Sh are input to the switches SW11 and SW12, respectively, and when Ss is input (when it becomes high level), SW11.
Is closed, and SW12 is closed when Sh is input (high level). Ss and Sh are input at the timing shown in the timing chart of FIG. 9, and in response thereto, the output Ds1 of the sample circuit S11 and the output of the hold circuit Dh1 are generated. When Ss is input when the value of Vin is a, a is held as Ds1, and when Sh is input next, a is transferred to the hold circuit and held as Dh1.

The first refresh signal Rf1 is the signal Rf1.
1 and Rf12, and the signal Rf11 is the switch SW1.
5, and the signal Rf12 is input to the switch SW13. Rf1 refreshes S11 at an intermittent timing of once for sample and hold a plurality of times, and Ss is input and sampling is started at the same time as the refresh is completed. Rf12 is input at the same time as Rf11 (at the same time, becomes high level), and the input ends after a while after the input of Rf11 ends. Here, in order to refresh the capacitance CC11, it is necessary to keep the potentials at both ends constant, but Rf11,
When RF12 is finished at the same time, CC1
There is a possibility that a charging voltage will be applied to unit 1. Maintaining Rf12 is effective in preventing this unexpected charging.

The second refresh signal Rf2 is the signal Rf2.
1 and Rf22, and the signal Rf21 is the switch SW1.
6, and the signal Rf22 is input to the switch SW14. Rf1 refreshes H11 at an intermittent timing of once for sample and hold a plurality of times, and Sh is input at the same time as the refresh is completed and holding is started. Rf22 is input at the same time as Rf21 (at the same time becomes high level), and the input ends after a short time after the input of Rf21 ends. Here, in order to refresh the capacitance CC12, it is necessary to keep the potentials at both ends constant, but Rf2
1. When RF22 is finished at the same time, C in transient state
The charging voltage may be applied to C21. Rf22
Continuation of is effective in preventing this unexpected charge.

FIG. 3 is a block diagram showing the sample and hold circuit SH2. The output of SH1 is switched to the switch SW21,
The output of the sample circuit S21 is connected to the switch SW22 and the coupling capacitance C through the coupling capacitance CC21.
It is connected to the hold circuit H21 via C22 in sequence.

The sample circuit S21 is a three-stage series MOS
The final stage output of the inverters INV11 to INV13 (FIG. 5) is connected to the first stage input via the feedback capacitance Cf21, and due to the amplification performance of INV11 to INV13, the inversion of Vin (power supply voltage −Vin) with good linear characteristics. Occurs in the output of S21. On the other hand, the hold circuit H21 is a three-stage series MOS similar to S21.
The final stage outputs of the inverters INV11 to INV13 (FIG. 5) are connected to the first stage input via the feedback capacitance Cf22, and when the switch SW22 is closed, the output of S21 is inverted, that is, Vin itself becomes H.
21 output.

Further, the sample and hold circuit SH2 includes capacitances CC21, CC22, Cf21 and Cf22.
Switches SW23 to SW26 for refreshing
When the switches SW25 and SW26 are closed, the same potential is applied to both ends of the capacitances Cf21 and Cf22, and refresh is performed. Switch S
W23 and SW24 apply the reference voltage to CC21 and CC22, and return the inputs of S21 and H21 to the reference voltage.

Switch SW21 and capacitance CC2
1 is connected to one end of an additional capacitance Cad21 for increasing the charge retention capability of the sample circuit S21, and the other end of the Cad21 is connected to the reference voltage generation circuit Gstd. On the other hand, between the switch SW22 and the capacitance CC22, one end of an additional capacitance Cad22 for enhancing the charge holding capability of the hold circuit H21 is connected, and the other end of the Cad22 is connected to the reference voltage generation circuit Gstd. The switch SW2
3, when SW24 is closed, Cad21, Ca
The d22 is refreshed by applying an equal charge to both ends.

The sample signal Ss is supplied to the switches SW21 and S21.
W22 is input to both, when Ss is input, SW2
Both SW1 and SW22 are closed. SH2 takes in the output of SH1 and holds it as output Ds2 in synchronization with the sample timing of SH1. As shown in FIG. 9, the timing of this output is delayed by one sample timing with respect to the sampling of SH1.

As shown in FIG. 4, outputs Dh1, Ds2 and signal Rf22 are input to the multiplexer MUX,
Dh1, Ds2 in response to changes in Rf22 high and low
Is output alternatively. The MUX has a pair of MOS switches MS1 and MS2, and Dh1 and Ds2.
Are input to MS1 and MS2, respectively. MS1 is closed when Rf22 is low level, MS2 is Rf
It is closed when 22 is at high level. Each MOS switch consists of nMOS and pMOS connected in parallel.
It is necessary to input a control signal of opposite polarity to the gate of OS. Therefore, Rf22 is input to the MOS inverter INV3, and signals of both positive and negative polarities are generated. From the above, S
When the hold circuit H11 for H1 is being refreshed, Ds2 is output from the MUX as the final output Dout, and then immediately returns to Dh1. As a result, as shown in FIG. 9, the final output Dout continuously outputs Vin without being affected by the refresh noise.

Inverters INV11 to INV shown in FIG.
A capacitor CL for obtaining a low-pass characteristic is connected to the output of the final stage inverter INV13
Balance resistances R1 and R2 between V12 and INV13
Is connected. By this, S11, S21, H1
1, the oscillation of S21 is prevented.

Switches SW11 to SW14, SW21 to
The SW24 is configured as shown in FIG. 6 and has the same MOS structure as the above.
A dummy transistor DT1 is connected to the subsequent stage of the switch MS3, and an inverter INV4 is provided to correspond to the nMOS and pMOS of the MOS switch.

The switches SW15, SW16, SW25,
The SW 26 is configured as shown in FIG. 7, and has the same MOS structure as that described above.
A dummy transistor DT2 is connected to the subsequent stage of the switch MS4, and an inverter INV5 is provided to correspond to the nMOS and pMOS of the MOS switch.

The reference voltage generation circuit Gstd is constructed as shown in FIG. 8, and the final stage output of the three-stage inverter of FIG. 5 is fed back to the first stage input via the feedback capacitance CF3, and further the switch SW3 of FIG.
The input and output of the three-stage inverter are directly connected by. As a result, the output of INV6 has a stable operating point Vdd.
It converges to / 2 and always outputs Vdd / 2.
In this case, CF3 contributes to the oscillation prevention of INV6.

[0027]

As described above, the sample and hold circuit according to the present invention is provided with a pair of sample and hold circuits and selects the outputs of these sample and hold circuits by a multiplexer. Since the output of the second sample-and-hold circuit is adopted during the operation, there is an excellent effect that the refresh noise can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sample hold circuit according to the present invention.

FIG. 2 is a block diagram showing a first sample hold circuit according to the first embodiment.

FIG. 3 is a block diagram showing a second sample and hold circuit in the embodiment.

FIG. 4 is a circuit diagram showing a round replexer in the embodiment.

FIG. 5 is a circuit diagram showing an inverter in the embodiment.

FIG. 6 is a circuit diagram showing a first switch in the example.

FIG. 7 is a circuit diagram showing a second switch in the example.

FIG. 8 is a block diagram showing a reference voltage generation circuit in the same embodiment.

FIG. 9 is a timing chart showing the operation of the embodiment.

FIG. 10 is a circuit diagram showing a conventional sample hold circuit.

[Explanation of symbols]

Cad11, Cad12, Cad21, Cad2
2. ． ． Additional capacitances CC1, CC2, CC11, CC12. ． ． Coupling capacitance CF11, CF12, CF21, CF22, CF
3. ． ． Feedback capacitances Ds1, Dh1, Ds2, Dout. ． ． Outputs DT1, DT2. ． ． Dummy transistors H1, H11, H21. ． ． Hold circuits INV1, INV2, INV11, INV12, INV
13, INV3, INV4, INV5, INV6. ． ．
MOS inverters MS1, MS2, MS3, MS4. ． ． MOS switch MUX. ． ． Multiplexers S1, S11, S12, S21. ． ． Sample circuit Sh. ． ． Hold signal SH1. ． ． First sample hold circuit SH2. ． ． Second sample hold circuit Ss. ． ． Sample signals SW1, SW2, SW3, SW11, SW12. ． ． Switches R1, R2. ． ． Equilibrium resistance Rf1. ． ． The first refresh signals Rf11, Rf12. ． ． Signal Rf2. ． ． Second refresh signals Rf21, Rf22. ． ． Signal Vin. ． ． Input voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayama Building Takayamauchi Co., Ltd.

Claims (5)

[Claims] 1. An input voltage, a sample signal, a hold signal, a first refresh signal, and a second refresh signal are connected, the input voltage is sampled by the sample signal, and the input voltage sampled by the hold signal is transferred. Holding, the first refresh signal is input at a predetermined frequency immediately before the sample signal to perform refreshing for sampling, and the second refresh signal is input at a predetermined frequency immediately before the hold signal to perform holding. A first sample-and-hold circuit adapted to perform refreshing for the purpose; and an output of the first sample-and-hold circuit, the sample signal, and the first refresh signal are connected, and a sample signal of the first sample-and-hold circuit is connected. Output is sampled and held And the first refresh signal is input at a predetermined frequency immediately before the hold signal,
A second sample and hold circuit adapted to perform refresh for sampling and holding;
When the outputs of the first and second sample and hold circuits are input and the second refresh signal is input to the first sample and hold circuit, the output of the second sample and hold circuit is selected, and at other times the first sample and hold circuit is selected. And a multiplexer for selecting the output of the hold circuit; 2. The first sample-hold circuit comprises: a first sample circuit formed by connecting the input and output of an odd-numbered series MOS inverter in series with a first feedback capacitance; and a first coupling capacitance connected to the first sample circuit. A first switch for connecting an input voltage via; a second switch connected to the output of the first sample circuit; and a second coupling capacitance connected to the output of the second switch; A first hold circuit formed by connecting the input and output of a MOS inverter with a second feedback capacitance; and a second coupling capacitance connecting the output of the second coupling capacitance to the first hold circuit; One switch is closed by the sample signal and the second switch is closed. The first sample circuit is refreshed by electric charge removal by the first refresh signal, and the first hold circuit is refreshed by electric charge removal by the second refresh signal. The sample hold circuit according to claim 1, wherein 3. A second sample-and-hold circuit comprising: a second sample circuit formed by connecting the input and output of an odd-numbered series MOS inverter in series with a third feedback capacitance; and a third coupling capacitance in the second sample circuit. A third switch for connecting the output of the first sample and hold circuit via the second switch; a second hold circuit in which the input and output of odd-numbered series MOS inverters are connected by a fourth feedback capacitance; and the output of the second sample circuit And a fourth coupling capacitance connecting the input to the second hold circuit, the third switch being closed by the sample signal, and the second sample circuit and the second hold circuit being the first refresh signal. That the refreshing by electric charge removal is performed by Sample and hold circuit of claim 1, symptoms. 4. The sample according to claim 1, wherein the first and second refresh signals are composed of a first signal for providing a period for removing charges and a second signal for providing a waiting period after removing charges. Hold circuit. 5. The sample-hold circuit according to claim 3, wherein a fourth switch is connected between the second sample circuit and the fourth coupling capacitance, and the fourth switch is closed by the sample signal. .