JPH0846629A - Atm network interface module - Google Patents

Abstract

PURPOSE:To provide the buffer management system in which an execution throughput of a high order layer packet level is improved by the addition of hardware as less as possible in the ATM network interface module. CONSTITUTION:A cell buffer to store ATM cells for the recomposition of a higher-layer packet is built up in a main memory 23 of a host work station 20 to which an ATMNIC (ATM network interface card) 10 is mounted. Furthermore, a VC dependent cell abort management table in which several hundreds of cells ira terms of VC number are registered is provided to a status storage section 12 in the ATMNIC 10. A 'reception enable' or 'reception disable' is set to the management, table depending on a buffer occupied amount. The reception processing section 12 receives an ATM cell of a logic channel (VC) when the setting of the management table indicates 'reception enable' and aborts the ATM cell of the logic channel (VC) when the setting of the management table indicates 'reception disable'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is located between an ATM layer, which is the lowest layer of a communication protocol layer in an ATM communication network, and a network layer, and is a data format conversion for connecting upper and lower layers. The present invention relates to an ATM network interface module that performs actual processing of an AAL (ATM Adaptation Layer) layer that plays a role of processing and address conversion processing, and in particular, the effective throughput of upper layer packets can be improved by adding as little hardware as possible. It relates to an ATM network interface module.

[0002]

2. Description of the Related Art An ATM network interface module is mounted on a host such as a workstation or an internet device via a bus I / F to provide an ATM network interface module.
It undertakes the transfer of communication data between the transmission method and the upper protocol layer.

A card type module is known as an ATM network interface module, and FIG. 11 shows an example of the configuration of a conventional ATM network interface card (ATMNIC). AT
As M network interface module,
Since ATMNIC is typical, hereinafter, in the present specification, “ATMNIC” is used as a phrase including the meaning of ATM network interface module in general.

In FIG. 11, a portion 10 surrounded by a broken line
0 is ATMNIC, the other part 11 surrounded by a broken line
0 is the mounted host workstation. ATMN
The IC 100 includes a local memory 102 that stores ATM cells for packet reassembly, a reception processing unit 103 that executes processing of the ATM layer and AAL layer and cell discard processing, a physical layer I / F 104, and a local area within the ATM NIC. Bus 1
01 and a bus I / F 105 connected to the system bus 111 in the host workstation 110, which are interconnected via the local bus 101.

A cell buffer memory is provided in the local memory 102. As shown in FIG. 12, the received ATM cells are accumulated in the cell buffer memory in the local memory 102 while being subjected to the AAL layer processing and the ATM layer processing until the ATM cells for the packets are prepared. Then, when all the cells are gathered and the reception processing is completed, the packet is passed to the upper protocol layer. Here, even if one cell is missing, the packet is not passed to the upper protocol layer and AAL
Discarded in layers.

[0006]

Conventionally, as described above, a cell buffer for accumulating ATM cells for reassembly into an upper layer packet has been realized in the local memory 102 in the ATM NIC. However, the amount of hard memory that can be implemented in the ATMNIC is small, and
The received packet is assembled in the local memory 102 connected to the local bus 101 in the MNIC 100, and then the upper layer packet is transferred to the main memory 113 of the host 110 via the local bus 101 to the CPU 112 of the host. Since the packet delivery of the local bus 101 was realized (see FIG. 12), the local bus 101
However, the capacity could not be sufficient, and sufficient processing capacity could not be achieved as ATMNIC.

Conventionally, no special processing is performed even if a buffer overflow occurs in the ATMNIC. Therefore, the ATM cell group remains in the cell buffer in an incomplete form, and the buffer area is unnecessarily occupied until it is discarded in the subsequent reception processing. This inefficient use of the cell buffer causes cell loss of other upper layer packets one after another, resulting in lower execution throughput at the upper layer packet level.

The present invention has been made in view of the above points, and it is an object of the present invention to improve the suppression of effective throughput, which has been a problem in the conventional method, by adding a minimum amount of hardware.

[0009]

In order to solve the above problems, in the present invention, an ATM network interface module is provided with a cell buffer memory for accumulating ATM cells for reassembly into AAL packets.
It is configured to be installed in the main memory in the workstation or the Internet device in which the ATM network interface module is mounted.

[0010]

Operation: The main memory of the workstation is ATM
Since the amount of memory is much larger than that which can be physically mounted on the NIC, the frequency of cell discard due to the absolute shortage of the cell buffer can be reduced. Also, the ATM cell remains
Since the packet is transferred to the host side, compared to the conventional case of transferring in packet units (see FIG. 12), no special packet transfer processing is involved in transferring the management of the received packet to the CPU of the host, and therefore, that much Therefore, the effective processing amount of the reception processing unit of the ATMNIC can be reduced and the congestion of the local bus can be reduced. By reducing the load on the hardware configuring the ATMNIC, the absolute throughput of the ATMNIC can be significantly improved.

[0011]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a basic block diagram of an ATMNIC according to an embodiment of the present invention. A portion 10 surrounded by a broken line is a basic configuration diagram of the ATMNIC according to the present invention, and another portion 20 surrounded by a broken line is a mounted workstation. In ATMNIC10, ATM layer and AAL
A reception processing unit 12 that executes layer processing and cell discard processing,
The physical layer I / F 13 and the bus I / F 14 (connecting the local bus 11 in the ATMNIC and the system bus 21 in the host workstation 20) are the local bus 11
Are interconnected via. Furthermore, a status storage unit 15 in which a VC-based cell discard management table (to be abbreviated as “management table” hereinafter), which will be described later, is stored, and a buffer occupancy that can monitor how much the buffer amount is occupied at an arbitrary time point A quantity counting unit 16 is provided. The host workstation 20 is a CP for simplicity.
It is shown in a configuration including only the U22 and the main memory 23.

In the main memory 23 of the host workstation 20, there is A for reassembly into upper layer packets.
A cell buffer memory (cell buffer 40 in FIGS. 5 to 10) for accumulating TM cells is set. The occupied amount of the cell buffer memory is detected by the buffer occupied amount counting unit 16.

FIG. 2 shows an AT input to the ATM NIC 10.
The ATM cell, which indicates the path of the M cell and is input via the physical layer I / F 13, is received in the reception processing unit 12 and then stored in the main memory 23 of the host 20 via the bus I / F 14. Accumulated. Then, when all the ATM cells forming the upper layer packet are gathered and the reception processing is completed, the reception processing unit 12 sends a packet reception end notification to the CPU 22 of the host 20 to manage the received packet to the CPU 22 of the host 20. Pass to.

FIG. 3 shows an example of the configuration of the VC-based cell discard management table 30 stored in the status storage unit 15. VC
The separate cell discard management table 30 is a logical channel (VC).
Is provided with a column (1 bit) indicating an attribute corresponding to the column for registering the identifier (VCI) of the
The ATM cell of indicates whether reception is possible (bit “0”) or reception is not possible (bit “1”).

The number of entries in the management table 30 is about several hundred. This is defined by the ATM transmission method 1
Based on the consideration that, of the 2-bit VCI (4096), only a few hundred are used at the same time.

In the initial state, nothing is registered in the management table 30. When an ATM cell arrives from a new VC that has no entry in the management table 30, the ATM cell
If the cell is judged to be the first cell of the upper layer packet (AAL packet) and the occupied amount of the cell buffer at that time is less than or equal to the threshold value, the VCI and attribute "0" (receivable), If the occupied amount of the cell buffer exceeds the threshold value, the VCI and the attribute “1” (not receivable) are displayed in the management table 30.

When cell discard due to buffer overflow occurs, the attribute of the VC column corresponding to the discarded cell in the management table 30 is set to "1" (not receivable).
Set to.

All ATMs arriving at ATMNIC10
For a cell, the cell discard management table for each VC is referred to based on the VCI, and when the attribute is “0” (reception possible), the cell is stored as it is, while the attribute is “1” (reception). If not), the reception processing unit 12
Discards the ATM cell.

EOP (En indicating the end of the AAL packet
d of Packet) cell arrives, the entry of the VC in the management table 30 is deleted to increase the free area of the management table 30 for another new VC registration. If an ATM cell from a new VC arrives when there is no free area in the management table 30, the A from the VC is
All TM cells have to be stored in the cell buffer unconditionally, but since the management table 30 determines that there is no entry for the arriving cell immediately after the management table 30 becomes empty, it is registered in the table, although it is in the middle. The effect can be minimized. Further, the number of possible entries in the management table 30 is optimized so that the frequency of occurrence of such a situation can be suppressed to the utmost limit. As described above, in the configuration according to this embodiment, the number of entries in the management table 30 is about several hundreds, but this can be implemented by adding a small capacity hard memory.

In the management table 30 of the embodiment, only the VC currently being received is registered so that the number of entries is suppressed to about several hundreds. Of course, the number of entries is increased so that all VCs are registered in advance. You may

Next, the operation of the embodiment will be described with reference to the flowchart of FIG. First, when an ATM cell is input to the ATMNIC 10 (F1), the VC-specific cell discard management table 30 in the status storage unit 15 is referred to for that VC (F2), and it is checked whether or not there is an entry in the management table 30 (F3). ). If the entry is made, the attribute is next checked (F4). If the attribute is "0" (reception possible), the occupied amount of the buffer memory set in the main memory 23 is measured (F5), and the buffer is If not full (F
6) The reception process is performed as it is (F7), and the result is stored in the cell buffer (F8). Next, it is checked whether the arrived cell is an EOP cell (indicating the end of the AAL packet) (F9), and if it is an EOP cell, the entry of the corresponding VC is deleted from the management table 30 (F10).

On the other hand, in step F4, when the attribute is "1" (not receivable), the ATM processing cell discards the ATM cell. In step F6,
Even when the buffer is full, the attribute is changed to "1" (not receivable) (F12) and the cell is discarded (F1).
3). This allows the table 30 to be registered for new VC registration.
The free space of. At this time, if there are ATM cells already stored in the buffer memory, they are also invalidated and are discarded.

In step F3, the management table 30
If it is an ATM cell of a new VC having no entry in, the ATM cell may be regarded as the head cell of the upper layer packet. Therefore, next, it is checked whether or not there is a space in the management table (F14), and if there is a space, the occupied amount of the cell buffer at that time is measured (F15). If the buffer occupancy is less than or equal to the threshold value (F16), it is determined that all ATM cells for the packet can be accommodated, and the VCI and attribute "0" (receivable) are registered in the table 30 (F1).
7). If the occupied amount of the cell buffer is equal to or larger than the threshold value (F16), it is determined that the cell discard will occur due to the buffer overflow, and the VCI and the attribute "1" (not receivable) are registered in the management table 30. Do (F
18).

In step F14, the management table 3
If there is no free area of 0, all ATM cells from that VC are unconditionally subjected to the reception processing (F7) and stored in the cell buffer (F8), but as soon as the table area becomes empty, the area immediately after that becomes available. It is determined that there is no entry for the arriving cell, and it is registered in the management table 30 even though it is in the middle, so that the influence can be minimized.

As described above, in the present invention, the ATM cell buffer is used for reassembly of the upper layer packet,
It is constructed in the main memory 23 of the workstation 20 in which the MNIC 10 is mounted. Since the main memory 23 of the workstation 20 is much larger than the memory amount that can be physically installed in the ATMNIC 10, the frequency of cell discard due to the absolute shortage of the cell buffer can be reduced, and the reception processing (the processing of the ATM layer) can be reduced. , AAL layer processing), any large network load can be accommodated as long as the processing speed of the reception processing unit 12 allows. Further, since a large capacity hard memory is not installed in the ATMNIC 10, there is an advantage that the ATMNIC can be manufactured at a very low price.

The ATM cell route of the above embodiment has already been described with reference to FIG. 2. However, comparing this with the cell transfer route of the conventional configuration shown in FIG. 12, the management of the received packet is controlled by the CPU 22 of the host 20. Since no special packet transfer processing is involved when the data is delivered to the device, the effective processing amount of the reception processing unit 12 can be reduced and the congestion of the local bus 11 can be reduced accordingly. By reducing the load on the hardware configuring the ATMNIC 10, the ATMNI
The absolute throughput of C10 can be greatly improved.

Further, according to the above-described embodiment, the VC-based cell discard management table 30 for setting the availability of reception for each logical channel (VC) based on the buffer occupation amount is provided in the status storage unit 1.
For a VC that is set to 5 and has an attribute of “1” in the management table 30, the reception processing unit 12 discards the corresponding cell before inputting to the buffer. As a result, the ATM cells forming useless packets including cell loss do not waste the network bandwidth unnecessarily, and the cell discard is concentrated on the packets of a specific VC, and the cell discard extends to a large number of packets. It is possible to effectively use the finite cell buffer in the ATM switch by preventing the above, and to improve the effective throughput at the upper layer packet level.

Further, if the buffer occupancy at the time when the leading ATM cell forming the upper layer packet (AAL packet) arrives exceeds the threshold value, the EOP cell determines the ATM cell forming the packet. The reception processing unit 12 discards all the packets until they arrive. This means that this packet is expected to lose ATM cells due to buffer overflow in the future, and the packet is discarded in advance, but this will cause cell loss, which is worthless. Such a packet does not occupy the buffer even for one cell, and it is possible to improve the utilization efficiency of the buffer and increase the effective throughput at the upper layer packet level.

Next, a concrete case is shown in FIGS. First, FIG. 5 and FIG. 6 show an operation example when an ATM cell having a VC having an entry in the management table 30 arrives at the ATMNIC 10. FIG. 5A shows a state when an ATM cell of VC1 having an entry of "0" (receivable) in the cell discard management table for each VC 30 arrives. Since the attribute is receivable, the upper layer packet sent by VC1 has no cell loss yet, and it is determined that the ATM cell is valid, and the reception processing unit 12 performs reception processing, and then the cell buffer 40 Accumulate (Fig. 5
(B)).

In FIG. 6A, "1" is added to the management table 30.
The ATM cell of VC2 that has the entry of (reception not possible) is
It is a state diagram when it arrives at TMNIC10. The reason why the attribute cannot be received is that cell loss has already occurred in the upper layer packet sent by VC2, or the buffer occupancy when the leading cell arrives is above the threshold value. Anyway, this VC2 A
Since the TM cell is completely invalid, it is discarded by the reception processing unit 12 (FIG. 6 (b)).

In FIGS. 7 and 8, an ATM cell having a VC having no entry in the cell discard management table for each VC 30 is an ATMN.
An example of the operation when arriving at the IC 10 is shown. First, referring to FIG. 7, FIG. 7A shows a state in which an ATM cell of VC3 having no entry in the management table 30 arrives at the ATMNIC 10 when the occupied amount of the cell buffer 40 is less than or equal to the threshold value. There is. V corresponding to the management table 30
Since there is no entry of C, it is determined that this cell is the head cell of the upper layer packet, and the cell buffer 40
Since there is a sufficient free space in the network, it can be assumed that all ATM cells for packets can be accommodated.
In (b)), the VCI (VC3) and the attribute “0” (receivable) are registered in the cell discard management table for each VC 30,
The head cell is stored in the cell buffer 40. As long as cell loss due to buffer overflow does not occur, all VC3 ATM cells arriving thereafter will be stored in the cell buffer 40.
It is accumulated in and is exchanged.

FIG. 8A shows a state in which an ATM cell of VC4 having no entry in the management table 30 arrives at the ATMNIC 10 when the occupied amount of the cell buffer 40 is equal to or more than the threshold value. Since there is no corresponding VC entry in the management table 30 as in FIG.
It is determined that the cell is the head cell of the upper layer packet. However, since the occupancy of the cell buffer 40 is equal to or greater than the threshold value, it is determined that the upper layer packet composed of this head cell will eventually contain a cell loss due to buffer overflow, and the VCI (VC) is stored in the management table 30.
4) and the attribute "1" (reception not possible) are registered, and the leading cell is discarded by the reception processing unit 12 (FIG. 8B). The reception processing unit 12 discards and discards all the ATM cells of the VC 4 that arrive thereafter.

FIG. 9A shows a state in which when the cell buffer 40 is full, an ATM cell of VC5 having an entry of “0” which can be received in the management table 30 has arrived at the ATMNIC 10. Since the VC 5 is receivable, the ATM cell is tried to be stored in the cell buffer 40, but it is unavoidably discarded because the cell buffer 40 is full. This single cell loss causes VC5
Since the upper layer packet of is completely invalidated, the ATM cell of VC5 already accumulated in the cell buffer 40 is discarded and the bit of the VC5 column of the management table 30 is changed to “1” (not receivable). Then, all the ATM cells of the VC5 that arrive thereafter are discarded by the reception processing unit 12 (FIG. 9B).

In FIG. 10A, the EOP cell of the VC 6 having the entry of “1” which cannot be received in the management table 30 is AT.
The state at the time of arrival at MNIC 10 is shown. Since the attribute cannot be received, it can be seen that all the ATM cells of this VC have been discarded by the reception processing unit 12 until now. The arrival of the EOP cell means that all the cells for the packet have arrived with respect to this VC, and that the ATM cell of the VC6 that follows the VC is the head cell of another upper layer packet. Therefore, as shown in FIG. 10B, the entry of the VC6 is deleted from the management table 30 in order to increase the free capacity of the management table 30, and this is executed for the ATM cell (head cell) of the VC6 that comes next. To prepare for cell discard control based on buffer occupancy.

[0035]

As described above, according to the present invention,
In the ATM network interface module, the effect that the effective throughput can be greatly improved is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of an ATM network interface module according to the present invention.

2 is an ATM cell ATMNI in the embodiment of FIG. 1;
It is a figure explaining the path | route from arriving at C to accumulating in a cell buffer.

3 is a VC provided in a status storage unit of the embodiment of FIG.
It is a block diagram of another cell discard management table.

4 is a flowchart showing a processing procedure for an ATM cell in the embodiment of FIG.

FIG. 5 is a case where a VC ATM cell having an entry of “0” in the cell management table for each VC in the embodiment of FIG.
It is a state diagram explaining the processing procedure when it arrives at TMNIC.

FIG. 6 is a state diagram illustrating a processing procedure when an ATM cell of a VC having an entry of unreceivable “1” in the VC-specific cell management table in the embodiment of FIG. 1 arrives at ATMNIC.

7 is a state for explaining a processing procedure when an ATM cell of a VC having no entry in the VC-specific cell management table arrives at the ATMNIC when the occupied amount of the cell buffer is equal to or less than the threshold value in the embodiment of FIG. 1; It is a figure.

8 is a state for explaining a processing procedure when an ATM cell of a VC having no entry in the VC-specific cell management table arrives at ATMNIC when the occupied amount of the cell buffer is equal to or more than the threshold value in the embodiment of FIG. 1; It is a figure.

FIG. 9 is a state diagram illustrating a processing procedure when an ATM cell of a VC having an entry of “0” which can be received in the VC-specific cell management table when the cell buffer is full in the embodiment of FIG. 1 arrives at ATMNIC. Is.

10 is a state diagram illustrating a processing procedure when an EOP cell arrives in the embodiment of FIG.

FIG. 11 is a configuration diagram of a conventional ATM network interface module.

FIG. 12 is a diagram showing a path from the arrival of an ATM cell to the storage in a cell buffer in the configuration of the conventional ATM network interface module.

[Explanation of symbols]

10,100 ATM network interface card (ATMNIC) 11,101 Local path 12,103 Reception processing unit 13,104 Physical layer I / F 14,105 Bus I / F 15 Status storage unit 16 Buffer occupancy counting unit 20,110 Host Workstation 21,111 System bus 22,112 CPU 23,113 Main memory 30 Cell discard management table for each VC 40 Cell buffer

Claims (3)

[Claims] 1. A data format conversion process, an address conversion process, etc. for connecting the two layers, which is located between the ATM layer, which is the lowest layer of the communication protocol layers in the ATM communication network, and the network layer. In the ATM network interface module that executes the actual processing of the AAL layer that plays the role of, a cell buffer memory that stores ATM cells for reassembly into an AAL packet is used as a workstation or an internet device in which the ATM network interface module is mounted. ATM characterized by being installed in the main memory inside
Network interface module. 2. The ATM network interface module according to claim 1, wherein a buffer occupation amount counting means for counting the occupation amount of ATM cells in the cell buffer memory, and a buffer occupation amount measured by the buffer occupation amount counting means. Based on the logical channel (V
C) Cell-by-VC discard management table for setting acceptance / rejection for each C), and if the setting of the management table is “receivable”, the ATM cell of the relevant logical channel (VC) is received, and “reception not possible” For example, an ATM network interface module provided with a reception processing unit that discards the logical channel (VC). 3. The management table is configured to register only a logical channel (VC) currently being received, and in the initial state, nothing is registered in the management table, and a new logic having no entry in the management table. Channel (VC) to A
When the TM cell arrives, it is determined whether or not the new logical channel (VC) can be received based on the buffer occupation amount at the time of arrival, and the logical channel (V
The ATM network interface module according to claim 2, wherein the VC identifier of C) and the determined availability of reception are displayed.