JPH0843491A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the test time of a semiconductor integrated circuit device provided with a memory and to reduce costs for its test. CONSTITUTION:A first selector circuit 21 is controlled by a testmode signal S, the signal of an internal circuit is selected in an ordinary operation, and test data is selected in a test operation so as to be written into a memory 22. The operation of the memory is controlled by a memory control circuit 23. The test data which has been read out from the memory and a control signal which is output from the memory control circuit are supplied to a second selector circuit 24, the control signal of the memory control circuit is selected so as to be output from an external output terminal 25 in the write operation of the test data to the memory by the control of a read/write signal R/W which is output from the memory control circuit. While the test data is being written into the memory, the control signal of the memory control circuit is output from the external output terminal so as to be capable of being monitored. As a result, the test time of a semiconductor integrated circuit device can be shortened, and its costs can be lowered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a memory, and more particularly to a memory test.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device having a memory, a memory and a control circuit of this memory are constructed as shown in FIG. 2 for testing. In FIG. 2, 11 is a first selector circuit, 12 is a memory, 13
Is a memory control circuit, 14 is a second selector circuit, and 15 is an external output terminal. A signal and test data from the internal circuit of the semiconductor integrated circuit device are supplied to the selector circuit 11, and one signal is selected by the test mode signal S1 instructing the test mode for the memory and written in the memory 12. There is. The operation of the memory 12 is controlled by a control signal output from the memory control circuit 13.
The data read from the memory 12 is supplied to the internal circuit and also to one input terminal of the selector circuit 14. The output signal of the memory control circuit 13 is supplied to the other input terminal of the selector circuit 14 and is controlled by a test mode signal S2 for instructing a test mode for the memory control circuit, so that one is selected and externally output. An output is made from the output terminal 15.

In the above structure, during normal operation, the memory test mode signal S1 becomes "0" level (or "1" level), and the selector circuit 11 selects the signal from the internal circuit to cause the memory 12 to operate. Written in. At this time, the operation of the memory 12 is controlled by the memory control circuit 13, and the data read from the memory 12 is supplied to the internal circuit.

On the other hand, during the test operation of the memory 12, the test mode signals S1 and S2 both become "1" level (or "0" level), the test data is selected by the selector circuit 11, and the control of the memory control circuit 13 is performed. Is written in the memory 12. When the writing of the test data to the memory 12 is completed, the memory control circuit 13 is
Under the control of, the reading of test data from the memory 12 is started and supplied to the selector circuit 14. Then, the test data read from the memory 12 is selected by the selector circuit 14, and the test data is output from the external output terminal 15. This data is monitored by an IC tester or the like to determine the quality of the memory 12.

When the memory control circuit 13 is tested, the test mode signal S1 is at "1" level (or "0" level) and the test mode signal S2 is at "0" level (or "1" level). . As a result, the test data is selected by the selector circuit 11 and written in the memory 12 under the control of the memory control circuit 13.
At this time, the selector circuit 14 causes the memory control circuit 13
The control signal output from the external output terminal 15 is selected.
Output from By monitoring this control signal with an IC tester or the like, it is determined whether the memory control circuit 13 is operating normally.

However, in the above configuration, in order to test the memory 12 and the memory control circuit 13,
It is necessary to repeat the operation of writing the test data in the memory 12 and reading the test data. For this reason, if the large-capacity memory 12 is built in the semiconductor integrated circuit device as in recent years, the test time becomes long, which eventually leads to an increase in the cost of the semiconductor integrated circuit device.

[0007]

The conventional semiconductor integrated circuit device having the built-in memory as described above has a problem that the test time is long and the cost is increased. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device that can reduce the test time and the cost for the test.

[0008]

A semiconductor integrated circuit device of the present invention is switch-controlled by a test mode signal indicating a test mode, selects a signal of an internal circuit during a normal operation, and selects test data during a test operation. First
Switching means, a memory for storing the signal or test data of the internal circuit selected by the first switching means, a memory control means for controlling the operation of this memory, the data read from the memory and the above A control signal supplied from the memory control means to the memory is supplied, and switching control is performed by a part of the control signals of the memory control means, so that when writing test data to the memory, the memory control means Second switching means for selecting the control signal and outputting it from an external output terminal, and selecting the test data read from the memory cell when reading test data from the memory and outputting the test data from the external output terminal. It is characterized by doing. A read / write signal of the memory can be used as a part of the control signal of the memory control means for controlling the second switching means.

[0009]

According to the above construction, the control signal of the memory output from the memory control means is selected by the second selection means and output from the external output terminal while the test data is being written in the memory. Therefore, the test data can be written in and read from the memory only once when the memory test and the memory control means test are performed. This will reduce the test time,
Cost reduction during testing is possible.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an extracted memory and its peripheral circuits in a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, 21 is a first selector circuit, 22 is a memory, 23 is a memory control circuit, 24 is a second selector circuit, and 25 is an external output terminal. A signal and test data from the internal circuit of the semiconductor integrated circuit device are supplied to the selector circuit 21, and one signal is selected by the test mode signal S for instructing the test mode to select the memory 2
Write to 2. At the time of this writing, the operation of the memory 22 is controlled by the control signal output from the memory control circuit 23. The data read from the memory 22 is supplied to the internal circuit and also to one input end of the selector circuit 24. A control signal output from the memory control circuit 23 is supplied to the other input terminal of the selector circuit 24, and a part of the control signal output from the memory control circuit 23, for example, read / write of the memory 22.
Write signal (read / write signal) R / W ^- ( ^- added after the symbol means inverted signal, that is, bar)
When the data is written in the memory 22 (when the read / write signal is at “0” level), the control signal output from the memory control circuit 23 is selected and output from the external output terminal 25. , When reading data from the memory 22 (when the read / write signal is at "1" level)
The test data read from the memory 22 is selected and output from the external output terminal 25.

In the above structure, the test mode signal S is at "0" level (or "1") during normal operation.
Level), and the signal from the internal circuit is selected by the selector circuit 21 and written in the memory 22. At this time, the operation of the memory 22 is controlled by the memory control circuit 23. The data read from the memory 22 is supplied to the internal circuit.

On the other hand, during the test operation of the memory 22, the test mode signal S becomes "1" level (or "0" level), the test data is selected by the selector circuit 21, and the memory 22 is controlled by the memory control circuit 23.
Is written to. While the test data is being written in the memory 22, the output signal of the memory control circuit 23 or the control signal output from the memory control circuit 23 such as an address counter in the memory control circuit 23 is output to the external output terminal 2
Connect an IC tester to 5 and monitor. Then, when the writing of the test data to the memory 22 is completed, the reading of the test data from the memory 22 is started by the control of the memory control circuit 23 and is supplied to the selector circuit 24. Then, the test data read from the memory 22 is selected by the selector circuit 24, and the test data is output from the external output terminal 25. This test data is monitored by an IC tester or the like to determine the quality of the memory 22.

According to the above configuration, the test of the memory control circuit 23 can be performed when the test data is written in the memory 22, so that the test time can be shortened and the test cost can be reduced. In particular, the test time can be relatively shortened as the number of words in the memory (the number of written data) increases.

In the circuit shown in FIG. 1, an external pin dedicated to the test may be provided for inputting the test mode signal S, or the external pin may be shared with other signals. . Alternatively, the external pin may not be provided, but the external mode may be connected to a bus provided in the internal circuit of the semiconductor integrated circuit device, and the test mode signal may be input via this bus. This bus can be either serial or parallel.

[0015]

As described above, according to the present invention, it is possible to obtain the semiconductor integrated circuit device which can reduce the test time and the cost for the test.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory and peripheral circuits thereof for explaining a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory and peripheral circuits thereof for explaining a conventional semiconductor integrated circuit device.

[Explanation of symbols]

21 ... First selector circuit, 22 ... Memory, 23 ... Memory control circuit, 24 ... Second selector circuit, 25 ... External output terminal, S ... Test mode signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyuki Oishi 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Yokohama office

Claims (2)

[Claims] 1. A first switching means which is switch-controlled by a test mode signal indicating a test mode, selects a signal of an internal circuit during a normal operation and selects test data during a test operation, and the first switching means. A memory for storing the signal or test data of the internal circuit selected in, and a memory control means for controlling the operation of this memory,
The data read from the memory and the control signal supplied to the memory from the memory control means are supplied,
Switching control is performed by a part of the control signals of the memory control means, so that when the test data is written in the memory, the control signal of the memory control means is selected and output from the external output terminal. And a second switching means for selecting the test data read from the memory cell and outputting the test data from the external output terminal when the test data is read from the semiconductor integrated circuit device. 2. The semiconductor integrated device according to claim 1, wherein a part of control signals of the memory control means for controlling the second switching means are read / write signals of the memory. Circuit device.