JPH0834510B2 - Redundant system of electronic exchange - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to an electronic exchange, and more particularly to a duplex system for coping with a failure occurrence.

(Prior Art) Since a telephone switchboard is required to have high reliability, various duplex systems for coping with a failure have been proposed. As a conventional duplication method, for example, as shown in FIG. 19, by duplicating the processor (CPU) and the memory, preparing all combinations of the processor and the memory, and switching the combinations when a failure occurs, As shown in FIG. 20, when a failure occurs in any of N processors having a specific function, there is an N + 1 method in which an extra processor is switched to. Of course, in addition to the functional devices such as the processor and the memory, the power supplies for supplying power to these are also duplicated.

However, each of these conventional duplex systems requires complicated hardware for bus switching control when a failure occurs. In addition, each of the redundant power supplies requires an extremely large capacity to supply power to all the functional devices such as the redundant processors and memories.

(Problems to be Solved by the Invention) As described above, the conventional duplex system has a problem in that the hardware becomes complicated and the power supply capacity also becomes large, so that the apparatus becomes large in size and expensive.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a duplex system of an electronic exchange capable of coping with the occurrence of a failure with a simple configuration and reducing the power supply capacity.

[Structure of the Invention] (Means for Solving Problems) In the present invention, among a plurality of substrates provided with various functional devices mounted in a shelf together with a power source,
When only a first-type board group provided with a functional unit such as a processor, a memory, and a time switch for converting a time-division time slot that directly controls the system down of the electronic exchange when a failure occurs, is duplicated, Each of the duplicated groups is connected to the first and second common buses, respectively. On the other hand, the second type board group provided with a functional device such as a processor that manages application services such as call management that does not directly contribute to the system down of the electronic exchange even if a failure occurs is not duplicated. One of the two common buses is connected to the third common bus which is selectively connected by the bus switch group. Then, the power supplies are duplicated, and each of the power supplies individually supplies power to the duplicated first type substrate group and shares power to the second type substrate group. Is connected to. Further, the duplicated first-type board group is provided with a failure detection unit for each board, and is connected to the third common bus via one of the first and second common buses. When at least one of the groups of one of the groups is detected by the failure detecting means, the occurrence of the failure is interrupted to the other of the first type board groups. The other group, which has received the fault occurrence notification, controls the switching of the bus switch group, so that the other group is connected to the third common bus in place of the one group.

(Operation) When a failure occurs in any one of the functional devices in one of the first-type substrate groups connected to the second-type substrate group, the first and second common buses are switched and the first and second common buses are switched. 3 common bus, so that the whole other group of the first type substrate group is connected to the second type substrate group instead of the whole one group, and system down is avoided. It

In this case, the bus switching control upon occurrence of a failure detects the failure occurrence of the operating group of the first type board group by the failure detecting means provided in association with each board, and detects the occurrence of the failure. This is performed by notifying a waiting group of one type of board group by interruption and switching the bus switch group by the waiting group which has received this notification. That is, fault monitoring and bus switching control are performed by the first-type board group itself. For this reason, compared to the case where a switching control device is provided separately from the first type board group and the switching control device monitors a fault in the operating group and switches the bus switch group when a fault is detected, The structure is simplified, and thus the cost of the device can be reduced.

In addition, it is sufficient for each of the redundant power supplies to have a capacity capable of supplying electric power to one group of the redundant type 1 board group and the functional device in the type 2 board group. The capacity may be smaller than that in the case of supplying power to the device.

(Embodiment) FIG. 1 is a schematic configuration diagram of an electronic exchange according to an embodiment of the present invention, in which a common control shelf 1 and a plurality of line / trunk shelves 2a to 2n are stacked as shown in FIG. It has a structure.

In the common control shelf 1, a main CPU (Mcpu) card 11 that manages exchange processing and maintenance, an application CPU (Acpu) card 12 that manages various applications such as call management, messaging, and directory, and these main CPU card 11 and applications. CPU card 12
Communication between the line / trunk (L / T) card 21 and the local CPU (Lcpu) card 13 that performs input / output level conversion in software, and the time switch (TSW) that converts time-division time slots. A card (card-shaped circuit device) that constitutes a common control unit such as the card 14 is mounted. In the present invention, the various cards 11 to 14 in the common control shelf 1 are collectively referred to as a common control card. Further, the processors in the common control cards 11 to 14 can communicate with each other via the common memory 16 connected to the common bus 15.

On the other hand, in the line / trunk shelves 2a to 2n, line / trunk (L / T) cards 21 to which subscriber terminals such as telephones and data terminals are connected are mounted according to the number of lines. Common control shelf 1 and line / trunk shelf 2a
Between 2n, a control highway 3 for serial transmission including a data highway for transmission from the local CPU card 13 to the line / trunk card 21 and a data highway for reception from the line / trunk card 21 to the local CPU card 13, The time switch card 14 and the line / trunk card 21 are connected by a PCM highway 4 for PCM time slot replacement.

Next, each part of FIG. 1 will be described in detail. FIG. 3 shows the internal structure of the line / trunk card 21, particularly the line / trunk card connected to the digital telephone 31. In Figure 3, the digital telephone LSI (DTLS
Reference numeral I) 32 is an LSI for controlling communication between the digital telephone 31 and a port / trunk card and a port controller (PC) 33 which is composed of a CPU for controlling telephones, office lines and the like connected to the line / trunk card. An interface LSI (ILSI) 34 is an LSI that controls communication between the port controller 33 and the local CPU 13 (FIG. 1) in the common control shelf 1, and operates in slave mode as described later. To do.

4 shows the local CPU card 1 in the common control shelf 1.
The internal structure of 3 is shown. In FIG. 4, the interface LSI (ILSI) 41 is the interface LSI in FIG.
It has the same configuration as 34, but has a different mode setting input from the outside, and operates in master mode as described later. The local memory 42 is for storing programs and data for operating the local CPU (Lcpu) 43, and the buffer 45 is the common bus 15 and the local CPU card 1
When the local CPU 43, which is for connecting to or disconnecting from the local bus 46 in 3, accesses the common bus 15, when the decoder 44 detects an address assigned to the common memory 71 (described later), The buffer 45 is turned on to connect the common bus 15 and the local bus 46. Note that different addresses are assigned to the local memory 42 and the common memory 71.

FIG. 5 shows the main CPU card 11 in the common control shelf 1.
The internal structure of is shown. Main CPU card 11 as shown
Has almost the same configuration as the local CPU card 13 shown in FIG. 4, and has a local memory 51, a main CPU (Mcpu) 52, a decoder 53, a buffer 54 and a local bus 55. However, since the main CPU card 11 is not connected to the control highway 3, it does not include an interface LSI.

Although not shown, the application CPU card 12 in the common control shelf 1 is also the main CPU shown in FIG.
It has the same structure as the card 11.

FIG. 6 shows the internal structure of the time switch card 14 in the common control shelf 1, which has a time switch controller and time switch 61, a decoder 62 and a buffer 63. The time switch card 14 is designed to be accessed only by the main CPU 52. Specifically, the decoder 62 monitors whether the address on the common bus 15 matches the address for time switch control, and it matches. Only when the buffer 63 is turned on, the time switch controller and the time switch 61 are connected to the common bus 15
Connect to.

FIG. 7 shows a common memory card 16 in the common connection shelf 1.
The internal configuration of FIG. 6 has a common memory 71, a decoder 72 and a buffer 73, and the method of accessing the common memory 71 is the same as the above-described access method in the time switch card 14 shown in FIG.

Next, referring to FIG. 8, a processor in the common control card in the common control shelf 1, for example, the local CPU 43 in the local CPU card 13 shown in FIG. 4 and the line / trunk card 21 shown in FIG. A communication method with the internal processor (port controller 33) will be described.
As described above, the communication between the processors in different shelves is performed by serial transmission by interrupt control.

In FIG. 8, the control highway 3 has a data highway (data input / output line), a frame cycle signal transmission line and a data highway clock transmission line,
M highway 4 is a PCM highway clock transmission line and PCM
It has a transmission line of a highway frame period signal. The clock generator 47 in the local CPU card 13 sends the data highway clock to the control highway 3. On the other hand, the line corresponding part 36 in the line / trunk card 21 is CODE
Including C and SLIC.

In this embodiment, as an interface LSI, there are two modes by mode setting input, that is, a master mode having a function of transmitting data in a time slot assigned to itself in synchronization with a change point of a time slot, and a time from an external source. A slave mode having a function of transmitting data only at the time slot address obtained by the slot designation address is used.

The interface LSI 41 in the local CPU card 13 operates in the master mode and is inserted between the local CPU and the control highway 3. This interface LSI4
Sending data from 1 to control highway 3
It is performed in synchronization with the changing point of the time slot. Also,
Interface LSI 34 in line / trunk card 21
When the header is detected, the data is received, and an interrupt request as a reception request is made to the local CPU 43.

Interface LSI3 in line / trunk card 21
4 operates in the slave mode and connects the control highway 3 and the PCM highway 4 to the port controller 33 that controls the input / output of each port in the card 21. Data can be sent from the interface LSI 34 to the control highway 3 only in a time slot designated by a time slot designation address from the outside. Further, upon reception of the interface LSI 34, the data is received via the control highway 3 after detecting the header, and the received data is validated only when the address of the received data matches the time slot designated address from the outside. It makes a determination and issues an interrupt request as a reception request to the port controller 33.

When the port controller 33 receives the interrupt request, it reads the reception data from the reception register in the interface LSI 34, and according to the data, the line / trunk card 21
Is controlled. When sending data to the line interface 36, the port controller 33
After writing the control data in the line corresponding control unit, the interface LSI 34 sends the control data to the line corresponding unit 36.

The status of the line interface 36 or data from a subscriber terminal such as the digital telephone 31 is determined by the interface LSI 34.
It is periodically taken into the I / O register of the line interface control unit. Then, the port controller 33 periodically reads the data in this I / O register to
Detects 36 state changes and detects this state change or local CP
The control data for U43 is written to the transmission register in the interface LSI34. After this, the interface LSI3
Reference numeral 4 outputs the contents of the transmission register to the data highway (data output line) of the control highway 3 in the time slot given by the time slot designation address from the outside.

Next, a communication system between the processors in the common control shelf 1, which is a feature of the present invention, that is, between the processors provided in each common control card will be described. For communication between processors in the common control shelf 1, each local CPU 43
Data transmission for transmitting to the main CPU52 or the application CPU the data related to the status of the subscriber terminal collected from the line / trunk card 21 under its control and the data processed from the subscriber terminal to a predetermined level, and the main CPU52 and the application. There is a data transmission for transmitting the terminal control data obtained by each CPU through the exchange processing to the local CPU 43 side.

As described above, the communication between the processors in the same shelf is performed by connecting the common bus 16 to the common memory 16 that can be commonly accessed by each processor, writing the data to be transmitted to the common memory 16, and This is performed by reading the data to be received from this common memory 16.

A method itself in which a common memory is connected to a common bus and data is transmitted between arbitrary processors via the common memory is known as seen in control by IEEE796, for example. According to this method, data is transmitted by a processor requiring access to the common memory issuing a control signal on the common bus and occupying the common bus during the access period. In that case, if access by a plurality of processors collides, processing is performed based on a predetermined priority.

In this embodiment, each local CPU 43 writes the state or dial information data to the common memory 16 each time a state change occurs on the subscriber terminal side and whenever dial information is sent from the subscriber terminal. By periodically polling the contents of the common memory 16 in the main CPU 52, the state change of each subscriber terminal is known and the corresponding process is performed. For example, if there is a call from the subscriber terminal, it is detected and the call processing is performed. In the series of routines of this call processing, when the data originally stored in the common memory 16 or the data written in the common memory 16 from the subscriber terminal via the local CPU 43 is required, the common memory 16 Is accessed to read the data and perform processing. If the control data for controlling the subscriber terminal side changes as a result of this processing, the control data is changed to a common memory.
Write to 16.

On the other hand, also in the local CPU 43, the contents of the common memory 16 are determined in order to determine whether or not the control data of the subscriber terminal has changed, and to detect the content of the control data when the change has occurred. We regularly poll.

In this way, each processor (main CPU52, local CPU4
(3 etc.) writes data to be transmitted to the common memory 16, polls the contents of the common memory 16 periodically or as needed, and reads the data to be received, thereby communicating between these processors. Is performed. By doing this, there is a difference in function level between the local CPU 43, the main CPU 52, and the application CPU, and the main CPU
Despite the fact that data is collected from the local CPU 43 side to the 52 or application CPU, the main CPU 52, the application CPU, etc. can execute their own processing programs (for example, exchange processing programs) without interruption, thus improving processing efficiency. improves.

In addition, the local CPU (Lcpu) 43, the main CPU (Mcpu), and the application CPU (Acpu) are connected via the common memory 16 on the common bus 15.
Since the communication between -Lcpu, Lcpu-Acpu, and Mcpu-Acpu can be performed flexibly, it is possible to perform higher-level services while maintaining real time.

Further, as shown in FIG. 9, the local CPU 43 located between the serial transmission area and the parallel transmission area changes from the physical level which is the processing level of the line / trunk card 21 to the logical level which is the processing level of the local CPU 43. If the conversion is performed, the main CPU 52 can handle the input / output at the maximum abstraction level. Figure 9 shows the line / trunk card 21, local CPU 43 and main CP.
Each function of U52 and the specific example of the communication data between these processors are shown. In this way, the local CPU 43 can control command data transmission between the subscriber terminal and the trunk, and the main CPU 5
Since the 2 does not need to manage the command data, the load on the main CPU 52 is reduced, and there are advantages that the change and addition are easy, the expandability is improved, and the productivity is increased.

Next, the internal configuration of the interface LSI (34, 41, etc.) will be described with reference to FIG. As described above, the interface LSI has a master mode having a function of transmitting data to the data highway in the control highway 3 in synchronization with the changing point of the time slot, and transmitting data to the data highway from the external time. It is arranged to be able to switch to a slave mode which is only possible in the time slot of the address matching the address given by the slot designation address. The control unit for switching the master / slave mode by the mode setting input is in the data highway transmitting / receiving unit 101.

In FIG. 10, the data highway transmitter / receiver 101 uses a frame synchronization signal DHFS and a data highway clock DH.
It operates by CLK and transmits / receives data to / from the data input line DHIN and the data output line DHOUT via the data highway transmission register 102 and the data highway reception register 103. In this case, the transmission / reception timing differs depending on the mode, as described above. That is,
In the master mode, the data in the transmission register 102 is transmitted in synchronization with the change point of the time slot, and in the case of reception, the data after the header detection is received and stored in the reception register 103. In slave mode, the data in the transmission register 102 is sent only in the time slot of the address that matches the external time slot designation address, and when receiving, the data is received after header detection and the external time slot designation is performed. Data is stored in the reception register 103 only when the address and the address in the received data match.

The CPU interface control unit 104 decodes the address data from the data bus and sends the data to each block in the interface LSI.

The line correspondence control unit 105 includes an input register 106 and an output register 1
07 and I / O specification register 10 that specifies the I / O mode
8 and is connected to the line interface 36 (FIG. 8).

The PCM time slot control unit 109 is a PCM frame synchronous PCMFS
And the PCM clock PCMCLK to count the number of time slots, compare with the PCM time slot address set in the PCM time slot specification register 110 by the port controller 33, and when these match, give frame synchronization to the CODEC. Take control.

In the electronic exchange of this embodiment, when the same data is transmitted from the local CPU 43 to a plurality of port controllers 33, a common group address is given to the slave mode interface LSIs 34 to which the port controllers 33 are connected. Data is transmitted using this group address. This group address has a meaning as a set of addresses of a plurality of interface LSIs 34, and is registered in advance in each interface LSI 34.

As a method of transmitting the same data from the local CPU 43 to the plurality of port controllers 33, the normal transmission is sequentially performed to each port controller and the same data is transmitted.
A method of adding transmission data to a group address representing a plurality of interface LSIs 34 connected to each other and transmitting the data can be considered. Although the method is simple, it is necessary to sequentially transmit the address and the transmission data individually to each port controller. On the other hand, in the method (1), since the transmission can be performed at once between the local CPU 43 and the plurality of port controllers 33, the time required for the transmission is shortened and the load on the local CPU 43 is also reduced.

Next, the transmission signal format in this embodiment is set to the 11th
It will be described with reference to the drawings. As shown in the figure, one frame is formed by the header, address, control data, and information data. The address is an individual address for individually transmitting data to a single port controller 33, a broadcast address for transmitting the same data to a plurality of port controllers 33, and the same data for all port controllers 33. It is divided into a broadcast address to be transmitted.
As the information (identifier) indicating the distinction between the individual address, the broadcast address and the broadcast address, the upper 2 bits (MSB side) in the address format shown in the lower part of FIG. 11 are used. In the case of an individual address, a single interface LSI address (ILSI address) follows the identifier of the upper 2 bits indicating the distinction of this address, and in the case of broadcast, a group address indicating an arbitrarily designated group. Each is added.

Now, as shown in FIG. 12, a single group address (#
If A) represents the address information of a plurality of interface LSIs, the interface LSI 3 connected from the local CPU 43 to the plurality of port controllers 33 will be described.
When transmitting the same data to 4, the identifier “10” is set in the upper 2 bits in the address format as shown in FIG. 11, and then #A is set as the representative address of # 1 to #n. Just add it. This allows local CPU4
The data from 3 is sent to the interface LSI 34 connected to the plurality of port controllers 33 by one transmission operation.

In the interface LSI 34 to which the data from the local CPU 43 is sent in this way, the group address is extracted from the data received via the data highway and compared with the group address registered in advance. As a result of this comparison, when both addresses match, the information data in the transmission data is received. In FIG. 12, the group addresses #A and #B are assigned to the standard telephone (ST) which is the line / trunk card 21 provided with the interface LSI 34.
The card is connected to T). This line / trunk card can receive transmission data from the local CPU 43, but other line / trunk cards cannot receive the same data.

FIG. 13 shows the configuration of the address processing circuit provided in the line / trunk 21 for performing the above-mentioned processing. The upper 2 bits (identifier) of the received address are shown.
Is supplied to the E and S terminals (control input terminal) of the selector 131. A group address stored in the memory 132 in the line / trunk 21 and an LSI address assigned to each interface LSI 34 are supplied to the A and B terminals (data input terminals) of the selector 131, respectively. From the selector 131, when (E, S) = (0,0), the LSI address is
When S) = (1,0), the group address is output and supplied to the first input terminal of the comparator 133.
The address information following the upper 2 bits of the received address is supplied to the second input terminal of the comparator 133, and when the values of the first and second input terminals match, the output of the comparator 133 becomes "1". On the other hand, the information of the upper 2 bits of the received address is further input to the 2-input AND gate 134, and it is determined whether the upper 2 bits are "11", that is, whether the received address is the broadcast address. The output of the AND gate 134 and the output of the comparator 133 are input to the 2-input OR gate 135. The “1” output of the OR gate 135 becomes a reception request to the port controller 33. That is, the interface LSI whose reception address is received
If it is an individual address (LSI address) corresponding to, a broadcast address (group address) including the received interface LSI, or a broadcast address, the information data following the address should be received. Is issued.

Such a configuration is effective for storing a program in each port, such as when starting up the system when the system goes down. That is, since the time required for loading a program or the like is determined only by the number of programs to be loaded regardless of the number of ports, the time required to start up the system is greatly shortened.

Next, the duplex system in this embodiment will be described. This duplication applies to the common control shelf 1. First
14A and 14B are views for explaining the duplicated structure in the common control shelf 1, where FIG. 14A is a front view and FIG. 14B is a rear view. The left and right are reversed in FIGS. 14 (a) and 14 (b).

As shown in FIG. 14, among various functional devices provided in the common control shelf 1, a main CPU (Mcpu), a local CPU (Lcpu), and a common memory whose failure directly affects the system down of the electronic exchange. And time switch (T
The first type board group on which SW) is mounted is duplicated as shown by 141 and 142, and is arranged on the left and right sides in the shelf 1. Further, the second type board group 143 in which the application CPU (Acpu) that is not directly involved in the system down even if a failure occurs is mounted is not duplicated and is arranged in the central portion of the shelf 1. The power supplies for supplying power to these functional devices are also duplicated as shown by 144 and 145, and are arranged at the left and right ends inside the shelf 1.

The first-type board groups 141 and 142 are the first and second common buses 1
51 and 152, respectively, and the second type substrate group 143 is the third
Connected to the common bus 153 of the. These common buses 141
˜143 and power lines 156,157 and ground line 158 are patterned on the motherboard of shelf 1.

First and second common buses 151, 152 and third common bus 1
A switch group 154, 155 for bus switching is inserted between 53 and. FIG. 15 shows the details of the switch group 154. Two directional gates G are connected in antiparallel.
1, G2 are configured as unit switches, and controlled by switch control lines S1 and S2. The gates G1 and G2 are turned on when the corresponding switch control lines S1 and S2 become "H" level. Therefore, if S1 = "H" and S2 = "L", for example, the signal is transmitted only from the common bus 153 to the common bus 151 side. The outputs of gates G1 and G2 are open when they are off. It is assumed that the switch group 155 is similarly configured.

When one of the first type substrate groups 141 and 142 is in the operating state, the switch control lines S1 and S2 connected to the switch group 154 are set to "H" or "L" level as necessary, The first common bus 151 and the third common bus 153 are connected. At that time, all the switch control lines connected to the switch group 155 are at the “L” level. On the contrary, when the other of the first type substrate groups 141 and 142 is in the operating state, the switch control lines S1 and S2 connected to the switch group 155 are R / W (read / write) signals, chip select signals, etc. Are appropriately set to "H" or "L" level, the second common bus 152 and the third common bus 153 are connected, and all the switch control lines connected to the switch group 154 at that time are "L" level. Becomes In this way, the first and second common buses 151 and 152 are selectively connected to the third common bus 1
53, so that the first substrate group 141, 142 and the second substrate group 143 are selectively connected.

Now, the first common bus 151 is connected to the third group via the switch group 54.
When a functional device on one of the first substrate groups 141 and 142 connected to the common bus 153 of the first substrate group 141, 142 is in an operating state and a failure occurs in any of the functional devices on the substrate group 141, This failure is detected as follows, and based on this, all the switch groups 154 are turned off, and the second
Common bus 152 is connected to the third common bus 153,
The board group 142 becomes the operating state in place of the board group 142, and the failure occurrence is dealt with.

As a failure detecting means of the main CPU 52, a watchdog timer 161 may be used as shown in FIG. The watchdog timer 161 includes a counter 162 and a clock generator 163 that supplies a clock to the counter 162.
The counter 162 is cleared by the program executed by the main CPU 52 at regular intervals. For example, it is assumed that the clock cycle is set to 10 msec, and when the counter 162 continuously counts 10 clocks, the Mcpu failure occurrence notification line 164 is set to the “H” level to notify the failure occurrence. 10msec × 10 = 100m when a failure such as program runaway occurs
Since the clear signal of the counter 162 cannot be generated within sec, the counter 162 detects the occurrence of a failure, and the detection result is output to the Mcpu failure notification line 164. It should be noted that the detection of the failure occurrence of the local CPU 43 can be similarly performed using the watchdog timer.

On the other hand, the failure detection of the time switch (TSW) is based on the main
By selecting a time slot that is not used by PU52, sending the test pattern to the PCM highway 4 in that time slot, and comparing the test pattern returned via the PCM highway 4 with the sent test pattern. Can be done. That is, if both test patterns match, it is determined to be normal, and if they do not match, it is determined to be abnormal. At this time, the return of the test pattern on the PCM highway 4 is performed by the time switch card 14 as shown in FIG.
A loop switch 170 may be provided in the main CPU 52, and the loop switch 170 may be closed by a command from the main CPU 52 only in the time slot when the test pattern is transmitted.

Further, the failure detection of the common memory 71 can be performed by the common memory 71 itself. For example, in the case of 1 byte / 8 bit configuration, 13 bits are used, and in the case of 16 bit configuration,
22 bits may be used for fault detection, and a known error detection LSI may be used. The failure detection of the time switch and the common memory 71 is performed by the register 165 in FIG. 16, and the detection results are output to the TSW failure notification line 166 and the memory failure detection line 167, respectively.

The various fault detection signals thus obtained are combined by the OR circuit 180 as shown in FIG.
Of the 42 boards that were used until the failure occurred (eg 14
It is input to the interrupt line of the main CPU 52 on the other board group 142 which is not 1) to start the program of the CPU 52. In this case, by turning off all the switch groups 154 and turning on the switch groups 155 at the same time, the first common bus 151 and the third common bus 153 are separated and the second common bus 153 is separated.
The common bus 152 and the third common bus 153 are connected as described above.

According to the duplication method as described above, the switch groups 154, 15
With 5, the failure occurrence can be dealt with by simply switching the connection between the first and second common buses 151, 152 and the third common bus 153 all together, and the hardware for switching control becomes very simple. .

On the other hand, the redundant power sources 144 and 145 are connected to the first type substrate groups 141 and 142 via the power lines 156 and 157, respectively, and are connected to the non-redundant second type substrate group 143 via the diodes 159 and 160, respectively. And supplies electric power to the functional devices in either one of the duplicated first substrate groups 141 and 142,
The functional devices in the second substrate group 143 that are not duplicated are shared in the form of load share to supply electric power. Therefore, a smaller power capacity is required as compared with the conventional technology in which each of the redundant power supplies supplies power to all of the functional devices that are duplicated and the functional devices that are not duplicated. If the power supply lines 156 and 157 are directly connected to the second board group 143,
Between 151 and 152, current flows from the higher potential side to the lower potential side. The diodes 159 and 160 are for preventing such a backflow phenomenon.

[Effects of the Invention] The duplexing method of the electronic exchange according to the present invention has an advantage that it is possible to deal with the occurrence of a failure by simple hardware, and at the same time, the capacity of each redundant power supply can be minimized. This can contribute to downsizing and cost reduction of the exchange.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic structure of an electronic exchange according to an embodiment of the present invention, FIG. 2 is a diagram showing a shelf stacking structure of the electronic exchange, and FIG. 3 is an inside of a line / trunk card in the same embodiment. FIG. 4 is a diagram showing a configuration, FIG. 4 is a diagram showing an internal configuration of a local CPU card in the same embodiment, FIG. 5 is a diagram showing an internal configuration of a main CPU card in the same embodiment, and FIG.
FIG. 7 is a diagram showing the internal structure of the time switch card in the same embodiment, FIG. 7 is a diagram showing the internal structure of the common memory card in the same embodiment, and FIG. 8 is a local CPU card in the common control shelf in the same embodiment. And FIG. 9 is a diagram for explaining the communication system in the line / trunk card, FIG. 9 is a diagram showing a specific example of communication data between the line / trunk card, the local CPU and the main CPU, and FIG. FIG. 11 is a diagram showing an internal configuration of an interface LSI in the embodiment, FIG. 11 is a diagram showing a transmission signal format for explaining a data transmission method from the local CPU to the port controller in the line / trunk card in the embodiment, FIG. FIG. 12 is a conceptual diagram for explaining the data transmission method, and FIG. 13 is an address in the line / trunk card used for implementing the data transmission method. FIGS. 14 (a) and 14 (b) are a front view and a rear view showing the arrangement of functional devices and power supplies in a common control shelf for explaining the duplex system in the same embodiment, and FIG. Fig. 16 is a diagram showing in detail the bus switching switch group in Fig. 14, Fig. 16
FIG. 18 to FIG. 18 are diagrams for explaining the failure detecting means associated with the duplex system, and FIGS. 19 and 20 are diagrams for explaining the conventional duplex system. 1 ... Common control shelf, 2a to 2n ... Line / trunk shelf, 3 ... Control highway, 4 ... PCM highway, 11 ... Main CPU card, 12 ... Application CPU card, 13 ... Local CPU card, 14 ... Time switch card, 15 ... common bus, 16 ... common memory, 21 ... line / trunk card, 33 ... port controller, 34,41 ... interface LSI, 43 ... local CPU, 52 ... main CPU, 7
1 ... Common memory, 141, 142 ... First board group, 143 ... Second board group, 144, 145 ... Power supply, 151-153 ... First to third common bus, 154, 155 ... Bus switching switch group, 159, 160 ... Backflow prevention Diode, 161: Watchdog timer.

Claims (3)

[Claims] 1. An electronic exchange having a plurality of boards provided with functional devices and a shelf having a power supply for supplying electric power to the boards mounted thereon, the electronic exchange being directly involved in system down of the electronic exchange when a failure occurs. The first-type board group provided with the functional devices is duplicated, and the duplicated groups are connected to the first and second common buses, respectively, so that even if a failure occurs, the system of the electronic exchange can be down. The second type substrate group provided with the functional devices not directly involved is not duplicated, and either the first or second common bus is connected to the third common bus selectively connected by the bus switch group. , The power supplies are duplicated, and each of the power supplies individually supplies power to the duplicated first type substrate group and shares power to the second type substrate group. The first-type board group, which is connected in such a manner as to be duplicated, is provided with a failure detection unit for each board, and is connected to the third common bus via one of the first and second common buses. When it is detected by the failure detection means that a failure has occurred in at least one of the one of the first substrate groups,
By notifying the occurrence of the failure to the other board group of the first type board group by interruption, and the other group receiving the failure occurrence notification controls the switching of the bus switch group,
The duplex system of the electronic exchange, wherein the other group is connected to the third common bus in place of the one group. 2. A first board group is provided with a processor for controlling a switching process, a memory and a time-division time slot as functional devices directly involved in a system down of an electronic exchange when a failure occurs. Claim 1 is characterized in that the circuit board group is provided with a processor for controlling application services such as call management as a functional device that is not directly involved in system down of the electronic exchange even if a failure occurs. Duplex method of electronic exchange described in paragraph. 3. A power supply having a capacity capable of simultaneously supplying electric power to any one of the duplicated type 1 substrate group and the type 2 substrate group. The duplex system for an electronic exchange according to claim 1.