JPH0834312B2 - Vertical field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is suitable for being incorporated into an individual element or an integrated circuit device.
The present invention relates to a vertical field effect transistor commonly known as DMOS (double diffused MOS).

[Conventional technology]

Vertical field-effect transistors are suitable for high withstand voltage and large current compared to those with horizontal structure such as ordinary MOS transistors, and have been practically used as power transistors for high frequencies and have been used in a wide range of applications. . This vertical field-effect transistor has a structure in which a large number of microtransistors made by using integrated circuit technology are connected in parallel, so that the vertical field-effect transistor is not limited to the above-mentioned individual elements such as power transistors,
It is also suitable for incorporation into integrated circuit devices that drive loads directly. FIG. 3 shows this typical conventional example. FIG. 3 (a) is a partially enlarged plan view thereof, and FIG.
It is X sectional view taken on the arrow.

The vertical field effect transistor in this example is an n-channel type for an individual device, and the drain layer 2 in FIG. 3 (b) is an n-type having a high impurity concentration and a low resistance, and is formed thereon. The semiconductor region 3 such as an epitaxial layer is also n-type and, in operation, this serves as a drain region. A gate 5 of polycrystalline silicon or the like is provided so as to cover the surface of the semiconductor region 3 with a very thin gate oxide film 4 interposed therebetween. Further, as shown in FIG.
In this example, a large number of square windows 5b of about m square are cut out in a square array. The window 5b may be formed in a hexagonal shape, and in this case, the windows 5b are hexagonally arranged according to the shape.

The channel formation layer 6 has its window with the gate 5 as a mask.
P-type diffusion is carried out from 5b using the ion implantation method, and the peripheral portion thereof is formed so as to dig under the gate 5.
Then, the strong n-type source layer 7 is diffused so that it is shallower than the channel forming layer 6 and its peripheral edge slightly goes under the gate 5 by the ion implantation method which also masks the gate 5. Further, a strong p-type contact layer 8 is formed at the center of the window 5b, as shown in FIG.
Is diffused to reach the channel formation layer 6 through the. After that, as shown in FIG. 3B, an insulating film 9 such as an oxide film is provided so as to cover the gate 5, and a source electrode 10 is further provided thereon to form a source layer 7 and a contact layer 8 in the window 5b.
To be in conductive contact with the surface of the. A drain electrode 11 is connected to the drain layer 2 on the lower side of the figure. It should be noted that FIG. 1A is shown without the source electrode 10 for convenience of illustration.

In the vertical field effect transistor having the above structure, as shown in FIG. 3 (b), the gate 5 to the gate terminal G are
A source terminal S is led out from the source electrode 10 and a drain terminal D is led out from the drain electrode 11, respectively. For example, the drain terminal D is used at a positive potential and the source terminal S is placed at a ground potential. When a positive voltage is applied to the gate terminal G, an n-type channel is formed on the surface of the p-type channel forming layer 6 below the gate 5, and as shown in the figure, electrons e as majority carriers are n-type. The source layer 7 enters the n-type semiconductor region 4 through the n-channel, flows vertically in the semiconductor region 4, and reaches the n-type drain layer 2.

The source layer 7 and the contact layer 8 are short-circuited by the source electrode 10, which keeps the channel forming layer 6 at substantially the same potential as the source layer 7 and stabilizes the gate threshold value of this field effect transistor. It Since the power supply voltage applied during the off operation is mainly borne by the depletion layer extending from the pn junction between the semiconductor region 4 and the channel forming layer 6 into the semiconductor region 4, the vertical field effect transistor has a high withstand voltage value. Can be made. Since the current capacity is naturally determined by the channel width, that is, the peripheral flow of the source layer 7, the pattern of the minute transistors connected in parallel is miniaturized to allow the peripheral length of the source layer 7 per unit chip area as long as the photoprocess accuracy allows. By increasing the total, the current capacity is improved or the on-resistance is reduced.

[Problems to be Solved by the Invention]

As described above, in the vertical field effect transistor, although the voltage applied to it is mainly borne in the semiconductor region 4,
If the overlength is applied to the channel length of about 1 to 2 μm, the so-called punch-through of the channel occurs and the control becomes uncontrollable, and if the punch-through voltage is improved, the current capacity tends to decrease. There's a problem.

As can be seen from FIG. 3A, the punch-through described above is likely to occur because the electric field is concentrated at the corners of the rectangular diffusion pattern of the channel forming layer 6 and the source layer 7, and this electric field concentration is relaxed as much as possible. Therefore, for example, the connecting layer 6a, which is shown only at one position in the figure, is provided with four adjacent channel forming layers 6.
Conventionally, a device such as an X-shape is provided so that the corners of the are connected to each other. However, since a large amount of channel current originally tends to flow in this corner portion, this means that the current flowing in the corner portion is eliminated, so that the effective peripheral length of the source layer 7 is reduced and the current capacity is considerably reduced. . In addition, the contact layer 6a must be diffused before the gate 5 is provided, and the so-called self-aligned diffusion using the gate as a mask like the channel forming layer 6 and the source layer 7 cannot be performed, which is very important for a photo process. In addition to requiring high precision,
This introduces the problem of increasing the number of processes.

In the case where the channel forming layer 6 and the source layer 7 are formed in a hexagonal shape as described above, since the angle of the corner is 120 degrees, the electric field concentration is considerably relaxed as compared with the case of a square shape of 90 degrees. It is not possible to obtain the effect of providing the above-mentioned connecting layer 6a. Further, when the vertical field effect transistor is built in an integrated circuit device, it is quite difficult to reasonably arrange them in a hexagonal array because the number of parallel connections of the small transistors is usually about several tens. In other words, the size of each small transistor has a lower limit depending on the accuracy of the photo process that can be used, so if you try to fit the required number in the planned area, the size will be cut off and the utilization efficiency of the area will decrease, or the plan will be forced. You have to expand the area.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems of the prior art and to obtain a vertical field effect transistor which has almost no electric field concentration in the channel portion and can have a large current capacity.

[Means for Solving the Problems] A long and narrow strip which is provided so as to cover one surface of a semiconductor region having one conductivity type in which a field effect transistor is to be formed through a gate oxide film and communicates with one surface of the semiconductor region. The gate is provided with a plurality of windows having rounded ends, and a channel forming layer diffused in the other conductivity type is formed in each of the windows of the plurality of gates by allowing the peripheral portion of the windows to enter under the gate, A source layer diffused in one conductivity type from the window of the gate to reach the channel forming layer, and a plurality of elongated windows of the gate are arranged in the source layer in a direction in which the elongated window extends, and the source layer extends in the direction in which the elongated window extends. A contact layer diffused in the other conductivity type so as to reach the channel forming layer from the surface of the source layer without dividing the contact layer in the window of the gate and the source layer. At least, it is provided with a source electrode that electrically contacts between the contact layers and between the windows to short-circuit the surfaces of both layers, and a drain electrode derived from the other surface side of the semiconductor region. Achieved by

In the above structure, since the channel forming layer and the source layer are diffused in a self-aligned manner from the window using the gate as a mask as in the conventional case, both are formed in an elongated pattern according to the shape of the window. The current capacity to be given to the vertical field effect transistor varies depending on the length of the elongated pattern of one source layer, that is, the peripheral length thereof, but is mainly determined by the number of channel forming layers as in the conventional case, and therefore the present invention. Also in this case, a plurality of source layers or a plurality of source layers are usually arranged side by side on the side of the elongated pattern.

By the way, in order to obtain the maximum current capacity from a certain area allocated for the vertical field effect transistor, the width of the elongated pattern of each source layer or the width of the window pattern opened in the gate is allowed for the accuracy of the photo process. It is necessary to make it as small as possible and make as many source layers as possible within this area. However, as mentioned in the above configuration,
The source electrode is conductively contacted with the source layer and the contact layer in the window of the gate, and the width of the source electrode or the contact layer is a minimum dimension in photoprocessing. For this reason,
In the present invention, it is most desirable to select the width of the source electrode or the contact layer to the minimum dimension allowed from the photo process accuracy in order to obtain the maximum current capacity.

[Action]

In the present invention, as described above, a narrow window is opened in the gate, and the source layer and the channel formation layer are also formed in a long stripe pattern by diffusion that masks the gate. Since a plurality of contact layers are distributed and arranged along the elongated pattern, it becomes a structure in which a plurality of conventional small transistors arranged in a predetermined direction are connected to each other in a stripe shape. Therefore, the corners of the source layer and the like that exist in each of the conventional microtransistors disappear, the concentration of the electric field in the channel is almost eliminated, and the punchthrough voltage is significantly improved. Of course, by appropriately rounding the edges of the stripes, for example, in the shape of a semi-circle, the electric field concentration at the edges of the stripe pattern can be relaxed to the extent that there is no practical problem. Can also be connected to form a single loop with no ends.

On the other hand, since the minute transistors are interconnected as described above, the peripheral length of the connected source layer portion cannot be used. However, as described in the embodiment, the width of each stripe is narrowed to reduce this per unit area. By arranging a large number of them, it is possible to increase the peripheral length of the source layer as a whole and to increase the current capacity rather than the conventional one. Also,
In a vertical field effect transistor built into an integrated circuit device, the length of a stripe or loop can be taken to fill a given area without being restricted by photo process accuracy, so that the utilization efficiency of the area is improved and the current capacity is consequently increased. To increase.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example in which an n-channel vertical field effect transistor according to the present invention is built in an integrated circuit device. FIG. 1 (a) is an enlarged plan view of the main part thereof, and FIG.
The sectional view taken along the line XX is shown in FIG.
A cross-sectional view taken along the arrow Y is shown. In the figure, the same reference numerals are given to the parts corresponding to FIG.

As shown in FIGS. 1 (b) and 1 (c), a semiconductor substrate 1 for an integrated circuit device is, for example, p-type as usual, and an n-type drain layer 2 strong as a so-called buried layer on the surface thereof. Is first diffused, and an epitaxial layer is conventionally grown as the semiconductor region 3 to have a thickness of, for example, 10 to 20 .mu.m in the n-type. The epitaxial layer is junction-separated into the semiconductor region 3 in the figure by deeply diffusing a strong p-type junction isolation layer from the surface thereof until reaching the substrate 1 in a pattern surrounding the illustrated range. In order to derive the drain terminal from the drain layer 2 to the outside, as usual, a strong n
A junction layer having a shape is diffused so as to reach the drain layer 2 as a buried layer from the surface of a portion (not shown) of the semiconductor region 3, and then an electrode film which is in conductive contact is provided on the surface.

When fabricating a vertical field effect transistor in the semiconductor region 3, first, the surface is covered with a thin gate oxide film 4 of about 0.1 μm, and then, for example, a polycrystalline silicon layer for the gate 5 is entirely formed with a thickness of 0.5 to 1 μm. By growing it and photoetching it, an elongated window 5a is opened as shown in FIG. 1 (a). The size of the window 5a in this embodiment is, for example, about 10 μm in the vertical width in the figure,
The length in the left-right direction is about 60 μm, and the shape of both ends thereof is semicircular as shown. For convenience of illustration, FIG. 1 (a) is shown with the source electrode 10 removed as in the case of FIG.

Then, the p-type channel forming layer 6 is diffused to a depth of, for example, about 3 μm at a predetermined impurity concentration by a conventional self-aligned ion implantation using the gate 5 as a mask and subsequent thermal diffusion. Gate 5 at the same time
It is made to enter under 2 to 3 μm. Next, a strong n-type source layer 7 having an impurity concentration of about 10 ²⁰ atoms / cm ³ is overlaid on the channel forming layer 6 by the ion implantation method using the gate 5 as a mask as above, but shallower than that. For example 1.5
It is diffused to a depth of .mu.m, and at this time, its peripheral edge is slightly inserted under the gate 5 so that the channel forming layer 6 under the gate 5 has a channel length of, for example, 1 to 1.5 .mu.m. As described above, the channel forming layer 6 and the source layer 7 are diffused in the elongated striped pattern having the same shape as the window 5a of the gate 5.

The p-type contact layer 8 is made to have a high impurity concentration of about 10 ¹⁹ atoms / cm ^3, and in this embodiment, each source layer is formed in a rectangular pattern having a size of about 5 μm square and the elongated pattern as described above. A plurality of them are arranged in the inside of 7 as shown in the drawing, and each is diffused to a depth to connect to the channel forming layer thereunder, and their mutual interval is, for example, about 5 μm.
In this embodiment, the contact layer 8 has the minimum dimension in the photo process.

After the diffusion of the semiconductor layer is completed, an insulating film 9 such as an oxide film is deposited on the entire surface to a thickness of 1 to 2 μm, and a window having a similar shape slightly smaller than the window 5a of the gate is formed on the window. It is removed by etching, and further covered therewith, a metal film of aluminum or the like for the source electrode 10 is vacuum-deposited or sputtered to a thickness of about 1 μm as shown in FIGS. 1B and 1C. The source electrode 10 is in conductive contact with the source layer 7 and the contact layer 8 in the above-mentioned window to short-circuit the surfaces of both layers, whereby the channel forming layer 6 connected to the contact layer 8 is connected to the source layer 7. They are placed at almost the same potential.

FIG. 2 shows a different embodiment of the present invention in a plan view corresponding to FIG. 1 (a). In this embodiment, gate 5
The window 5a which is opened is elongated as in the case of FIG. 1, but its width is narrower, for example, about 7 μm. p
The procedure for diffusing the channel-shaped channel forming layer 6 and the n-type source layer 7 in a stripe shape using the gate 5 as a mask is the same as in the case of FIG. To be done. However, in this embodiment, an insulating film 9 is provided next to the diffusion of these layers, and a window having the same shape as the window 5a of the gate but having a width of, for example, about 3 μm is removed. This is the minimum size in the photo process in this embodiment.

Then, a plurality of contact layers 8 are arranged in the source layer 7 and diffused in the same manner as in the embodiment of FIG. 1, except that the insulating film 9 is used as a part of the mask. The length of each contact layer 8 in the left-right direction in the figure is, for example, about 5 μm as before, but the width in the up-down direction in the figure is the same as the window width of the insulating film 9.
It is about 5 μm to 5 μm. Although not shown in FIG. 2, the source electrode 10 is provided in the window of the insulating film 9 so as to be in conductive contact with a portion between the contact layers of the contact layer 8 and the source layer 7.

In this embodiment, the width of the source electrode 10 in conductive contact with the semiconductor layer in the window of the insulating film 9 is set to the minimum dimension allowed in the photo process, which is 3 μm in this example, so that the width of the stripe of the source layer 7 is reduced. By narrowing the number of stripes formed per unit area, the current capacity can be further increased by about 20% compared with the case of the embodiment of FIG. Further, in this embodiment, the conductive contact area of the source electrode with the source layer 7 and the contact layer 8 is smaller than that in the previous embodiment, but both layers 7 and 8 can be maintained at substantially the same potential. .

If a photo process with higher accuracy can be used, this minimum size can be made smaller to increase the current capacity, but the radius of the end portion of the stripe of the source layer 7 becomes small, and the problem of electric field concentration appears a little. As shown by the chain line C in FIG. 2, connect the ends of the stripes to each other.
As a whole, for example, the loop shape as described above can eliminate the possibility of electric field concentration at the stripe edge.

The vertical field effect transistor according to the present invention configured as described above has a withstand voltage value which can be used at a circuit voltage of 150 to 200 V and a current capacity of 50 mA or more per 100 square μm of the chip area, and a high frequency of 1 to 4 MHz. It can be used for various purposes. Further, as for the gate threshold value, a low value of about 2 V can be stably guaranteed.

The embodiments described above are merely examples, and the present invention can be carried out in various modes within the scope thereof.

〔The invention's effect〕

As described above, in the present invention, the window opened in the gate of the vertical field effect transistor has an elongated shape, and the channel forming layer and the source layer inside the channel forming layer are sequentially formed from the window of the gate in the peripheral portion thereof. Under the gate, diffuse to form both layers in a stripe-shaped pattern with a double structure.Distribute and distribute a plurality of contact layers in the stripe-shaped source layer, and then set the source electrode to the gate. Since it is provided so as to make conductive contact with the source layer and contact layer in the window, the channel has a shape with no corners where electric field concentration is likely to occur, as in the structure in which conventional rectangular or hexagonal microtransistors are integrated. It can be formed, the punch-through voltage is significantly improved, and the operating voltage of the vertical field effect transistor is increased from the conventional 100V class to 200V class, and the stripe-shaped To increase the peripheral length of the source layer by narrowing the turn width and increasing the number of stripes per unit area, and improving the current capacity of the transistor by about 20 to 30% compared to the past, although it may vary slightly depending on the accuracy of the photo process. You can

Further, according to the aspect described in the embodiment of FIG. 2 in which the minimum dimension on the photo process is used for opening the window of the insulating film, the photo process for diffusion of each semiconductor layer including the contact layer requires high accuracy. The vertical field-effect transistor can have a large current capacity without making use of the minimum dimension allowed in the photo process.

The present invention having the above characteristics is most suitable for incorporating a plurality of relatively small vertical field effect transistors in an integrated circuit device. That is, in such a case, there is always a restriction on the area that can be allocated to each transistor, but since the vertical field effect transistor according to the present invention can arbitrarily set its stripe length, the allocated area is used most effectively to A large current capacity can be taken.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIG. 2 relate to the present invention. FIG. 1 is an enlarged plan view and a sectional view of an essential part of an embodiment of a vertical field effect transistor according to the present invention, and FIG. It is a principal part enlarged plan view of a different Example. FIG. 3 is an enlarged plan view of a main part of a vertical field effect transistor according to the prior art. In the figure, 1: semiconductor substrate for integrated circuit device, 2: drain layer, 3: semiconductor region or epitaxial layer, 4: gate oxide film, 5: gate, 5a, 5b: window of gate, 6: channel formation layer, 6a : Connecting layer, 7: source layer, 8: contact layer, 9: insulating film, 10: source electrode, 11: drain electrode, C: stripe connecting path, D:
Drain terminal, e: electron, G: gate terminal, S: source terminal,
Is.

Claims (1)

[Claims] 1. An elongated semiconductor device which is provided so as to cover one surface of a semiconductor region having one conductivity type in which a field effect transistor is to be formed, with a gate oxide film interposed therebetween, and has a rounded end. Is provided with a gate having a plurality of windows opened, and the windows of the plurality of gates are respectively
In the source layer, a channel forming layer diffused by the other conductivity type by allowing the peripheral portion to enter under the gate from the window, and a source layer diffused by one conductivity type so as to reach the channel forming layer from the window of the gate. A plurality of contacts are arranged in the direction in which the elongated window of the gate extends, and the contacts are diffused by the other conductivity type so as to reach the channel formation layer from the surface of the source layer without dividing the source layer in the direction in which the elongated window extends. A contact layer in the window of the gate and at least a portion between the contact layers of the source layer and a plurality of windows to make a conductive contact to short-circuit the surfaces of both layers. A vertical field-effect transistor comprising a drain electrode led out from the other surface side.