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JPH08340019A - Board, manufacture of board, and wire bonding method - Google Patents

Board, manufacture of board, and wire bonding method

Info

Publication number
JPH08340019A
JPH08340019A JP7146015A JP14601595A JPH08340019A JP H08340019 A JPH08340019 A JP H08340019A JP 7146015 A JP7146015 A JP 7146015A JP 14601595 A JP14601595 A JP 14601595A JP H08340019 A JPH08340019 A JP H08340019A
Authority
JP
Japan
Prior art keywords
bonding
electrode
gold
layer
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7146015A
Other languages
Japanese (ja)
Other versions
JP3232959B2 (en
Inventor
Hiroshi Haji
宏 土師
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14601595A priority Critical patent/JP3232959B2/en
Publication of JPH08340019A publication Critical patent/JPH08340019A/en
Application granted granted Critical
Publication of JP3232959B2 publication Critical patent/JP3232959B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/191—Disposition
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    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Drying Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To form an electrode having sufficient bondability at a low cost, by a method wherein, after bonding inhibition material deposited on the surface layer part of an electrode which is formed on a board main body and composed of three layers of a copper foil, a barrier metal layer and a gold layer is eliminated, a protruding part for bonding which is composed of gold is formed on the electrode. CONSTITUTION: An electrode 2 which is composed, from below, of a copper foil, a barrier metal layer and a gold layer is formed on the surface of a board main body 1. The gold layer is formed by electroless plating which can reduce the cost and the processing time. In this case, however, bonding inhibition material 3 composed of nickel compounds or the like is deposited on the surface layer part of the electrode 2. The board main body 1 is put in a vacuum chamber 4, and the bonding inhibition material 3 is eliminated by etching. The board main body 1 is taken out from the vacuum chamber 4, and set on a wire bonding equipment or the like. A protruding part 8 for bonding is formed on the electrode 2 wherein the bonding inhibition material 3 is eliminated and metal is exposed, by using a high purity gold wire or the like.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ワイヤの接合性を高め
た基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate having improved wire bondability.

【０００２】[0002]

【従来の技術】従来、基板本体に、銅箔、バリアメタル
層及び金層の三層からからなる電極を形成し、この電極
とチップの電極とを、ワイヤで接続することが広く行わ
れている。ところで、この金層は、ワイヤとの十分な接
合性を有するものでなければならない。2. Description of the Related Art Conventionally, it has been widely practiced to form an electrode composed of three layers of a copper foil, a barrier metal layer and a gold layer on a substrate body and to connect the electrode and the electrode of a chip with a wire. There is. By the way, this gold layer must have sufficient bondability with the wire.

【０００３】このため従来、この金層は、経験的に３０
０ナノメートル以上比較的厚く形成しなければならない
ものと信じられている。そして、この金層は、電解メッ
キ法、あるいは無電解還元型メッキ法により形成するこ
とが常識となっていた。Therefore, conventionally, this gold layer has been empirically
It is believed that it must be formed relatively thicker than 0 nanometers. It has been common knowledge that this gold layer is formed by an electrolytic plating method or an electroless reduction type plating method.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、電解メ
ッキ法あるいは無電解置換型メッキ法のいずれであって
も、厚めの金層を形成するには、長大な処理時間と高い
製造コストがかかっていた。However, regardless of the electrolytic plating method or the electroless displacement type plating method, it takes a long processing time and high manufacturing cost to form a thick gold layer. .

【０００５】そこで本発明は、安価でしかも十分な接合
性を有する電極を備えた基板を提供することを目的とす
る。Therefore, an object of the present invention is to provide a substrate provided with an electrode which is inexpensive and has sufficient bonding properties.

【０００６】[0006]

【課題を解決するための手段】本発明の基板は、基板本
体に、銅箔、バリアメタル層及び金層の三層からからな
る電極を形成し、電極の表層部に析出した接合阻害物を
除去し、接合阻害物が除去された電極に金からなる接合
用突部を形成してなる。The substrate of the present invention has an electrode comprising three layers of a copper foil, a barrier metal layer and a gold layer formed on the substrate body, and a bonding inhibitor deposited on the surface layer of the electrode. Then, a joining projection made of gold is formed on the electrode from which the joining inhibitor has been removed.

【０００７】[0007]

【作用】上記構成において、例えばキュア工程などのよ
うに、ワイヤボンディングを完了するまでの間に、基板
本体は加熱される運命にあるが、このような加熱の際
に、金層の表層部に再度接合阻害物が析出しても、接合
用突部の表層部まで接合阻害物が及ぶことはなく、接合
用突部と半導体チップの電極とを良好な接合性をもって
ワイヤがけすることができる。In the above structure, the substrate body is destined to be heated until the wire bonding is completed, for example, in the curing step, but at the time of such heating, the surface layer of the gold layer is not covered. Even if the bonding inhibitor deposits again, the bonding inhibitor does not reach the surface layer of the bonding protrusion, and the bonding protrusion and the electrode of the semiconductor chip can be wire-bonded with good bonding property.

【０００８】[0008]

【実施例】次に、図面を参照しながら本発明の実施例を
説明する。Embodiments of the present invention will now be described with reference to the drawings.

【０００９】図１（ａ）から（ｆ）は、本発明の一実施
例におけるワイヤボンディング方法の工程説明図であ
る。まず図１（ａ）に示すように、基板本体１の表面
に、下層から銅箔、バリアメタル層及び金層の三層から
からなる電極２を形成する。ここで従来の技術の項で述
べたように、従来この金層は、経験的に３００ナノメー
トル以上、電解メッキ法あるいは無電解還元型メッキ法
により形成しなければならないものと信じられていた。FIGS. 1A to 1F are process explanatory views of a wire bonding method in one embodiment of the present invention. First, as shown in FIG. 1A, an electrode 2 composed of three layers of a copper foil, a barrier metal layer and a gold layer is formed on the surface of a substrate body 1 from the lower layer. Here, as described in the section of the prior art, it was empirically believed that this gold layer must be formed by an electrolytic plating method or an electroless reduction type plating method for 300 nm or more.

【００１０】しかし、本発明者の実験によれば、無電解
置換型めっき法（通称フラッシュメッキ法）により、金
層の厚さを１０ナノメートル以上１００ナノメートル程
度というように極薄にしても十分な接合性が得られるこ
とが確認されている。もちろん、従来のように、電解メ
ッキ法や無電解還元型メッキ法により形成しても良い
が、無電解置換型メッキ法により極薄の金層を形成する
方が、コストが安くなりしかも処理時間を短縮できるの
で、一層好適である。However, according to the experiments by the present inventor, the electroless displacement plating method (commonly called flash plating method) was used to make the thickness of the gold layer extremely thin such as about 10 nanometers to 100 nanometers. It has been confirmed that sufficient bondability can be obtained. Of course, it may be formed by an electrolytic plating method or an electroless reduction type plating method as in the conventional method, but the cost is lower and the processing time can be reduced by forming an ultrathin gold layer by an electroless displacement type plating method. Is more preferable because it can be shortened.

【００１１】ここで、本実施例では、無電解置換型メッ
キ法によるものとする。すると、金層を形成した段階に
おいて、図１（ａ）に示すように、電極２の表層部（金
層の表層部でもある）に、ニッケルの化合物などからな
る接合阻害物３が析出する。本発明者の実験によれば、
図１（ａ）に示す状態では、ワイヤ（きわめて純度の高
い金線）との接合性はやや不良であった。In this embodiment, the electroless displacement plating method is used. Then, at the stage of forming the gold layer, as shown in FIG. 1A, the bonding inhibitor 3 composed of a nickel compound or the like is deposited on the surface layer portion of the electrode 2 (also the surface layer portion of the gold layer). According to the experiment of the inventor,
In the state shown in FIG. 1A, the bondability with the wire (gold wire of extremely high purity) was slightly poor.

【００１２】次に、図１（ｂ）に示すように、基板本体
１を真空チャンバー４に入れエッチングにより、接合阻
害物３を除去する。なお、５はアースされた第１電極、
６は高周波電源７に接続された第２電極である。通常こ
のエッチングによって、電極２の表層部を、５ナノメー
トル程度取り除けば、接合阻害物３はほぼ完全に除去さ
れる。Next, as shown in FIG. 1 (b), the substrate main body 1 is placed in a vacuum chamber 4 and etched to remove the bonding inhibitor 3. In addition, 5 is a grounded first electrode,
Reference numeral 6 is a second electrode connected to the high frequency power supply 7. Usually, by removing the surface layer portion of the electrode 2 by about 5 nm by this etching, the bonding inhibitor 3 is almost completely removed.

【００１３】次に基板本体１を真空チャンバー４から取
り出し、ワイヤボンディング装置などにセットする。そ
して図１（ｃ）に示すように、接合阻害物３が取り除か
れて金層が露呈している電極２に、接合用突部８を形成
する。Next, the substrate body 1 is taken out of the vacuum chamber 4 and set in a wire bonding device or the like. Then, as shown in FIG. 1C, the bonding protrusion 8 is formed on the electrode 2 from which the bonding inhibitor 3 is removed and the gold layer is exposed.

【００１４】この接合用突部８は、純度の高い金線（ワ
イヤボンディング用のワイヤでよい）などを用いて、図
２（ａ）あるいは（ｂ）に示すように、ボールボンディ
ングにより形成しても良いし、図２（ｃ）に示すよう
に、ウェッジボンディングによっても良い。なお、接合
用突部８の高さは、電極２の上面から５マイクロメート
ル以上あることが望ましい。The joining projection 8 is formed by ball bonding, as shown in FIG. 2A or 2B, using a high-purity gold wire (which may be a wire for wire bonding). Alternatively, as shown in FIG. 2C, wedge bonding may be used. The height of the bonding protrusion 8 is preferably 5 μm or more from the upper surface of the electrode 2.

【００１５】次に、図１（ｄ）に示すように、基板本体
１に接着剤９を塗布し、この接着剤９上に半導体チップ
１０を搭載する。このプロセスは通常のダイボンディン
グ工程と同じである。Next, as shown in FIG. 1D, an adhesive 9 is applied to the substrate body 1 and the semiconductor chip 10 is mounted on the adhesive 9. This process is the same as a normal die bonding process.

【００１６】次に図１（ｅ）に示すように、基板本体１
をキュア装置に入れ、例えば１５０℃で３０分間程度加
熱して、接着剤９を硬化させ、半導体チップ１０を基板
本体１に固着する。この加熱によって、電極２の表層部
に再度接合阻害物３が析出してくることがあるが、接合
用突部８よりも接合阻害物３が高くなることはなく、接
合用突部８は、外部に露呈したままの状態を保つ。Next, as shown in FIG. 1E, the substrate body 1
Is placed in a curing device and heated at, for example, 150 ° C. for about 30 minutes to cure the adhesive 9 and fix the semiconductor chip 10 to the substrate body 1. By this heating, the bonding inhibitor 3 may be deposited again on the surface layer of the electrode 2, but the bonding inhibitor 3 does not become higher than the bonding protrusion 8, and the bonding protrusion 8 is Keep exposed to the outside.

【００１７】次に図１（ｆ）に示すように、基板本体１
をキュア装置から取り出し、ワイヤボンディング装置に
セットする。そして、半導体チップ１０の電極１１と、
接合用突部８とを、高純度の金線からなるワイヤ１２で
接合する。これにより、ワイヤボンディングが完了す
る。Next, as shown in FIG. 1 (f), the substrate body 1
Is taken out from the curing device and set in the wire bonding device. Then, the electrode 11 of the semiconductor chip 10
The protrusion 8 for joining is joined with the wire 12 which consists of a high purity gold wire. This completes the wire bonding.

【００１８】なお上述したように、従来の金メッキ電極
の形成方法では、電解メッキ法により３００ないし５０
０ナノメートル程度の金層を形成していたが、これに比
べ、本実施例では極めて薄い金層を形成すれば足りる。
すなわち、本実施例では、より少ない金の使用量で十分
な接合性を提供できる。As described above, in the conventional method for forming the gold-plated electrode, 300 to 50 is formed by the electrolytic plating method.
Although a gold layer having a thickness of about 0 nanometer was formed, in this embodiment, it is sufficient to form an extremely thin gold layer.
That is, in this embodiment, sufficient bondability can be provided with a smaller amount of gold used.

【００１９】[0019]

【発明の効果】本発明の基板は、基板本体に、銅箔、バ
リアメタル層及び金層の三層からからなる電極を形成
し、電極の表層部に析出した接合阻害物を除去し、接合
阻害物が除去された電極に金からなる接合用突部を形成
してなるので、少ない量の金により安価なコストで十分
な接合性を有する電極を形成することができる。EFFECTS OF THE INVENTION The substrate of the present invention is formed by forming an electrode composed of three layers of a copper foil, a barrier metal layer and a gold layer on the substrate body and removing the bonding inhibitor deposited on the surface layer of the electrode to bond Since the joining protrusion made of gold is formed on the electrode from which the inhibitor is removed, it is possible to form the electrode having sufficient joining properties at a low cost with a small amount of gold.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）本発明の一実施例におけるワイヤボンデ
ィング方法の工程説明図 （ｂ）本発明の一実施例におけるワイヤボンディング方
法の工程説明図 （ｃ）本発明の一実施例におけるワイヤボンディング方
法の工程説明図 （ｄ）本発明の一実施例におけるワイヤボンディング方
法の工程説明図 （ｅ）本発明の一実施例におけるワイヤボンディング方
法の工程説明図 （ｆ）本発明の一実施例におけるワイヤボンディング方
法の工程説明図FIG. 1A is a process explanatory diagram of a wire bonding method according to an embodiment of the present invention. FIG. 1B is a process explanatory diagram of a wire bonding method according to an embodiment of the present invention. (D) Process explanatory drawing of wire bonding method in one embodiment of the present invention (e) Process explanatory drawing of wire bonding method in one embodiment of the present invention (f) Wire in one embodiment of the present invention Process explanatory drawing of bonding method

【図２】（ａ）本発明の一実施例における接合用突部の
例示図 （ｂ）本発明の一実施例における接合用突部の例示図 （ｃ）本発明の一実施例における接合用突部の例示図FIG. 2A is an exemplary view of a joining projection in one embodiment of the present invention. FIG. 2B is an illustration of a joining projection in one embodiment of the present invention. FIG. 2C is a joining projection in one embodiment of the present invention. Illustration of protrusion

【符号の説明】[Explanation of symbols]

１ 基板本体 ２ 電極 ３ 接合阻害物 ８ 接合用突部 １０ 半導体チップ １１ 電極 １２ ワイヤ DESCRIPTION OF SYMBOLS 1 Substrate main body 2 Electrode 3 Bonding inhibitor 8 Protrusion for bonding 10 Semiconductor chip 11 Electrode 12 Wire

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】基板本体に、銅箔、バリアメタル層及び金
層の三層からからなる電極を形成し、前記電極の表層部
に析出した接合阻害物を除去し、接合阻害物が除去され
た前記電極に金からなる接合用突部を形成したことを特
徴とする基板。1. An electrode composed of three layers of a copper foil, a barrier metal layer and a gold layer is formed on a substrate body, and a bonding inhibitor deposited on a surface layer portion of the electrode is removed to remove the bonding inhibitor. A substrate, wherein a bonding projection made of gold is formed on the electrode. 【請求項２】前記接合用突部は、ボールボンディングに
より形成されることを特徴とする請求項１記載の基板。2. The substrate according to claim 1, wherein the joining protrusion is formed by ball bonding. 【請求項３】前記接合用突部は、ウェッジボンディング
により形成されることを特徴とする請求項１記載の基
板。3. The substrate according to claim 1, wherein the joining projection is formed by wedge bonding. 【請求項４】基板本体に、銅箔、バリアメタル層及び金
層の三層からからなる電極を形成するステップと、前記
電極の表層部に析出した接合阻害物を除去するステップ
と、接合阻害物が除去された前記電極に金からなる接合
用突部を形成するステップとを含むことを特徴とする基
板の製造方法。4. A step of forming an electrode composed of three layers of a copper foil, a barrier metal layer and a gold layer on a substrate body, a step of removing a bonding inhibitor deposited on a surface layer portion of the electrode, and a bonding inhibition. And a step of forming a bonding protrusion made of gold on the electrode from which the object has been removed. 【請求項５】前記接合阻害物は、エッチングにより除去
されることを特徴とする請求項４記載の基板の製造方
法。5. The method for manufacturing a substrate according to claim 4, wherein the bonding inhibitor is removed by etching. 【請求項６】基板本体に、銅箔、バリアメタル層及び金
層の三層からからなる電極を形成するステップと、前記
電極の表層部に析出した接合阻害物を除去するステップ
と、接合阻害物が除去された前記電極に金からなる接合
用突部を形成するステップと、前記基板本体に接着剤を
塗布するステップと、前記接着剤上に半導体チップを搭
載するステップと、前記板本体を加熱して前記接着剤を
硬化させることにより前記半導体チップを前記基板本体
に固着するステップと、前記半導体チップの電極と前記
接合用突部とを導電性を有するワイヤで接続するステッ
プとを含むことを特徴とするワイヤボンディング方法。6. A step of forming an electrode comprising three layers of a copper foil, a barrier metal layer and a gold layer on a substrate body, a step of removing a bonding inhibitor deposited on a surface layer portion of the electrode, and a bonding inhibition. A step of forming a bonding projection made of gold on the electrode from which the object has been removed; a step of applying an adhesive to the substrate body; a step of mounting a semiconductor chip on the adhesive; A step of fixing the semiconductor chip to the substrate body by heating to cure the adhesive, and a step of connecting the electrode of the semiconductor chip and the bonding projection with a wire having conductivity. A wire bonding method characterized by:
JP14601595A 1995-06-13 1995-06-13 Substrate, substrate manufacturing method and wire bonding method Expired - Lifetime JP3232959B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1065712A1 (en) * 1999-06-28 2001-01-03 Sumitomo Electric Industries, Ltd. Method of wire bonding in semiconductor device
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
US6645606B2 (en) 2001-06-06 2003-11-11 Denso Corporation Electrical device having metal pad bonded with metal wiring and manufacturing method thereof
DE19744266B4 (en) * 1996-10-07 2007-04-05 Denso Corp., Kariya A wire bonding

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19744266B4 (en) * 1996-10-07 2007-04-05 Denso Corp., Kariya A wire bonding
EP1065712A1 (en) * 1999-06-28 2001-01-03 Sumitomo Electric Industries, Ltd. Method of wire bonding in semiconductor device
US6426563B1 (en) 1999-06-28 2002-07-30 Sumitomo Electric Industries Semiconductor device and method for manufacturing the same
US6784090B2 (en) 1999-06-28 2004-08-31 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing the same
US6601752B2 (en) 2000-03-13 2003-08-05 Denso Corporation Electronic part mounting method
DE10111710B4 (en) * 2000-03-13 2011-12-15 Denso Corporation Mounting method for electrical components
US6645606B2 (en) 2001-06-06 2003-11-11 Denso Corporation Electrical device having metal pad bonded with metal wiring and manufacturing method thereof

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