JPH08335627A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a semiconductor device having a field shield structure and manufacturing method thereof whereby the integration degree can be elevated more than that of the conventional device. CONSTITUTION: A semiconductor device has a field shield isolation structure 11 for electrically insulating and isolating elements formed on a semiconductor substrate 7. Grooves 12 are formed in an inert region 10, a field shield insulation film 5 and field shield electrodes 6 are buried in the grooves and the top face of the electrode 6 is made flush with the surface of the substrate 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a MOSLSI having a high degree of integration realized by a fine processing technique and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device using silicon as a semiconductor substrate, a so-called LOC has conventionally been used in which a thick thermal oxide film is selectively formed on a substrate as an element isolation method.
The OS method has often been used. However, in the LOCOS method, an oxide film region that grows laterally from the periphery of a thick thermal oxide film toward the active region, so-called Bird's Beak (Bird's
Since Beak) becomes an obstacle to miniaturization, in recent years, other technologies, especially the field shield element separation method, have been attracting attention.

The field / shield element separation method is described in, for example, Nikkei Microdevice, June 1992 issue 84-.
As shown on page 88, a MOS structure composed of a field shield insulating film and a field shield electrode (hereinafter referred to as a field shield isolation structure) is provided between active regions forming a semiconductor element, By fixing the shield electrode to a reference potential (for example, GND, 0V), formation of a parasitic channel on the surface of the substrate is prevented and insulation between the active regions is isolated.

Further, as an improved version of this field shield element separation method, in JP-A-5-109886, a field shield separation structure comprising a field shield insulating film and a field shield electrode is provided on a semiconductor substrate. A structure having a structure embedded in a trench is shown, and it is expected to realize an integrated circuit with a higher degree of integration.

[0005]

However, the conventional field / shield separation structure is still unsatisfactory in terms of the degree of integration. For example, even in the semiconductor device described in the above publication in which a field shield structure is buried inside a groove for the purpose of improving the degree of integration, the width of the upper part of the field shield electrode located on the substrate is equal to or larger than the width of the groove. Therefore, there is a problem that a large area is required for the field / shield separation structure, that is, the inactive region. Therefore, in order to realize a higher degree of integration than ever, it was necessary to further improve the conventional field shield structure.

The present invention has been made in view of the above circumstances, and easily realizes a semiconductor device having a field / shield separation structure capable of improving the degree of integration more than ever, and a semiconductor device of that kind. It is an object of the present invention to provide a possible manufacturing method.

[0007]

In order to achieve the above object, a semiconductor device of the present invention comprises a field shield insulating film for electrically insulating and separating a plurality of elements formed on a semiconductor substrate. In a semiconductor device having a field / shield separation structure having a field shield electrode and a field shield electrode, a diffusion layer forming an element on the surface side of the semiconductor substrate in an inactive region where the field / shield separation structure is formed. A groove having a depth equal to or greater than the depth is formed, the field shield insulating film is deposited on the inner wall surface of the groove, the field shield electrode is embedded in the inside, and the field shield electrode is formed. The upper surface of the same is flush with the surface of the semiconductor substrate.

In order to improve the insulation isolation performance of the field / shield isolation structure, a negative potential is applied on the N-type element isolation region side with respect to the field / shield electrode.
It is desirable that at least one of the boosted potentials of the power supply voltage is supplied to the P-type element isolation region side.

Further, the field shield insulating film has a two-layer structure of a silicon dioxide film formed on the inner wall surface side of the groove and a silicon nitride film formed on the field shield electrode side, or the field shield insulating film is formed. It has a two-layer structure of a silicon nitride film formed on the inner wall surface side and a silicon dioxide film formed on the field shield electrode side, or is formed sequentially from the inner wall surface side of the groove toward the field shield electrode side. A three-layer structure of a silicon dioxide film-a silicon nitride film-a silicon dioxide film may be used.

On the other hand, the semiconductor device manufacturing method of the present invention is
In a method of manufacturing a semiconductor device having a field shield isolation structure having a field shield insulating film and a field shield electrode for electrically insulating and isolating a plurality of elements formed on a semiconductor substrate, the field shield is provided. A first step of forming a groove having a depth equal to or greater than the depth of a diffusion layer forming the element in the inactive region where an isolation structure is formed, the opening being on the surface side of the semiconductor substrate;
A second step of forming the field shield insulating film covering the inner wall surface of the groove, and forming a field shield electrode in the groove such that its upper surface is flush with the surface of the semiconductor substrate. It is characterized by having a third step.

In the third step, a material to be the field shield electrode is formed on the field shield insulating film, the material is embedded in the groove, and then the semiconductor substrate of the semiconductor substrate is formed. By subjecting the material to planarization until the surface is exposed, the field
It is desirable that the upper surface of the shield electrode be flush with the surface of the semiconductor substrate. As specific means thereof, the film formation of the material is performed by a vapor phase growth method of silicon, and the flattening of the material is performed by a chemical mechanical polishing method, an etch back method, or a flattening corrosion method by wet etching. It can be done by

Further, in the second step, a silicon dioxide film and a silicon nitride film are sequentially laminated from the inner wall surface side of the groove, or a silicon nitride film and a silicon dioxide film are sequentially laminated from the inner wall surface side of the groove. To form a two-layer field shield insulating film or a three-layer field shield insulating film by sequentially laminating a silicon dioxide film, a silicon nitride film, and a silicon dioxide film from the inner wall surface side of the groove. You may.

[0013]

According to the semiconductor device of the present invention, since the field shield insulating film and the field shield electrode are buried inside the groove having a depth equal to or larger than the depth of the diffusion layer forming the element, they are separated. The separation between the power diffusion layers is twice the total width and depth of the groove, which is substantially increased as compared with the non-embedded field shield separation structure. In addition, in the case of the semiconductor device of the present invention, since the upper surface of the field shield electrode is flush with the surface of the semiconductor substrate, the area required for the field shield separation structure on the substrate surface is only the width of the groove. Therefore, miniaturization can be achieved as compared with the case of the conventional buried type field shield separation structure.

When a negative potential is supplied to the field shield electrode on the N-type element isolation region side or a boosted potential of the power supply voltage (Vcc) is supplied on the P-type element isolation region side, the GND potential or Vcc is applied. Since the margin of the limit value of the diffusion layer potential against overshoot and undershoot when the diffusion layer potential changes becomes larger than that in the case where
The margin of insulation separation performance increases.

Further, when the field shield insulating film has a two-layer structure or a three-layer structure composed of a silicon dioxide film and a silicon nitride film, the effective film thickness can be reduced and a film having few defects as a whole can be formed. Can be formed,
The insulation separation effect can be enhanced.

On the other hand, according to the method of manufacturing a semiconductor device of the present invention, it is possible to easily manufacture a semiconductor device which can cope with the above miniaturization. For example, in the third step, a material to be the field shield electrode is formed on the field shield insulating film by a vapor phase growth method of silicon so as to have a film thickness equal to or larger than the depth of the groove, and then chemically formed. When the material is flattened by any one of the mechanical polishing method, the etchback method, and the flattening corrosion method by wet etching,
A field shield electrode whose top surface is flush with the substrate surface can be formed without using a photolithography technique.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a view showing a field / shield separation structure in a MOSLSI (semiconductor device) of this embodiment (FIG. 1A is a cross-sectional view showing a vertical structure, and FIG. 1B is a plan view). Is an N-type MOS transistor (element to be separated), 2 is a source diffusion layer, 3 is a drain diffusion layer, 4 is a gate electrode, 5 is a field shield insulating film, and 6 is a field shield electrode.

As shown in FIG. 1A, the N-type MOS transistor 1 is formed in the active region 8 on the surface of the semiconductor substrate 7. The N-type MOS transistor 1 includes a gate electrode 4 made of polysilicon, a gate insulating film 9 made of silicon dioxide having a film thickness of 10 to 14 nm, and an LDD (Lightly Dope).
d-Drain) structure N-type source and drain diffusion layers 2, 3
It is composed of An inactive region 10 is formed between the active regions 8 and a field shield isolation structure 11 for electrically insulating and isolating the N-type MOS transistors 1 from each other is formed in the inactive region 10.

The field / shield separating structure 11
Is composed of a field shield insulating film 5 and a field shield electrode 6. In the inactive region 10,
A groove 12 having a depth equal to or larger than the depth of the source / drain diffusion layers 2 and 3 is formed on the surface side of the semiconductor substrate 7, and the field shield insulating film 5 is deposited on the inner wall surface of the groove 12. ing. Further, a field shield electrode 6 is embedded inside the groove 12 with a field shield insulating film 5 interposed therebetween. The upper surface of the field shield electrode 6 is flush with the surface of the semiconductor substrate 7. An interlayer insulating film 13 is formed above the field shield electrode 6.

As shown in FIGS. 1A and 1B, the source / drain diffusion layers 2 and 3 through the contact hole 14,
Electrode wirings 16 and 17 are respectively formed via 15. Further, as shown in FIG. 1B, an electrode wiring 19 is formed from the field shield electrode 6 through the contact hole 18, and an electrode wiring 21 is formed from the gate electrode 4 through the contact hole 20.

A method of manufacturing the MOSLSI having the above structure will be described below with reference to FIGS. First, as shown in FIG.
Grooves 12 are formed on the surface of a wafer W made of a P-type silicon single crystal substrate 7 of 4 Ω · cm by using the silicon dioxide film 22 left on the active region 8 where the N-type MOS transistor is to be formed as an etching mask. Form. In addition,
The groove 12 is processed by a dry etching method using chlorine gas, and the groove 12 has a depth of 0.5 to 1.5 μm and a width of 0.2 to 0.5 μm.

Then, as shown in FIG. 2B, a film thickness of 10 is formed on the surface of the wafer W by thermal oxidation or vapor phase epitaxy.
An insulating film 23 of silicon dioxide having a thickness of ˜80 nm is formed, and then a film thickness of 100 to 500 n is formed on the surface by vapor phase epitaxy.
Then, a polysilicon film 24 of m is formed. At this time, the polysilicon film 24 has a shape that completely fills the groove 12 and covers the entire surface of the wafer W, and contains an impurity such as phosphorus during the vapor phase growth of polysilicon, or an impurity after the vapor phase growth step. It is formed into a doped polysilicon film by any method of introduction and therefore has conductivity.

Then, as shown in FIG. 2C, chemical mechanical polishing (CMP) is performed until the surface of the substrate 7 is exposed from the front side of the wafer W.
Method) is performed to remove the polysilicon film 24 on the surface of the substrate 7 to fill the inside of the groove 12 only. The CMP method is used to chemically and mechanically polish a wafer surface using an alkaline solution, an abrasive, etc., as described in detail in the magazine "Electronic Materials" June 1993, pp. 41-62. Is a technique for flattening. Simultaneously with or after this polishing, the silicon dioxide films 22 and 23 which protect the surface of the substrate 7 in the active region 8 are also removed. In this way, the silicon dioxide film 23 remaining on the inner wall surface of the groove 12 becomes the field shield insulating film 5, and the polysilicon film 24 embedded therein becomes the field shield electrode 6.

Thereafter, as shown in FIG. 2D, a conventional MOS transistor formation process is performed on active region 8. That is, a gate insulating film 9 made of silicon dioxide having a film thickness of 10 to 14 nm is formed on the surface of the substrate 7 corresponding to the active region 8 by the thermal oxidation method, and arsenic of arsenic is formed using the polysilicon gate electrode 4 formed on the upper surface as a mask. Diffusion depth 0.1 μm, concentration 10 ¹⁷ ions / cm ² by ion implantation
A low-concentration low-concentration N-type diffusion layer 25 is formed, and these are used as the source and drain diffusion layers 2 and 3 of the N-type MOS transistor 1.

Further, as shown in FIG. 3 (e), a process is performed to make these transistors 1 have an LDD structure. That is, by using the insulating films 26, 26 formed on both side surfaces of the gate electrode 4 of each transistor 1 as a mask together with the gate electrode 4 and introducing arsenic, which is an N-type impurity, by an ion implantation method, a diffusion depth of about 0. A deep high-concentration N-type diffusion layer 27 having a thickness of 3 μm and a concentration of about 10 ¹⁸ to 10 ²¹ ions / cm ² is formed. Then, the high concentration N-type diffusion layer region 2
7 is located farther from the gate electrode 4 than the low-concentration N-type region 25, and thereby has an effect of preventing the short channel effect and lowering the resistance values of the source / drain diffusion layers 2 and 3. A silicon dioxide film 28 is formed on the surface of the field shield electrode 6 and the surfaces of the source and drain diffusion layers 2 and 3 by thermal oxidation.

Thereafter, as shown in FIG. 3F, an interlayer insulating film such as a silicate glass (BPSG) containing boron and phosphorus is formed on the surface of the wafer W, as in the process flow of a conventional general MOS device. 13 is formed.

Further, as shown in FIG. 3 (g), a contact hole forming step and a step of forming electrode wirings 16 and 17 in which conductive polysilicon, titanium / tungsten, aluminum, etc. are formed in a single layer or a laminated structure are performed. In this way, the MOS LSI of this embodiment is completed.

In the MOSLSI of this embodiment, the field shield insulating film 5 and the field shield electrode 6 are embedded in the groove 12 having a depth greater than the depth of the source / drain diffusion layers 2 and 3. Therefore, the separation distance between the diffusion layers 2 and 3 to be separated is a total length which is twice the width dimension and the depth dimension of the groove 12, which is substantially larger than that in the case of the non-embedded field shield separation structure. Increase. At this time, as the depth of the groove 12 becomes deeper than the depth of the source / drain diffusion layers 2 and 3, the insulation separation performance becomes higher.

In addition, in particular, in the case of this embodiment, the field shield electrode 6 does not extend on the substrate 7 and its upper surface is flush with the surface of the substrate 7, so that the field shield electrode is formed on the surface of the substrate 7. The area required for the isolation structure 11 is only the width of the groove 12, and the area of the inactive region 10 can be reduced as compared with the case of the conventional buried type field shield isolation structure. Therefore, by adopting the field / shield separation structure 11 in the present embodiment, miniaturization can be achieved, and the integration degree of the MOS LSI can be further improved.

According to the MOSLSI manufacturing method of this embodiment, after the polysilicon film 24 is formed on the field shield insulating film 5 by the vapor phase epitaxy method, the surface of the wafer W is flattened by the CMP method. Since the photolithography technique is not used, the manufacturing process can be simplified, and since the photomask is not used, the manufacturing cost can be reduced as compared with the case of the conventional field / shield separation structure. it can.

Next, a second embodiment of the present invention will be described with reference to FIG. The field shield separation structure in the MOS LSI of this embodiment differs from that of the first embodiment in that
The point is that the field shield insulating film has a multi-layer structure instead of a single-layer structure. Therefore, in FIG. 4, parts having the same functions as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 4, in this embodiment,
After forming the groove 12 on the surface of the silicon single crystal substrate 7, the insulating film 3 having a three-layer structure of a silicon dioxide film 30-a silicon nitride film 31-a silicon dioxide film 32 is formed on the inner wall surface of the groove 12 and the surface of the substrate.
3 (field shield insulating film 5) is formed, and further, polysilicon 24 is vapor-phase grown on the upper surface thereof, and then the wafer surface is flattened by the CMP method as in the first embodiment. The field shield electrode 6 made of 24 and the surface of the substrate 7 are processed into the same plane.

Here, for the insulating film 33 having the three-layer structure, the surface of the substrate 7 including the inner wall surface of the groove 12 is thermally oxidized to form a silicon dioxide film 30 having a film thickness of 2 to 4 nm. Obtained by forming a silicon nitride film 31 having a film thickness of 4 to 12 nm by a vapor phase growth method, and then thermally oxidizing the silicon nitride film 31 to form a silicon dioxide film 32 having a film thickness of 1 to 4 nm. It is a thing.

Subsequent steps are exactly the same as those in the first embodiment, and a gate insulating film forming step, a gate electrode forming step, a source / drain diffusion layer forming step, an interlayer insulating film forming step, a contact hole forming step, an electrode wiring forming step. The MOSLSI of FIG. 4 is completed through the steps. In the case of this embodiment,
Each of the electrode wirings 16 and 17 has an aluminum wiring in which a titanium nitride-tungsten film is sequentially buried in the opening, extends to the upper surface of the interlayer insulating film in the opening, and is connected to another element electrode.

Also in the case of this embodiment, as in the case of the first embodiment, the field shield separation structure 11 composed of the field shield insulating film 5 and the field shield electrode 6 is provided on the substrate 7.
Since it does not extend onto the surface, the degree of integration can be improved, and at the same time, the upper surface of the field shield electrode 6 is covered with the substrate 7.
Since the means for making the surface the same as the surface is a simple flattening process step by the CMP method, a MOSLSI with a high degree of integration can be manufactured economically.

Further, in this embodiment, since the silicon dioxide films 30 and 32 and the silicon nitride film 31 are used as the films forming the field shield insulating film 5, the field shield insulating film 5 is effectively thinned. Insulation separation effect can be enhanced. Further, the multi-layer insulating film 33 formed of the silicon dioxide films 30 and 32 and the silicon nitride film 31 becomes an insulating film having an excellent shielding property even if phosphorus or boron is introduced into the polysilicon 24 forming the field shield electrode 6. That is, according to this embodiment, by forming the field shield insulating film 5 as a multilayer composite film, it is possible to effectively form an insulating film having a smaller film thickness as compared with a single-layer film with fewer defects. It is possible to improve the retention, improve the economical efficiency, and enhance the insulation separation effect.

In the first and second embodiments, the CMP method is used as a means for flattening the surface of the wafer W after the polysilicon film 24 is formed, but instead of this, a photoresist is used. An etch back method in which the entire surface of the wafer is dry-etched after being applied thickly, or a flattening corrosion method by wet etching in a fluid of a mixed etching solution containing hydrofluoric acid and nitric acid as main components may be used. Even when these methods are used, similar to the above-mentioned embodiment,
The effects of simplifying the manufacturing process and reducing the manufacturing cost can be achieved.

The field shield electrode does not have to fill the entire inside of the groove as in these embodiments, but has a structure in which voids exist inside the electrode, or following vapor phase growth of a polysilicon film. A structure may be adopted in which the silicon dioxide film is vapor-phase grown again, and then the CMP method is performed to fill the insulating film.

The various sizes are not limited to those in these embodiments, and for example, as an example of other sizes, the width of the groove is 8
0 nm to several mm, groove depth of source / drain diffusion layer depth of 10 μm, field shield film thickness of 5
~ 200 nm, the thickness of the polysilicon film is 40-800 n
It can be about m.

Further, the silicon dioxide film in the second embodiment
The insulating film having a three-layer structure of a silicon nitride film-a silicon dioxide film can exhibit the effect as a multi-layer composite film even if one of the silicon dioxide films is omitted and the two-layer structure is formed.

Next, a third embodiment of the semiconductor device of the present invention will be described with reference to FIG. This embodiment particularly shows the relationship of voltage application to the field shield electrode, and FIG. 5 is a cross-sectional view showing the vertical structure and connection of the MOS LSI of this embodiment.

As shown in FIG. 5, an N-type region 36 called N-Well is formed on the surface of the P-type single crystal silicon substrate 35, and a P-type MOS transistor TR is formed in this region 36.
p is formed. On the other hand, N-type MOS transistors TRN1 and TRN2 are formed on the surface of the P-type substrate 35, and the semiconductor device of this embodiment constitutes an LSI having a CMOS structure.

N-type MOS transistors TRN1 and TRN2
Isolation is done by the field shield isolation structure formed in the groove between these transistors.
An electrode wiring FSn is led out from the shield electrodes 37, 37. Regarding the N-type MOS transistor TRN1, the gate electrode 38 to the electrode wiring Gn, the N-type source diffusion layer 39 to the electrode wiring Sn, the N-type drain diffusion layer 40 to the electrode wiring Dn, and the P-type substrate 35 to the P-type. The electrode wiring SBn is led out through the diffusion layer 41.

On the other hand, the P formed in the N-Well 36
The isolation of the type MOS transistor TRP is also made by the field shield isolation structure similar to that between the N type MOS transistors, and the electrode wiring FSp is derived from the field shield electrodes 42, 42. In addition, P-type MO
Regarding the S transistor TRP, the electrode wiring Gp from the gate electrode 43 to the electrode wiring S from the P-type source diffusion layer 45.
p is the P-type drain diffusion layer 44 to the electrode wiring Dp is N
-Electrode wiring S from Well 36 through N-type diffusion layer 46
Bp is derived respectively. Each electrode wiring extends in parallel with the surface of the substrate 35 and on the upper surface of the interlayer insulating film 47.

Here, the N-type MOS transistor TRN1
, TRN2, and between the P-type MOS transistor TRP and the field shield isolation structure, the field shield insulating films 48 and 49 have the single-layer structure of the first embodiment and the multilayer composite film structure of the second embodiment. Either may be adopted.

In the semiconductor device of this embodiment, a substrate potential generating circuit (not shown) is connected to the electrode wiring SBn for applying a potential to the P-type substrate 35 to supply a negative potential of -1 to -3V. At the same time, the substrate potential generating circuit is also connected to the electrode wiring FSn connected to the field shield electrode 37 on the N-type MOS transistors TRN1 and TRN2 side, so that a similar negative potential is supplied to the field shield electrode 37. It is configured to.

On the other hand, the electrode wiring FSp connected to the field shield electrode 42 on the P-type MOS transistor TRP side.
Is originally provided to supply a word line drive potential and an output buffer drive potential (not shown).
Is connected to the field shield electrode 4
2 is supplied with a boosted potential of a power supply voltage of Vcc + 2Vtn (Vtn is a threshold value of an N-type MOS transistor).

According to this embodiment, also in the semiconductor device having the CMOS structure, the field shield isolation structure embedded in the trench formed in each of the N-type MOS transistor isolation region and the P-type MOS transistor isolation region is provided. Similar to the first and second embodiments, it is suitable for miniaturization, and the degree of integration of MOSLSI can be improved.

Further, the N-type MOS transistor TRN1
, And the negative potential is supplied to the field shield electrode 37 on the TRN2 side, and the boosted potential of the power supply voltage is supplied to the field shield electrode 42 on the P-type MOS transistor TRP side. Compared to the case of the conventional field shield isolation structure that supplies a potential, the margin for overshoot and undershoot of the diffusion layer potential becomes large, and more stable element isolation performance can be exhibited.

That is, according to the semiconductor device of the present embodiment, by adopting the trench type (groove type) field shield isolation structure in the CMOS structure LSI, a good insulation isolation function between transistors or diffusion regions can be obtained. Can be achieved at high density, and future VLSI implementation can be facilitated.

Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Is. Further, the field shield separation structure of the present invention can be applied to separation of general elements in various semiconductor devices such as memories such as DRAM, logic, microcomputer LSI and the like. further,
Not only a semiconductor device having a CMOS structure but also a PMOS structure,
Of course, it can be applied to element isolation in a semiconductor device having an NMOS structure.

[0052]

As described above in detail, according to the semiconductor device of the present invention, the field shield insulating film, the field shield film and the field shield insulating film are provided inside the groove having a depth not less than the depth of the diffusion layer forming the element. Since the shield electrode is buried,
The separation distance between the diffusion layers to be separated is electrically the total length of twice the width and depth of the groove, which is substantially increased as compared with the case of the non-embedded field shield separation structure. In addition, in the case of the semiconductor device of the present invention, since the upper surface of the field shield electrode is flush with the surface of the semiconductor substrate, the area required for the field shield separation structure on the substrate surface is only the width of the groove. Since it is possible to achieve miniaturization as compared with the case of the conventional buried type field shield separation structure, it is possible to further improve the integration degree of the MOS LSI.

When a negative potential is supplied to the field shield electrode on the N-type element isolation region side and a boosted potential of the power supply voltage is supplied to the P-type element isolation region side, an overshoot occurs when the diffusion layer potential changes. Since the margin of the diffusion layer potential limit value with respect to or undershoot increases, the margin of insulation isolation performance increases, and more stable element isolation performance can be exhibited.

Further, when the field shield insulating film has a two-layer structure or a three-layer structure consisting of a silicon dioxide film and a silicon nitride film, the effective film thickness can be made thin and a film with few defects can be formed as a whole. Therefore, the yield can be improved, the economic efficiency can be improved, and the insulation separation effect can be improved.

On the other hand, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor device which can cope with the above miniaturization can be easily manufactured. For example, in the third step, a material to be the field shield electrode is formed on the field shield insulating film by a vapor phase growth method of silicon so as to have a film thickness equal to or larger than the depth of the groove, and then chemically formed. When the material is flattened by any one of the mechanical polishing method, the etchback method, and the flattening corrosion method by wet etching,
Since the field shield electrode whose upper surface is flush with the substrate surface can be formed without using the photolithography technique, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 shows a semiconductor device according to a first embodiment of the present invention,
It is the longitudinal cross-sectional view which follows the AA line of (a) and (b), and (b) top view.

FIG. 2 is a first half of a diagram showing a method of manufacturing a semiconductor device step by step.

FIG. 3 is the latter half.

FIG. 4 is a vertical sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a vertical sectional view showing a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

 1 N-type MOS transistor (element) 2 Source diffusion layer 3 Drain diffusion layer 4, 38, 43 Gate electrode 5, 48, 49 Field shield insulating film 6, 37, 42 Field shield electrode 7 Semiconductor substrate 8 Active region 9 Gate Insulating film 10 Inactive region 11 Field shield isolation structure 12 Groove 24 Polysilicon film (material) 30,32 Silicon dioxide film 31 Silicon nitride film 33 Three-layer insulating film 35 P-type substrate 39 N-type source diffusion layer 40 N Type drain diffusion layer 44 P type source diffusion layer 45 P type drain diffusion layer

Claims (13)

[Claims] 1. A field-shield insulating film and a field-shield electrode for electrically insulating and separating a plurality of elements formed on a semiconductor substrate.
In a semiconductor device having a shield separation structure, a depth equal to or larger than a depth of a diffusion layer which is opened on the front surface side of the semiconductor substrate and constitutes the element is formed in an inactive region where the field shield separation structure is formed. A groove is formed,
The field shield insulating film is deposited on the inner wall surface of the groove, the field shield electrode is embedded therein, and the upper surface of the field shield electrode is flush with the surface of the semiconductor substrate. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein at least one of a negative potential on the N-type element isolation region side and a boosted potential of a power supply voltage on the P-type element isolation region side with respect to the field shield electrode. A semiconductor device characterized in that one of them is supplied. 3. The semiconductor device according to claim 1, wherein the field shield insulating film is a silicon dioxide film formed on the inner wall surface side of the groove and a nitride film formed on the field shield electrode side. A semiconductor device having a two-layer structure of a silicon film. 4. The semiconductor device according to claim 1, wherein the field shield insulating film is a silicon nitride film formed on the inner wall surface side of the groove and a dioxide film formed on the field shield electrode side. A semiconductor device having a two-layer structure of a silicon film. 5. The semiconductor device according to claim 1, wherein the field shield insulating film is sequentially formed from the inner wall surface side of the groove toward the field shield electrode side. A semiconductor device comprising a three-layer structure of silicon film-silicon dioxide film. 6. A method of manufacturing a semiconductor device comprising a field shield isolation structure having a field shield insulating film and a field shield electrode for electrically insulating and isolating a plurality of elements formed on a semiconductor substrate. A first step of forming, in an inactive region in which the field / shield separation structure is formed, a groove having a depth equal to or greater than a depth of a diffusion layer forming the element, the groove being opened to the front surface side of the semiconductor substrate; A second step of forming the field shield insulating film covering the inner wall surface of the groove, and forming a field shield electrode in the groove whose upper surface is flush with the surface of the semiconductor substrate A method of manufacturing a semiconductor device, comprising the third step of: 7. The method for manufacturing a semiconductor device according to claim 6, wherein in the third step, a material to be the field shield electrode is formed on the field shield insulating film, and the material is formed. After filling the inside of the groove, the upper surface of the field shield electrode is made flush with the surface of the semiconductor substrate by flattening the material until the surface of the semiconductor substrate is exposed. Manufacturing method of semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the third step, the film formation of the material is performed by a vapor phase epitaxy method of silicon, and the flattening of the material is performed by a chemical mechanical method. A method of manufacturing a semiconductor device, which is performed by a polishing method. 9. The method of manufacturing a semiconductor device according to claim 7, wherein in the third step, the film formation of the material is performed by a vapor phase epitaxy method of silicon, and the flattening of the material is an etch back method. A method for manufacturing a semiconductor device, comprising: 10. The method of manufacturing a semiconductor device according to claim 7, wherein in the third step, the film formation of the material is performed by a vapor phase growth method of silicon, and the flattening of the material is performed by wet etching. A method of manufacturing a semiconductor device, which is performed by a flattening corrosion method. 11. The method of manufacturing a semiconductor device according to claim 6, wherein in the second step, a silicon dioxide film and a silicon nitride film are sequentially stacked from the inner wall surface side of the groove. A method of manufacturing a semiconductor device, comprising forming a field shield insulating film having a two-layer structure composed of these films. 12. The method of manufacturing a semiconductor device according to claim 6, wherein in the second step, a silicon nitride film and a silicon dioxide film are sequentially laminated from the inner wall surface side of the groove. A method of manufacturing a semiconductor device, comprising forming a field shield insulating film having a two-layer structure composed of these films. 13. The method of manufacturing a semiconductor device according to claim 6, wherein in the second step, a silicon dioxide film, a silicon nitride film and a silicon dioxide film are sequentially formed from the inner wall surface side of the groove. A method for manufacturing a semiconductor device, which comprises forming a field shield insulating film having a three-layer structure composed of these films by stacking.