JPH08330978A - Error correction system - Google Patents

Abstract

PURPOSE: To realize the error correction system which detects erroneous correction occurring at the time of error correction to prevent the erroneous correction. CONSTITUTION: An error detection code encoder 3 generates a CRC code to add it to input data. A Reed Solomon code encoder 5 generates a Reed Solomon code from an input data sequence to add it to the data sequence. A convolutional code encoder 7 subjects input data to known convolutional code encoding. A Viterbi decoder 10 performs decoding correspondingly to convolutional code encoding. A Reed Solomon code decoder 12 uses the Reed Solomon code to restore the original data. An error detector 14 uses the CRC code to detect the error of data encoded by the error detection code encoder 3 in the transmission system. A selector 17 selects one of delay circuits 15 and 16 by an output control signal 20 of the error detector 14. A speed converter 18 converts the time width of output data of the selector to the same time width as transmission data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction system, and more particularly to an error correction system for detecting and correcting an error in data transmitted in digital radio communication.

[0002]

2. Description of the Related Art Conventionally, data transmitted by digital radio communication or the like is transmitted and received by adding an error correction code to the data in consideration of an error at the time of transmission, and the data is received by using a reception error correction code in a receiving system. Is detected and corrected (for example, Japanese Patent Laid-Open No. 1-228327).

FIG. 3 is a block diagram showing an example of a conventional error correction system. FIG. 3A shows a transmission system and FIG. 3B shows a reception system. First, the conventional transmission system of FIG. 3A will be described. The data serially input from the input terminal 1 is supplied to the speed converter 2 so that the time width of the input data is shortened equally. The series data on the finite field (Gallowa field) GF (2) taken out in series from the speed converter 2 is supplied to the serial-parallel converter 4 and serial-parallel converted to the series data on GF (256). Then, it is input to the Reed-Solomon encoder 5.

The Reed-Solomon encoder 5 generates a Reed-Solomon code, which is an error correction code, by using a predetermined generator polynomial for a certain set of parallel data. The data and Reed-Solomon code extracted from the Reed-Solomon encoder 5 are supplied to a parallel-serial converter 6 and subjected to parallel-serial conversion, and then supplied to a convolutional encoder 7 where they are convolutionally encoded and output from an output terminal 8. It The data output from the output terminal 8 is wirelessly transmitted via a transmitter (not shown).

The wirelessly transmitted data is received by a receiving section (not shown) of the receiving system, and then supplied to the Viterbi decoder 10 through the input terminal 9 of FIG. 3B and is supplied to the convolutional encoder 7. Viterbi decoding, which is a corresponding error correction process, is performed. The received data output from the Viterbi decoder 10 is converted from the series on GF (2) to GF by the serial-parallel converter 11.
(256) After serial-to-parallel conversion to the above sequence, it is input in parallel to the Reed-Solomon decoder 12, and data error detection and error correction are performed using the Reed-Solomon code and a predetermined generator polynomial.

The parallel-serial converter 13 converts the received data of the series on GF (256) output from the Reed-Solomon decoder 12 into a series on GF (2) and outputs it to the speed converter 18. The reception data input to the speed converter 18 is converted into data having the same time width as the transmission data and then output to the output terminal 19.

[0007]

However, in the above-mentioned conventional error correction system, the size of the error in the data can be corrected when the Reed-Solomon code is decoded, but the error is corrected when the size exceeds a certain size. It will be impossible. In the case where this cannot be corrected, it is erroneously corrected to another code word that the size of the erroneous data is correctable when viewed from another code word. In particular, in data such as multiplexed data in which multiple types of data are multiplexed in one frame, if error correction occurs when error correction is performed using the Reed-Solomon code, all data in one frame Data may be erroneous.

The present invention has been made in view of the above points,
An object of the present invention is to provide an error correction method that detects an error correction that occurs during error correction and prevents the error correction.

[0009]

In order to achieve the above object, the present invention provides an error detection encoder that adds an error detection code to transmission data, and an error that adds an error correction code to output data of the error detection encoder. A correction encoder and a transmission means for transmitting the output data series of the error correction encoder are provided on the transmission side, and a receiving means for receiving the transmitted data series and an error correction code for the received data series from the receiving means are provided. Decoder for error correction of received data sequence using, error detector for error detection of data sequence by using error detection code of output data sequence of decoder, error detection when error is not detected by error detector The data in the output data sequence of the decoder is selected based on the output control signal of the decoder, and when an error is detected by the error detector, the data from the receiving means based on the output control signal of the error detector is selected. And a selector for selecting the data in the transmit data series to the receiving side is obtained by the configuration obtaining received data from the selector.

[0010]

In the present invention, an error detection code is added to generate an error correction code for a data sequence, and the error correction code is added and transmitted.
An error detection code using the error detection code is detected from the output data sequence of the decoder decoded using the error correction code, and it is determined based on the detection result of the error detector whether or not the error correction decoding is correctly performed by the decoder. Therefore, when an error is detected, it is judged that the data which has not been correctly error-corrected and decoded by the decoder and is erroneously corrected or the uncorrectable data is output, and the output data which is not decoded by the decoder is selectively output. You can

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of an error correction system according to the present invention. FIG. 1A shows a transmission system and FIG. 1B shows a reception system. In the figure, the same components as those in FIG. 3 are designated by the same reference numerals. As shown in FIG. 1A, the transmission system of this embodiment has a rate converter 2, an error detection encoder 3, a serial-parallel converter 4, a Reed-Solomon encoder 5, a parallel-serial converter 6 and a convolutional encoder 7. It is composed of

The speed converter 2 uses the time width (speed) of input coded data from the input terminal 1 (this is multiplexed data in which a plurality of types of data are multiplexed in one frame in this embodiment). ) Is shortened so that it becomes the same as when the Reed Solomon code described later is added. The error detection encoder 3 is a circuit that generates an error detection code for detecting an error in the reception system in the encoded data and adds the error detection code to the encoded data. As an example of the error detection code, the error detection encoder 3 is a cyclic circuit. -There is a redundancy check (CRC) code.

In this CRC code, assuming that the information sequence is a sequence on the Galois field GF (2), a generator polynomial G for the polynomial expression I (x) of the information sequence consisting of k-bit elements.
When the degree of (x) is (nk), the transmission polynomial C (x) having a CRC code is defined as the following equation.

C (x) = I (x) x ^n−k + R (x) where R (x) is the generator polynomial G of I (x).
It is a remainder polynomial obtained by dividing by (x).

At this time, even if an error occurs in C (x) during transmission, it is possible to detect errors up to (nk) in length.
At this time, the error length is the number of bits between the lowest erroneous bit and the highest erroneous bit on C (x).
Particularly, as the generator polynomial G (x), a polynomial of G (x) = 1 + x ⁵ + x ¹² + x ¹⁶ is often used according to the recommendation of the International Telegraph and Telephone Consultative Committee (CCITT). C (x) in this case
Is the information sequence I (x) of k bits, and I (x) is G
It is a sequence in which the remainder divided by (x) is added with 16 bits.

The serial-parallel converter 4 is a circuit for converting a serially input data series into parallel data and outputting the data series.
The input data series C (x) on F (2) is converted into a data series on GF (256) which is a series in which the number of elements is 256 and the operation is valid, and is output. At this time, in the parallel portion, each element on GF (256) is represented by 8 bits by bit representation. The serial-parallel converter 4 is
It has a function of collecting a series on GF (2) by 8 bits into one symbol and outputting it as a series on GF (256).

The Reed-Solomon encoder 5 generates a Reed-Solomon code from the input data series and adds it to the data series. The parallel-serial converter 6 is a circuit for converting a data sequence input in parallel to serial and outputting the same, and in this embodiment, GF (2
56) Converts the input data sequence above into a data sequence above GF (2) and outputs it. The convolutional encoder 7 performs known convolutional encoding on the input data.

As shown in FIG. 1B, the receiving system of this embodiment has a Viterbi decoder 10, a serial-parallel converter 11, a Reed-Solomon decoder 12, a parallel-serial converter 13, an error detector 14, It comprises delay circuits 15 and 16, a selector 17, and a speed converter 18.

The Viterbi decoder 10 performs decoding corresponding to convolutional coding. Similar to the serial-parallel converter 4 of the transmission system, the serial-parallel converter 11 has a function of collecting the 8-bit series on GF (2) into 1 symbol and outputting it as a series on GF (256). The Reed-Solomon decoder 12 restores the original data using the Reed-Solomon code. The parallel-serial converter 13 has the same GF as the parallel-serial converter 6 of the transmission system.
The input data sequence in (256) is converted into a data sequence in GF (2) and output.

The error detector 14 detects an error in the data encoded by the error detection encoder 3 of the transmission system by using an error detection code (here, a CRC code). The delay circuit 15 delays the output data of the parallel-serial converter 13 for the time from the data input of the error detector 14 to the output of the error detection result.

In the delay circuit 16, the output data of the Viterbi decoder 10 is serial-parallel converter 11, Reed-Solomon decoder 12,
Selector 1 through parallel-serial converter 13 and error detector 14
The data output from the Viterbi decoder 10 is delayed by the time until the data is input to 7. The selector 17 selects one of the delay circuits 15 and 16 by the output control signal 20 of the error detector 14. The speed converter 18 converts the time width of the output data of the selector into the same time width as the transmission data.

Next, the operation of this embodiment having the above configuration will be described. First, to explain the operation of the transmission system,
The transmission data input to the input terminal 1 is supplied to the speed converter 2, where it is assumed that the transmission period of the continuous k-bit data D1 to Dk is the frame length T as shown in FIG. In order to prevent the original time length T from being exceeded even if an error detection code to be described later is multiplexed on these k-bit data D1 to Dk, FIG.
As shown in (B), the time width is converted to be shorter.

As shown in FIG. 2B, the transmission data whose time width has been converted is supplied to the error detection encoder 3, where the polynomial I (x) of the input data is generated as a generator polynomial G (x).
The 16-bit remainder R (x) obtained by dividing by is added to the transmission data as a CRC code which is an error detection code and is supplied to the serial-parallel converter 4. G1 to G shown in FIG.
Reference numeral 16 represents the above 16-bit CRC code.

The serial-parallel converter 4 is input in series, as shown in FIG.
The transmission data of (B) and the 16-bit C shown in (C) of FIG.
The data sequence on GF (2), which is time-series combined data with the RC code, is grouped by 8 bits, and the collected 8 bits are converted into a data sequence on GF (256) as one symbol, and are parallel to 8 bits. It is supplied to the Reed-Solomon encoder 5.

The Reed-Solomon encoder 5 has a total of {(k / (k / 8)) symbols of k bits of data input in parallel and 2 (= 16/8) symbols of 16-bit CRC code.
8) +2} symbol data, and generate a check word defined as a solution of a predetermined simultaneous equation, that is, a Reed-Solomon code, and generate {(k / 8) +
After being added to the 2} symbol data, the data is supplied in parallel to the parallel-serial converter 6.

The parallel-serial converter 6 receives the GF input in parallel.
The sequence on (256) is converted into the sequence on GF (2) and the data is serially supplied to the convolutional encoder 7. The convolutional encoder 7 performs convolutional encoding such as a cross interleave code on the input data sequence in order to further enhance the error correction decoding capability. The output encoded data of the convolutional encoder 7 is transmitted from the output terminal 8 after being subjected to predetermined transmission processing such as amplification and modulation by a transmission unit (not shown).

The above-mentioned transmitted encoded data is received and demodulated by a receiving section (not shown) of the receiving apparatus, and then the data shown in FIG.
It is supplied to the Viterbi decoder 10 via the input terminal 9 of (B), where error correction processing for the encoding in the convolutional encoder 7 of the transmission system is performed and it is equivalent to the input data sequence of the convolutional encoder 7. Data series is restored.

The received data series taken out serially from the Viterbi decoder 10 is supplied to the serial-parallel converter 11 and GF
(2) The sequence above is converted into the sequence above GF (256) and supplied to the Reed-Solomon decoder 12. The Reed-Solomon decoder 12 performs decoding corresponding to the encoding by the Reed-Solomon encoder 5 of the transmission system on the input data series, and corrects and restores error data. However, the number of error data that can be corrected and restored by the Reed-Solomon decoder 12 is limited to a certain value according to the number of words of the Reed-Solomon code.

The data series on GF (256) taken out in parallel by the Reed-Solomon decoder 12 is converted into a data series on GF (2) by the parallel-serial converter 13, and the error detector 14 and the delay circuit 15 are converted. Are input respectively.
The error detector 14 is C included in the serial input data sequence.
Error detection processing is performed using the RC code. Here, when the Reed-Solomon decoder 12 correctly corrects the error, there is no error detected by the error detector 14, but when the error is corrected or cannot be corrected, the error is detected. Is detected (provided that the data is correctly decoded by the Viterbi decoder 10).

Therefore, the error detector 14 generates a control signal 20 according to the detection error result and applies it as a select signal to the selector 17, and when the error is not detected, the error correction by the Reed-Solomon decoder 12 is normally performed. The selector 17 selects the output data sequence of the Reed-Solomon decoder 12 extracted from the delay circuit 15 when it is determined that the output data sequence is present. On the other hand, when an error is detected, the error detector 14 judges that there is erroneous correction or uncorrectable data by the Reed-Solomon decoder 12, and the Viterbi decoder extracted by the Reed-Solomon decoder 12 is not extracted by the delay circuit 16. The output data sequence of 10 is selected by the selector 17.

Here, in the delay circuit 15, after the output data series of the parallel-serial converter 13 is input to the error detector 14, an operation for error detection and a control signal 20 are generated according to the operation result. Time corresponding to the time to be done,
It is a circuit for delaying the output data series of the parallel-serial converter 13 for time adjustment. In addition, the delay circuit 16 is
The data sequence output from the Viterbi decoder 10 is serial-parallel converter 11 and Reed-Solomon decoder 1 from the output time point.
2. A circuit for adjusting the time for delaying the output data sequence of the Viterbi decoder 10 for a time corresponding to the time when it is input to the selector 17 through the parallel-serial converter 13 and the error detector 14 (or the delay circuit 15). is there.

The selector 17 performs a selecting operation according to the above control signal and outputs only the data in the input data series (does not output redundant bits such as CRC code and Reed Solomon code) to the speed converter 18. Supply. The speed converter 18 converts the input data into the same time width as the input transmission data of the input terminal 1 and outputs it to the output terminal 19 as reception data.

As described above, according to the present embodiment, it is judged that the error correction by the Reed-Solomon decoder 12 is normally performed only when the error detector 14 does not detect the error, and the Reed-Solomon decoder 12 detects the error correction. When the error detector 14 detects an error, the Reed-Solomon decoder 12 judges that there is erroneous correction or uncorrectable data. Since the data of the output data series of the Viterbi decoder 10 that has not been decoded by the Reed-Solomon decoder 12 is subjected to speed conversion and output to the output terminal 19, there is erroneous correction or uncorrectable data by the Reed-Solomon decoder 12. In some cases, the Reed-Solomon decoder 12 outputs the data with some errors from the Viterbi decoder 10. Completely prevented that another data has been output the original data.

Therefore, according to the present embodiment, in the case of data in which a plurality of types of data are multiplexed in one frame, such as multiplexed data, many errors are caused by the Reed-Solomon decoder 12 due to erroneous correction or uncorrectability. By outputting the reception data containing the error-free data rather than outputting the data erroneously, it is possible to obtain the data with less deterioration in reproduction quality as compared with the conventional case.

The present invention is not limited to the above embodiment, and the error correction code may be an adjacent code or other error correction code other than the Reed-Solomon code. Also, an error detection code other than the CRC code is possible.

[0036]

As described above, according to the present invention,
An error detection code is generated by adding an error correction code to the data sequence, and then transmitted and received, and the decoder output data sequence decoded using the error correction code is subjected to error detection using the error detection code. , If the error is detected correctly by the decoder based on the detection result, when the error is detected, the error-corrected data which is not correctly error-corrected by the decoder and the error-corrected data or the uncorrectable data is output. Since it is determined that the received data has not been decoded by the decoder and the selected data is output, it is possible to prevent the output of erroneously corrected data that is significantly different from the original data.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the system of the present invention.

FIG. 2 is a diagram showing a signal format of a main part of FIG.

FIG. 3 is a block diagram of an example of a conventional method.

[Explanation of symbols]

 1 transmission multiplexed data input terminal 2, 18 speed converter 3 error detection encoder 4, 11 serial-parallel converter 5 Reed-Solomon encoder 6, 13 parallel-serial converter 7 convolutional encoder 8 transmission data output terminal 9 reception data input Terminal 10 Viterbi Decoder 12 Reed-Solomon Decoder 14 Error Detector 15, 16 Delay Circuit 17 Selector 19 Received Data Output Terminal

Claims (3)

[Claims] 1. An error detection encoder that adds an error detection code to transmission data, an error correction encoder that adds an error correction code to output data of the error detection encoder, and an output data sequence of the error correction encoder. And a receiving means for receiving the transmitted data series, and an error correction of the received data series by using the error correction code of the received data series from the receiving means. Decoder for performing, error detector for performing error detection of the data sequence using the error detection code of the output data sequence of the decoder, and output control of the error detector when no error is detected by the error detector The data in the output data sequence of the decoder is selected based on the signal, and when an error is detected by the error detector, the receiving means based on the output control signal of the error detector. An error correction system characterized in that the receiving side has a selector for selecting the data in the received data sequence, and the received data is obtained from the selector. 2. The error correction code is a Reed-Solomon code, the error detection code is a CRC code, and the transmission data extracted from the error detection encoder and the CR
The transmission data is subjected to speed conversion so that the frame length of the time-series combined data sequence with the C code becomes equal to the frame length of the transmission data input to the error detection encoder, and the error detection encoder is subjected to the speed conversion. The error detection system according to claim 1, further comprising a speed converter for inputting. 3. A first rate converter for shortening each time width of transmission multiplexed data equally, and an error for generating and adding a CRC code based on the output transmission multiplexed data of the first rate converter. A detection encoder, a first serial-parallel converter that serial-parallel converts the output multiplexed data of the error detection encoder, and a Reed-Solomon code based on the parallel output multiplexed data of the first serial-parallel converter. A Reed-Solomon encoder for generating and adding the Reed-Solomon code to the input multiplexed data for output; a first parallel-serial converter for parallel-serial converting the parallel output multiplexed data of the Reed-Solomon encoder; A convolutional encoder for performing convolutional coding on the output multiplexed data sequence of the first parallel-serial converter; transmitting means for transmitting the output multiplexed data sequence of the convolutional encoder; and the transmitted multiplexing. data Receiving means for receiving a sequence, Viterbi decoder for performing decoding corresponding to the convolutional code on the multiplexed data sequence received by the receiving means, and multiplexed data sequence serially output from the Viterbi decoder And a Reed-Solomon decoder for decoding the parallel output multiplexed data sequence of the second serial-parallel converter based on the Reed-Solomon code, and a Reed-Solomon A second parallel-serial converter that parallel-serial converts the multiplexed data series output in parallel from the decoder, and error detection based on the CRC code for the output multiplexed data series of the second parallel-serial converter And an error detector that outputs a control signal according to the error detection result, and time-adjusts the output control signal of the error detector with respect to the output multiplexed data sequence of the parallel-serial converter. 1 delay circuit, a second delay circuit for time-aligning the output multiplexed data sequence of the Viterbi decoder with the output control signal of the error detector, and when no error is detected by the error detector A selector that selects the output multiplexed data of the first delay circuit and selects the output multiplexed data of the second delay circuit when the error is detected; and a speed conversion of the output multiplexed data of the selector. And a second rate converter having the same rate as that of the transmission multiplexed data.