JPH08329684A - Memory device - Google Patents

Abstract

PURPOSE: To provide a memory circuit for users in which readout failure at the time of the power source voltage drop is avoided by supplying a raised power source voltage to the sense amplifier circuit. CONSTITUTION: When the power source voltage drops, the sense amplifier circuit 18 on the side of memory transistor group 16 as memory circuit for users approaches the lower limit of its regular readout operation range. And failure occurs in the readout of data of '1' at a sense amplifier circuit 1F on the side of monitor memory circuit 1C where the lower limit is higher than the side of the circuit 16, and a value different from the expected one is read out. As the result, an expected value judging circuit 1G outputs a signal L announcing the approach to the lower limit of regular operation range on the side of the circuit 16 at the rising time of E signals, system clocks, and is inputted into a booster circuit 41 through a line 1H. During the period of outputting this signal L, a voltage twice the usual power source voltage is supplied to the circuit 18 as power source voltage. Through this, the narrowing of the variation width of the bias voltage, which is one factor to cause readout failure by drop of power source voltage is restored, and thereby the margin of readout operation of the circuit 16 at the time of low voltages is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for improving a read margin of data from a user memory circuit when a microcomputer operates at a low voltage.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a memory device provided in a conventional microcomputer disclosed in, for example, Japanese Patent Application No. 5-206266, in which 11 is an address bus, 12 is a data bus, and 13 is a data bus. Is a system clock signal (hereinafter referred to as E signal) line for operating the memory circuit.

Reference numeral 14 is an address decoder circuit for decoding an address signal, 15 is a selector circuit for selecting a bit line of a user memory circuit, and 16 is for a user having a plurality of memory transistors (hereinafter referred to as memory Tr) 1A. A memory transistor group as a memory circuit, 17 is a sense amplifier control circuit, and 18 is a sense amplifier circuit for identifying the state of the memory Tr1A.

Further, 19 is a word line for selecting the memory Tr1A, 1B is a bit line for selecting the memory Tr1A, 1C is a monitor memory circuit having another memory Tr, 1D is a monitor memory circuit 1C. Bit line, 1
E is a selector circuit connected to the monitor memory circuit 1C.

Further, 1F is a sense amplifier circuit for the monitor memory circuit 1C, and 1G is whether or not the data of the monitor memory circuit 1C read from the sense amplifier circuit 1F matches a preset expected value. It is an expected value determination circuit for determining.

The operation when the user memory circuit in the microcomputer outputs data based on the E signal which is the system clock will be described with reference to the timing chart of FIG.

That is, in FIG. 9, the E signal indicated by the symbol S1 is the Vcc level of the power supply voltage (hereinafter, "H").
The address signal S2 of the memory transistor group 16 to be read is output from the CPU to the address bus 11.

At this time, the address is temporarily set to the indefinite period t1.
However, after that, the word line 19 is decoded by the address decoder circuit 14 during the time t2 and input to the memory Tr group 16 in which the memory Tr1A is arranged in a matrix.
Choose one.

At the same time, the bit line 1B connected to the memory Tr group 16 selected by the word line 19 is connected to the selector circuit 1
5 to obtain a required set of memories Tr1A. In all of the above read preparation operations, the E signal S1 is "H".
Done between.

Next, the E signal S1 is changed to the GND level (hereinafter, "
L ”), the sense amplifier circuit 18 starts operating, and during the time t3, the data“ 1 ”or“ 0 ”is identified from the state of the set of memories Tr1A selected in the read preparation stage. , "1" or "0" of the data is output to the data bus 12, and the data reading is completed.

Next, the operation of identifying the data of the memory Tr1A in the sense amplifier circuit 18 will be described by taking the circuit of FIG. 10 as an example. In FIG. 10, 31 and 32 are P-channel transistors (hereinafter referred to as PchTr), 33 and 3
Reference numeral 4 is an N-channel transistor (hereinafter referred to as NchTr), and 35 is an inverter.

The source terminal of PchTr31 is connected to Vcc, the gate terminal is GND, and the drain terminal is NchT.
It is connected to the drain terminal of r33 and the gate terminal of NchTr34.

The source terminal of the NchTr 33 is connected to GND, the gate terminal is connected to the source terminal of the NchTr 34, and further connected to the bit line 1B.

The drain terminal of NchTr34 is PchT
It is connected to the drain terminal of r32 and the input terminal of the inverter 35. The source and gate terminals of PchTr32 are connected to Vcc and GND, respectively.

In the above circuit, the memory Tr1A
Voltage V1 which is the information of the bit line 1B according to the state of
Is the gate terminal of NchTr33 and NchTr3
4 is input to the source terminal.

Then, by this voltage V1, NchTr3
NchT by changing the conductance of 3
It can be seen that the bias voltage V2 applied to the gate terminal of r34 changes.

That is, when the potential of V1 becomes maximum, the bias voltage V2 becomes the minimum value V2L, and when V1 becomes minimum, V2 becomes V2.
Becomes the maximum value V2H.

On the other hand, the input voltage V0 of the inverter 35 is N
It changes according to the amount of change in the conductance of chTr34, that is, the amount of change in V2. That is, when the voltage of V2 is the minimum value, the conductance of the NchTr 34 is minimum and the voltage V0 shows the maximum value, and when the voltage of V2 is the maximum value, the voltage V
0 indicates the minimum value.

Therefore, the threshold value of the inverter 35 is the voltage V
Since it is set between the maximum value and the minimum value of 0, "1" or "" which is the data from the memory Tr1A
0 "can be identified.

The operation of the data identification circuit in the sense amplifier circuit 18 has been described above. Since the circuit constants and the like in the sense amplifier circuit 18 are set at the values at the time of 5V operation, this circuit is used at a low voltage. In doing so, the power supply voltage may become low.

In such a case, the bias voltages V2L to V2H in FIG. 10 become extremely narrow, and even if the memory Tr1A from which data is to be read is turned on, the I _DS current flowing in the memory Tr1A is small, so that 10
The V1 voltage shown in (3) cannot be sufficiently pulled to "L".

As a result, it becomes difficult to identify the data from the memory Tr1A, and the data is read (especially "1").
A read error occurred.

On the other hand, the following method has been conventionally proposed as a remedy for the above-mentioned read failure. That is,
A monitor memory circuit 1C having a memory Tr1A in which a word line is always selected, a selector circuit 1E always selecting a bit line 1D of the monitor memory circuit 1C,
The sense amplifier circuit 1F on the monitor memory circuit 1C side, in which the normal operation range at the power supply voltage is set narrower than the sense amplifier circuit 18 on the user memory circuit side, is provided, and the memory Tr1A of the monitor memory circuit 1C is always selected.
1 "data is read.

Further, the data read from the monitor memory circuit 1C is judged by the expected value judgment circuit 1G for judging whether the expected value is read, and from the result, the sense on the user memory circuit side is detected. Pch for controlling the range from the maximum value to the minimum value of the bias voltage V2 in the data identification circuit shown in FIG.
Pch for controlling the range of the minimum value to the maximum value of the input voltage V0 to Tr31 and NchTr33 and the inverter 35
Tr32 and NchTr34 can be switched between using a transistor having a threshold value set in a 5V system and using a transistor having a threshold value set in a low voltage system.

As a result, when the power supply voltage drops and approaches the normal operation limit on the user memory circuit side, read failure occurs first on the monitor memory circuit 1C side, and data different from the expected value is read. From the expected value determination circuit 1G to the sense amplifier circuit 18, the "L" signal (RE) indicating that the user memory circuit side is approaching the normal operation limit
After the SET is released, and while the data is being read accurately on the monitor memory circuit 1C side, an "H" signal is output) during the period when the data is not being read.

Receiving this signal, the PchTrs 31 and 32 and the NchT of the sense amplifier circuit 18, which is a data identification circuit, are received.
The r33 and 34 are switched to the transistors in which the threshold value or the like is set in the low voltage system, and the width of the bias voltage V2L to V2H is widened.

The inverter 35 is sufficient for the V0 voltage. "
By providing a fluctuation range capable of switching between H ”and“ L ”, it is possible to improve the read operation margin of the user memory circuit when the voltage is low.

[0028]

Since the conventional memory device is constructed as described above, the sense amplifier circuit 18 is provided.
If the voltage (for example, 0-5V) supplied to the device drops to the operating limit (for example, 0-3V) for some reason, the low voltage system is used for the transistor that is judged by "0", "1". By switching to the one with the threshold value set,
Although the reading failure can be remedied, as shown in FIG. 11, the judgment range R1 which is the normal operation width at the power supply voltage is narrowed to R2 and only the judgment point P is shifted by changing the threshold value of the transistor. However, there is a problem in that it cannot be relieved when the above voltage fluctuation is large.

The present invention has been made in order to solve the above problems, and when the power supply voltage drops, the data read margin of the user memory circuit is automatically improved to improve the user memory circuit. An object of the present invention is to obtain a memory device that can prevent read failures.

An object of the present invention is to provide a memory device in which a read failure of a user memory circuit that occurs when the power supply voltage drops can be reliably avoided by boosting the power supply voltage supplied to the sense amplifier circuit.

An object of the present invention is to provide a memory device capable of avoiding a read failure of a user memory circuit that occurs when the power supply voltage drops by lowering the ground voltage supplied to the sense amplifier circuit.

An object of the present invention is to provide a memory device capable of avoiding a read failure of a user memory circuit that occurs when the power supply voltage drops by boosting the voltage supplied to the gate of a transistor of the user memory circuit. To do.

An object of the present invention is to provide a memory device capable of avoiding a read failure of a user memory circuit that occurs when the power supply voltage drops by reducing the voltage supplied to the source of a transistor of the user memory circuit. To do.

[0034]

According to a first aspect of the present invention, there is provided a memory device, comprising: a sense amplifier circuit for reading a program or data stored in a user memory circuit based on an address input; and a normal operating range of a power supply voltage. A monitor memory circuit set to be narrower than the power supply voltage of the user memory circuit, and an expected value determination circuit for determining whether or not the data read from the monitor memory circuit has an expected value, When the decrease of the power supply voltage is detected by the data read from the monitor memory circuit and the expected value judgment circuit detects the data different from the expected value, the operation margin expansion means is caused to read the operation margin of the user memory circuit. Is designed to be extended.

In the memory device according to the second aspect of the present invention, the operation margin expanding means is a booster circuit for automatically raising the power supply voltage supplied to the sense amplifier circuit.

In the memory device according to the third aspect of the present invention, the operation margin expanding means is a step-down circuit that automatically lowers the power supply voltage supplied to the sense amplifier circuit.

According to a fourth aspect of the present invention, in the memory device, the operation margin expanding means is a boosting circuit for automatically increasing the power supply voltage supplied to the gate of each memory transistor of the user memory circuit. .

In the memory device according to the fifth aspect of the present invention, the operation margin expanding means is a step-down circuit that automatically lowers the voltage supplied to the source of each memory transistor of the user memory circuit.

[0039]

In the memory device according to the present invention, the lower limit of the normal operating range of the readable voltage is set higher than that of the user memory circuit side by the sense amplifier circuit of the monitor memory circuit side. At the time of decrease, the sense amplifier detects data different from the expected value, and the expected value determination circuit extends the read operation margin of the user memory circuit to prevent the read failure.

In the memory device according to the invention of claim 2, the power supply voltage supplied to the sense amplifier circuit is raised by the booster circuit when the power supply voltage is lowered, and the read operation margin of the user memory circuit is improved.

In the memory device according to the third aspect of the present invention, when the power supply voltage is lowered, the ground voltage supplied to the sense amplifier is lowered by the step-down circuit to improve the read operation margin of the user memory circuit.

According to another aspect of the present invention, in the memory device, when the power supply voltage drops, the voltage value supplied to the gate of each memory transistor of the user memory circuit is automatically increased and supplied to the selected word line. , By further supplying to the gate of the selected memory transistor and increasing the drain-source current of this memory transistor,
The read operation margin of the user memory circuit is improved.

According to another aspect of the present invention, the memory device automatically lowers the voltage value supplied to the source of each memory transistor when the power supply voltage is reduced, so that the gate-source voltage of the memory transistor is reduced. Raising the drain-source current to improve the read operation margin of the user memory circuit.

[0044]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. Note that, in FIG. 1, the same components as those described with reference to FIG. 8 are designated by the same reference numerals, and duplicate description thereof will be omitted.

In FIG. 1, reference numeral 41 is a booster circuit as an operation margin expanding means, 42 is a power supply line for supplying a power supply voltage Vcc to the sense amplifier circuit 18 or a power supply voltage boosted to 2 Vcc by the booster circuit 41, and 43 is a sense amplifier. This is a switching circuit for making the data read from the sense amplifier circuit 18 equal to the voltage of the peripheral circuit when the power supply voltage supplied to the circuit 18 is different from that of the peripheral circuit.

FIG. 2 shows the details of the booster circuit 41. In FIG. 2, 81, 82, 83, 84 are connected to the input line and the ground line and are turned on by the "L" signal. 85, 86 are capacitors connected between the input line and the ground line, 87,
Reference numeral 88 is a diode, 89 is a NOR circuit which receives the output of the expected value determination circuit 1G and a clock, and 8A is an inverter.

Next, the operation will be described. Now, after the reset of the microcomputer is released, the power supply voltage of the memory device is sufficiently within the normal operating range, and the monitor memory circuit 1C
If "1" data is correctly read from the side sense amplifier circuit 1F, the expected value determination circuit 1G always outputs the "H" signal as described above.

This "H" signal is transmitted through line 1H as shown in FIG.
By inputting to the booster circuit 41 shown in FIG.
Since one input of the OR circuit 89 becomes "H", "L" is output from the NOR circuit 89 regardless of the other clock (CLK) input signal, and SW81 and 82 are ON and SW8.
3, 84 are turned off.

Therefore, the capacitor 85 is charged, the voltage at the point a is at Vcc level, and the voltage at the point b is S.
Since W83 and W84 are OFF, and the capacitor 86 is not charged, it is almost at the GND level.

Therefore, the voltage at the point a (Vcc level) is output from the booster circuit 41 through the diodes 87 and 88 and supplied to the sense amplifier circuit 18 through the power supply line 42, so that it is the same as the peripheral circuit as in the conventional case. ROM data is read at the power supply voltage (Vcc level).

On the other hand, thereafter, when the power supply voltage drops due to some factor (consumption of the battery used for the power supply of the microcomputer, etc.), the sense amplifier circuit 18 on the side of the memory transistor group 16 as the user memory circuit reads. As the lower limit of the normal operating range is approached, as described in the related art, the sense amplifier circuit 1F on the monitor memory circuit 1C side, which has the lower limit of the normal operating range set higher than the user memory side, is set to "1". "A data read failure occurs and a value different from the expected value is read.

As a result, the "L" signal indicating that the expected value determination circuit 1G is approaching the lower limit of the normal operation range on the user memory circuit side is output when the E signal which is the system clock rises (data is read out). It is output to the booster circuit 41 through the line 1H during a period (not closed).

As a result, the 2-input NO in the booster circuit 41
When one input of the R circuit 89 is fixed to "L" and the clock signal which is the other input becomes "L", NOR
“H” is output from the circuit 89.

For this reason, SW81, 82 are OFF, SW
83 and 84 are turned on, whereby the electric charge of the capacitor 85, which has been connected in series to the Vcc input line, is discharged, and a voltage of about 2 × Vcc is output to the point b.

At this time, the voltage at the point b becomes higher than the voltage at the point a, and the voltage at the point b (about 2 × Vcc level) is output from the booster circuit 41. Further, in this state, the capacitor 86 is also charged.

After that, by setting the clock to "H" before the capacitor 85 is completely discharged, the SWs 81 and 82 become O.
The N, SWs 83, 84 are turned off, and then the capacitor 86 is discharged, so that the voltage at the point b is maintained at about 2 × Vcc, and at the same time, the capacitor 85 is charged.

By repeating the above operation with the clock signal, while the "L" signal is being output from the expected value judgment circuit 1G, the power supply voltage of about 2 × Vcc is sensed on the user memory circuit side. It will be supplied to the amplifier circuit 18.

As a result, it is possible to recover the narrowing of the fluctuation range from V2L to V2H of the bias voltage V2 of FIG. 10, which is one of the factors that causes the read failure due to the decrease of the power supply voltage, and the user at low voltage can be recovered. It is possible to improve the read operation margin of the use memory circuit.

That is, in this embodiment, as shown in FIG. 3, the voltage (for example, 0 to 5 V) supplied to the sense amplifier circuit 18 is lowered to its operation limit (for example, 0 to 3 V) for some reason. In this case, even if the judgment range R1 which is the normal operation width in the power supply voltage is narrowed to R2, the judgment point P remains the same and the judgment range is expanded to R3 due to the voltage increase, so that a large voltage fluctuation is read out. Make it possible to avoid defects.

Example 2. FIG. 4 shows another embodiment of the present invention, in which the same components as those shown in FIG. 8 are designated by the same reference numerals, and the duplicate description thereof will be omitted. In the figure, 51 is a step-down circuit as an operation margin expanding means, 52 is a sense amplifier circuit with Vss at the ground voltage GND level, or the step-down circuit 51 has GND-power supply voltage V.
This is a line that supplies the Vss voltage reduced to cc.

Further, 53 is a switch for making the data read from the sense amplifier circuit 18 equal to the voltage of the peripheral circuit when the Vss voltage supplied to the sense amplifier circuit 18 and the Vss voltage of the peripheral circuit are different. Circuit.

Next, FIG. 5 shows an example of the step-down circuit 51.
SWs, 95, 91, 92, 93, 94 connected to the input line and the ground line and turned on by the "L" signal
Capacitors connected between the 96 input line and the ground line, 97 and 98 are diodes, 99 is a NOR circuit that receives the output of the expected value determination circuit 1G and a clock, and 9A is an inverter.

Next, the operation will be described. Now, after the reset of the microcomputer is released, if the power supply voltage of the memory device is sufficiently within the normal operating range and the "1" data is accurately read from the sense amplifier circuit 1F on the monitor memory circuit 1C side, The "H" signal is always output from the expected value determination circuit 1G.

Therefore, the "H" signal is input to the step-down circuit 51 shown in FIG.
Since one input of the input NOR circuit 99 becomes "H", "L" is output from the NOR circuit 99 regardless of the input of the other clock, and SW91 and 92 are ON and SW9.
3, 94 are turned off.

At this time, the capacitor 95 is charged,
Furthermore, the voltage at point b is at GND level, and the voltage at point a is also SW9.
Since 3, 94 are OFF and the capacitor 96 is not charged with electric charges, it is almost at the GND level.

Therefore, the GND level is output from the step-down circuit 51, and the sense amplifier circuit 18 is supplied through the line 52.
To the same Vss voltage (GN) as the peripheral circuit as before.
The data of the memory transistor group 16 is read at the D level).

After that, the power supply voltage is lowered due to some factor (consumption of the battery used for the power supply of the microcomputer, etc.), and the sense amplifier circuit 18 on the user memory circuit side approaches the lower limit of the normal operation range of reading. The lower limit of the normal operation range is set higher than the user memory circuit side, and the sense amplifier circuit 1 on the monitor memory circuit 1C side is set.
At F, a read failure of "1" data occurs, and a value different from the expected value is read.

As a result, the "L" signal indicating that the expected value judgment circuit 1G is approaching the lower limit of the normal operation range on the user memory circuit side is output when the E signal which is the system clock rises (data is read out). It is output during the period (not closed) and is input to the step-down circuit 51 from the line 1H.

As a result, one input of the NOR circuit 99 in the step-down circuit 51 is fixed to "L", and when the clock signal which is the other input becomes "L", the NOR circuit 9
“H” is output from 9.

Therefore, SW91, 92 are OFF, SW9
When 3, 94 are turned on, the capacitor 95 provided in series with the input line is discharged, and GND-V is applied to point a.
A cc level voltage is output.

At this time, the voltage at the point a becomes lower than the voltage at the point b, and the voltage at the point a (GND-Vcc level) is output from the step-down circuit 51. Further, in this state, the capacitor 96 is also charged.

After that, by setting the clock to "H" before the capacitor 95 is completely discharged, the SWs 91 and 92 become O.
The N, SW 93, 94 are turned off, and then the capacitor 96 is discharged, so that the voltage at the point a is GND-Vcc.
The level is maintained, and at the same time, the capacitor 95 is charged.

By repeating the above operation with the clock signal, the Vss voltage is GND-Vcc while the "L" signal is being output from the expected value judgment circuit 1G.
Voltage of the sense amplifier circuit 18 on the user memory circuit side
Will be supplied to.

As a result, by widening the potential difference between the power supply and Vss, the narrowing of the fluctuation range of the bias voltages V2L to V2H in FIG. 10, which is one of the factors that cause the read failure due to the decrease in the power supply voltage, is recovered. Therefore, the read operation margin of the user memory circuit at a low voltage can be improved.

Example 3. FIG. 6 shows another embodiment of the present invention. In this embodiment, the same components as those described in the second embodiment are designated by the same reference numerals, and the duplicated description will be omitted. In FIG. 6, 61
Is a memory transistor group 16 which is a user memory circuit
The Vss voltage at the GND level or the GND-Vc by the step-down circuit 51 is provided on the source side of each memory Tr1A in the
It is a line for supplying the reduced Vss voltage to c.

In this embodiment, since the power supply voltage is lowered, the V1 voltage of the sense amplifier circuit of FIG. 10 is sufficient "
If the read failure occurs on the monitor memory circuit 1C side without being pulled by L ″, the Vss voltage stepped down to the GND-Vcc level by the step-down circuit 51 is output as in the second embodiment. .

Therefore, this Vss voltage is applied to the Vss line 6
1, the source side of each memory Tr1A in the memory transistor group 16 which is the memory circuit for the user (the power supply voltage is within the normal operating range of the sense amplifier circuit, and the monitor memory circuit 1C side reads out the data as expected. If so, the GND level voltage is supplied).

By doing so, the gate-source voltage V of the memory Tr1A, which has been lowered due to the decrease in the power supply voltage,
_GS can be increased and the drain-source current _IDS can be increased, and the V1 voltage of the sense amplifier circuit 18 in FIG. 10 can be sufficiently pulled to "L".

As a result, it becomes possible to improve the read operation margin of the user memory circuit when the voltage is low.

Example 4. FIG. 7 shows still another embodiment of the present invention. In addition, in this embodiment,
The same reference numerals are given to the same components as those described above, and the duplicate description will be omitted. In FIG.
Reference numeral 71 is a line for supplying a voltage of Vcc level or 2 × Vcc level (conventionally Vcc level when the word line is selected) to the word line 19 selected by the address decoder circuit 14.

In this embodiment, when the power supply voltage is lowered, the V1 voltage of the sense amplifier circuit 18 in FIG. 10 is not sufficiently pulled to "L", and a data read failure occurs on the monitor memory circuit 1C side. In the same manner as described above, the booster circuit 41 outputs the voltage boosted to the 2 × Vcc level.

Therefore, this voltage is supplied to the selected word line 19 by the address decoder circuit 14 and the gate side of the memory Tr1A in the selected memory transistor group 16 (the power supply voltage is within the normal operating range of the sense amplifier circuit 18). If the data having the expected value is read on the monitor memory circuit 1C side, the voltage of Vcc level is supplied).

By doing so, it is possible to increase the gate-source voltage V _GS of the memory Tr1A and increase the drain-source current I _DS, which has been lowered due to the decrease of the power supply voltage, and the sense amplifier circuit of FIG. It is possible to pull the V1 voltage of 18 to "L" sufficiently.

This makes it possible to improve the read operation margin of the user memory circuit when the voltage is low.

[0085]

As described above, according to the first aspect of the present invention, the sense amplifier circuit for reading out the program or data stored in the user memory circuit based on the address input, and the normal operating range of the power supply voltage are set as described above. A monitor memory circuit set to be narrower than the power supply voltage of the user memory circuit, an expected value determination circuit for determining whether or not the data read from the monitor memory circuit has an expected value, and the monitor described above. Detecting a decrease in the power supply voltage from the data read from the memory circuit for memory, and when the expected value judgment circuit detects data different from the expected value, the operation margin expanding means extends the read operation margin of the user memory circuit. Since it is configured so as to improve the data read margin of the user memory circuit automatically when the power supply voltage drops, There is an effect of preventing a read failure from occurring in the memory circuit over THE.

According to the second aspect of the present invention, the operation margin expanding means is configured to be a booster circuit that automatically raises the power supply voltage supplied to the sense amplifier circuit. Therefore, when the power supply voltage drops. There is an effect that the read failure of the user memory circuit that occurs in 1) can be surely avoided by boosting the voltage supplied to the sense amplifier circuit.

According to the third aspect of the invention, the operation margin expanding means is configured as a step-down circuit that automatically lowers the ground voltage supplied to the sense amplifier circuit. There is an effect that the read failure of the user memory circuit that occurs in 1) can be avoided by reducing the voltage supplied to the sense amplifier circuit.

According to the invention of claim 4, the operation margin expanding means is constituted by a booster circuit for automatically increasing the voltage supplied to the gate of each memory transistor of the user memory circuit. Read failure of the user memory circuit that occurs when the power supply voltage is reduced can be avoided by boosting the voltage supplied to the gate of the transistor of the user memory circuit.

According to the fifth aspect of the present invention, the operation margin expanding means is configured as a step-down circuit that automatically drops the voltage supplied to the source of each memory transistor of the user memory circuit. The read failure of the user memory circuit that occurs when the power supply voltage drops can be effectively prevented by reducing the voltage supplied to the source of the transistor of the user memory circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a booster circuit in FIG.

FIG. 3 is an explanatory diagram showing a method of expanding an operation margin of data reading according to the present invention.

FIG. 4 is a block diagram showing a memory device according to another embodiment of the present invention.

FIG. 5 is a circuit diagram showing details of the booster circuit in FIG.

FIG. 6 is a block diagram showing a memory device according to another embodiment of the present invention.

FIG. 7 is a block diagram showing a memory device according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional memory device.

9 is a timing chart showing signals in each part of the block in FIG.

FIG. 10 is a circuit diagram showing details of the sense amplifier circuit in FIG.

FIG. 11 is an explanatory diagram showing a conventional data read operation margin.

[Explanation of symbols]

1C monitor memory circuit, 1G expected value judgment circuit, 1
6 memory transistor groups (user memory circuits), 1
8 sense amplifier circuits, 41 step-up circuits (operation margin expansion means), 51 step-down circuits (operation margin expansion means).

Claims (5)

[Claims] 1. A user memory circuit having a plurality of memory transistors arranged in a matrix and storing a program or data to be operated by a microcomputer, and the program or data stored in the user memory circuit. A sense amplifier circuit that reads out based on an address input, a monitor memory circuit in which the normal operating range of the power supply voltage is set narrower than the power supply voltage of the user memory circuit, and data read from the monitor memory circuit is expected. When the expected value determination circuit that determines whether the value is the same as the expected value determination circuit and the data read from the motor memory circuit detects a decrease in the power supply voltage, and the expected value determination circuit detects data different from the expected value And an operation margin extending means for extending the read operation margin of the user memory circuit. Equipped memory device. 2. The memory device according to claim 1, wherein the operation margin expanding means is a booster circuit that automatically raises a power supply voltage supplied to the sense amplifier circuit. 3. The memory device according to claim 1, wherein the operation margin expanding means is a step-down circuit that automatically lowers the ground voltage supplied to the sense amplifier circuit. 4. The operation margin expanding means is a booster circuit for automatically increasing the voltage supplied to the gate of each memory transistor of the user memory circuit. Memory device. 5. The operation margin expanding means is a step-down circuit that automatically drops the voltage supplied to the source of each memory transistor of the user memory circuit. Memory device.