JPH08328891A - Duplex system using standby redundant configuration - Google Patents

Abstract

PURPOSE: To improve the throughput of the system by omitting the selection of the check point data that is performed by a CPU of operating system at a check point, the transfer of the check point data, etc. CONSTITUTION: A CPU 11 receives a store device full generation notification signal 91 and sends a check point instruction signal 92 to a data extension processor 60. The CPU 11 monitors a check point status signal 93 and starts execution of a task after the processing of the device 60 is completed. Then the CPU 11 produces the signal 92, and a data quantity counter of a data monitor device 30 is cleared. Furthermore, the change of the task management information 18 occurred at the CPU 11 is sent to a standby processor 2 from an operating processor 1. Then the device 60 extends the data stored in a data store device 50 into the task internal data stored in a main memory 22 and invalidates the signal 93.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system having a standby redundant configuration of a computer system.

[0002]

2. Description of the Related Art In a redundant system having a standby redundant configuration by loose coupling that does not share memory between an active system processing unit and a standby system processing unit, information necessary for processing takeover at a specific timing (hereinafter referred to as a checkpoint) ( Hereinafter, the checkpoint data will be referred to as "checkpoint data" from the active processing device to the standby processing device. This checkpoint operation ensures that the states of the active system processing device and the standby system processing device are the same, so that when a failure occurs in the active system processing device, the standby system processing device performs the processing of the active system processing device from the checkpoint. It is possible to take over. If a checkpoint operation can be performed when a failure occurs, the standby processing device can take over the processing from the failure occurrence state of the active processing device.

FIG. 23 shows, for example, "Journal of the Institute of Electronics, Information and Communication Engineers Special Issue 3-3-1 Loosely Coupled Multiprocessor" (199).
Nov. 0 Vol. 73) is a block diagram of a conventional redundant system with a standby redundant configuration by the checkpoint system shown in FIG. 73, in which 1 is an active processor in an operating state, 11 is a central processing unit (CP).
U), 12 are main memories, 13 is a system bus, 2 is a standby processing unit in a standby state, 21 is a central processing unit (CPU), 22 is a main memory, and 23 is a system bus. Here, the active processing device 1 in the operating state and the standby processing device 2 in the standby state have the same configuration. Reference numeral 3 is a data transfer means for notifying the checkpoint data from the active processing device 1 to the standby processing device 2. As the data transfer means, there are a method of using a disk that can be shared by the active processing device 1 and the standby processing device 2, a method of performing communication through a line, and the like.

Further, 4a to 4n and 5a to 5n stored in the main memories 12 and 22 are tasks to be run by the CPUs 11 and 21, and tasks 4a and 5a, ..., 4n.
And 5n are the same. 6a to 6n are data indicating the internal state of the task such as variables, flags and register information of the tasks 4a to 4n (hereinafter referred to as task internal data), 7a to 7n are task internal data of the tasks 5a to 5n, 18, 28 Is task management information, and 19 and 29 are checkpoint data lists used for selecting data at checkpoints.

Next, the operation will be described. Here, FIG.
4 is a flow chart showing a checkpoint process (operation) of the active processing device 1, and FIG. 25 is a flow chart showing a checkpoint process (operation) of the standby processing device 2. The CPU 11 of the active processing device 1 executes the task stored in the main memory 12 according to the task management information 18 (ST1
0), when the specified checkpoint is reached (ST
11) Go to ST12. Here, the checkpoint is the timing of executing a checkpoint instruction embedded in a task or the timing of task switching. When proceeding to ST12, the checkpoint data to be notified to the standby processing device 2 at the current checkpoint is selected (ST12).
The checkpoint data is selected based on the checkpoint data list 19 registered in advance. The selected checkpoint data is read from the task internal data 6a to 6n and transmitted to the data transfer means 3 (ST13).

On the other hand, in FIG. 25, the standby system processing device 2 monitors the checkpoint data notification from the active system processing device 1 (ST14), and if there is the notification, it refers to the checkpoint data list 29 and receives the checkpoint data. The data is stored in the corresponding area of the task internal data 7a to 7n (ST15). With the above operation, the consistency of the task internal data 6a to 6n and 7a to 7n at the check points of the active processing device 1 and the standby processing device 2 is maintained.

Further, FIG. 26 shows, for example, Japanese Patent Laid-Open No. 4-3679.
It is a block diagram of the conventional duplication system shown by the 03 gazette. In the figure, 101 is a main processor (operating processor), 102 is a slave processor (standby processor), 112 and 122 are tracking buffers, 11
Reference numeral 3123 is a buffer dividing means, and 114 is a tracking cable.

Next, the operation will be described. FIG. 27 shows FIG.
In the flow chart showing the operation procedure of No. 6, when the main system processor 101 performs tracking of data, the buffer dividing means 113 judges whether the scan cycle of the program for handling the data to be tracked is high speed or low speed. , The amount of data handled by each program is calculated (ST20). The number of blocks in the tracking buffer 112 is calculated from the obtained amount of data and the size of the tracking buffer 112 (ST21). And the de
If you want to track the
Check the tracking method whether only low-speed tracking or both high-speed and low-speed tracking are required (ST2
2) Select high / low speed / mixing division method (ST23)
Then, tracking processing is performed.

[0009]

In the conventional redundant system of the standby redundant configuration by the checkpoint system in FIG. 23, the time required for the checkpoint data selection and the notification processing to the data transfer means becomes an overhead and the system throughput. There was a problem that it decreased. In addition, in a computer system that schedules tasks, it is necessary to transfer task management information to the standby processing device 2, and this transfer is performed by adding the checkpoint data and transferring only when an active system failure occurs. However, in the former case, there is a problem that the checkpoint processing time becomes longer, and in the latter case, there is a problem that the transfer may be impossible depending on the degree of failure.

Further, in the conventional duplexing system disclosed in Japanese Patent Laid-Open No. 4-369903, even if the buffer for equalization is divided, the data to be equalized requires the access program. Depending on, it is a division that secures an area for tracking at high speed or low speed, and the area (address) of the main memory or the like to be tracked is a fixed area, so if you want to equalize only a specific area, or However, there has been a problem that the H / W must be changed in the case where it is desired to change the address to be equivalenced by changing the system.

Further, in the conventional duplexing system disclosed in Japanese Patent Laid-Open No. 4-369903, only the slave system is made to have the same value at the time of writing from the master system. Even if you just want to equalize the data in the memory to restart the system and enter the duplication system, you must write the data to all areas. It was also a cause of unnecessary erroneous output to the outside.

The present invention has been made to solve the above problems, and an object thereof is to improve system throughput by reducing the time required for selecting checkpoint data and the time required for passing checkpoint data. It is what

[0013]

According to a first aspect of the present invention, an active processing unit and a standby processing unit each having a central processing unit and a main memory are provided in parallel, and data necessary for taking over processing when a failure occurs is provided. In a redundant system having a standby redundancy configuration for transferring data from the active processing device to the standby processing device, a monitor bus for inter-system connection and data accessed by the central processing unit in the active processing device to the main memory A data monitor device that captures the data, a data transfer device that transfers the captured data to the standby processing device using the monitor bus, and a data storage device that stores the data transferred from the active processing device, And a data expansion device for writing the data accumulated in the data accumulating device into the main memory of the standby processing device.

In the second invention, the first data storage device for storing the data taken in by the data monitor device is provided in the active processing device, and the data stored in the second data storage device of the standby processing device is expanded. While the device is being developed in the main memory, the data taken in by the data monitor device is stored in the first data storage device of the operating system processing device.

According to the third aspect of the invention, equalization is started by instructing the active processing unit to equalize the contents of the main memory of the active processing unit and the main memory of the standby processing unit with the same value, and the equalization is completed. Then, the standby system processing device notifies the active system processing device of an interrupt.

In the fourth invention, when the central processing unit of the operating system processor accesses the main memory, the accessed data is transferred to the standby system processor and the data is expanded in the standby system main memory. , And equivalence between systems is performed at the same time.

In the fifth aspect, when a failure occurs in the standby system processing device, the standby system status signal is used to notify the active system processing device of the failure of the standby system processing device, and the data of the active system processing device is described above. The transfer to the standby processing device is stopped.

In the sixth invention, a bus occupation time monitoring device for the monitor bus is provided in the active processing device, and when the bus occupation time monitoring device detects that the monitor bus monitoring time has expired, data transfer retry processing is performed and retry is performed. On failure,
When the standby processing device has a failure, the transfer of the data of the active processing device to the standby processing device is stopped.

In the seventh invention, when a failure occurs in the active system processing device, the active system status signal is used to notify the standby system processing device of the failure of the active system processing device. The reception of data from the processing device is cut off, and the data stored in the data storage device of the standby processing device at that time is expanded into the main memory of the standby processing device as normal data.

According to the eighth aspect of the present invention, an active processing unit and a standby processing unit each having a central processing unit and a main memory are provided in parallel, and the data necessary for taking over the processing when a failure occurs is stored in the operating system processing unit. In the redundant system of the standby redundancy configuration in which the main memory is transferred from the main memory to the standby processing device and the two main memories are equalized, an area setting unit that sets an area to be equivalenced between the both main memories, and this area setting unit Operates if the equalized area setting register for registering the set area and the address accessed by the central processing unit to the main memory is the area set in the equalized area setting register, and is necessary for inheriting the address. And an equalizing circuit for transferring various data to the standby processing device.

According to a ninth aspect of the invention, a mode designation signal for setting whether the access type of the central processing unit is to be equalized is a writing time or a reading time, and a writing signal or a reading signal from the central processing unit. In response to this, a mode selection unit is provided for determining whether or not the access type of the central processing unit is the set mode, and if it is the set mode, the equalizing circuit is operated and the standby processing unit is addressed. And the data required for takeover are transferred.

[0022]

According to the first aspect of the invention, the data accessed by the central processing unit to the main memory is monitored by the data monitor of the operating system and transferred to the standby system processing unit by the data transfer unit. The data transferred to the standby system is stored by the data storage device of the standby system. The accumulated data is written and expanded in the standby main memory by the data expansion device.

According to the second aspect of the invention, the first data storage device of the operating system stores the data in the active processing device even if the data cannot be transferred to the standby system while the data is being developed in the standby processing device. , Does not interfere with running task execution.

In the third aspect of the invention, equalization (equalization) is started by an instruction to the active processing unit, and an interrupt is input to the active processing unit upon completion of equalization.

According to the fourth aspect of the invention, when the central processing unit of the active processor accesses the main memory, the accessed data is transferred to the standby processor and the data is expanded in the standby main memory. Thus, the central control unit of the operating system operates so that the data accessed to the main memory is always expanded in the main memory of the standby system.

In the fifth invention, when a failure occurs in the standby system processing device, the failure signal is notified to the active system processing device by the standby system status signal, and the transfer of data from the active system processing device is stopped. .

In the sixth aspect of the present invention, when the bus occupation time monitoring device detects that the monitor bus monitoring time has expired, a retry process for data transfer is performed, and when the retry fails, the data transfer of the active system processing device is stopped.

According to the seventh aspect of the invention, when a failure occurs in the active system processing device, the active system status signal is used to notify the standby system processing device of the failure, and the standby system processing device uses the active system processing device. The reception of the data from the device is cut off, and the data stored in the data storage device of the standby processing device at that time is expanded to the main memory of the standby processing device as normal data.

In the eighth invention, the area to be equalized between the two main memories is registered in the equalize area setting register from the area setting section, and the address accessed by the central processing unit to the main memory is registered in the equalize area setting register. If it is in the specified area, the equalizing circuit operates to transfer the address and data necessary for taking over to the standby processing device.

In the ninth invention, a mode designating signal for setting whether the access type of the central processing unit is to be written or read and the write signal or the read signal from the central processing unit are set as an equivalence target. In response, if a mode is set, a mode selection unit for determining whether the access type of the central processing unit is the set mode is provided.
The equalizer circuit is activated to transfer the address and the data required for takeover to the standby processing device.

[0031]

【Example】

Example 1. The first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a redundant system having a standby redundant configuration according to a first embodiment of the present invention. In FIG. 1, 1 is an active processing device, 2 is a standby processing device,
23, the same reference numerals as those shown in FIG. 23 are the same as or equivalent to those of the conventional one, and therefore detailed description thereof will be omitted. Reference numeral 30 is a data monitor device that monitors and fetches task internal data 6a to 6n written from the CPU 11 to the main memory 12.
Reference numeral 40 is a data transfer device for transferring the fetched data to the standby processing device 2, 50 is a data storage device for storing the data transferred from the active processing device 1, and 60 is a main point of the stored data at the checkpoint timing. Memory 22
A data expansion device for expanding the task internal data 7a to 7n therein, and a monitor bus 70 for transferring data from the active processing device 1 to the standby processing device 2.

Further, reference numeral 91 is a storage device full for monitoring the data storage amount of the standby system data storage device 50 by counting the amount of data taken in by the data monitor device 30 and notifying the operating system CPU 11 if it is full. An occurrence notification signal, 92 is a checkpoint instruction signal for the operating CPU 11 to notify the data decompression device 60 of a checkpoint (timing), and an instruction to start data decompression, and 93 is a checkpoint status indicating the operating state of the data decompression device 60. It is a signal, and is significant during data expansion processing, and insignificant during non-data expansion processing.

Next, the operation will be described. FIG. 2 is a flow chart showing the flow of checkpoint processing (operation) of the operating system processing apparatus 1 according to the first embodiment. CP now
If a change occurs in the task internal data 6a to 6n due to the task execution (ST30) in U11, the data monitor device 30 takes in the changed data and address (ST34), and the data taken in by the data transfer device 40. The address is transferred to the standby processing device 2 using the monitor bus 70 (ST35). Here, the data monitor device 3
0 counts the amount of captured data, and if the amount of captured data, that is, the amount of data transferred to the standby processing device 2 exceeds the capacity of the data storage device 50 (S
T36), the storage device full occurrence notification signal 91 to the CPU 11
Is issued (ST37).

On the other hand, the CPU 11 receiving the storage device full occurrence notification signal 91 (ST31) issues a checkpoint instruction signal 92 to the data expansion processing device 60 (S).
T32). By monitoring the checkpoint status signal 93, the CPU 11 waits for the processing of the data expansion device 60 to be completed (ST33), and starts task execution again. Here, the CPU 11 causes the checkpoint instruction signal 92
Is issued, the data amount counter of the data monitor device 30 is cleared. In ST31,
Similar to the conventional example, ST is executed at the timing of the checkpoint instruction embedded in the task or the timing of the task switch.
Proceed to 32. Furthermore, changes in the task management information 18 stored in the main memory 12 caused by a task switch or the like in the CPU 11 are similarly transferred from the active processing device 1 to the standby processing device 2 in the above flow.

Next, the flow of the checkpoint processing (operation) of the standby system processing device 2 will be described with reference to the flowchart of FIG. The data storage device 50 receives and stores the data and address transferred from the active processing device 1 (ST40).
If there is a notification of the checkpoint instruction signal 92 from (ST41), the checkpoint status signal 93 is made significant, and the process proceeds to ST43 (ST42). When the operation proceeds to ST43, the data decompression device 60 converts the data stored in the data storage device 50 into the task internal data 7 in the main memory 22.
a to 7n are expanded (ST43), and when the expansion of all the stored data is completed, the checkpoint status signal 93 is made insignificant, and the completion of data expansion is notified to the active processing device 1 (ST44). Here, the area where the data is to be expanded is determined by the address added to the data transferred from the active processing device 1.

In this way, in the first embodiment of the present invention, selection of checkpoint data by the CPU 11 at checkpoint (timing) and transfer of checkpoint data (transfer from 40 to 50) are omitted, Internal task data 6 of the active processor 1 and the standby processor 2
A checkpoint process for maintaining consistency between a to 6n and 7a to 7n is realized. Although 30 has been described as a data monitor device for monitoring and fetching the task internal data 6a to 6n written from the CPU 11 to the main memory 12, the CPU 11 accesses the main memory when the standby processing device 2 is restarted ( The data monitor device monitors and takes in the task internal data 6a to 6n read or written.

Example 2. A second embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a configuration diagram showing a redundant system having a standby redundancy configuration according to the second embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. Reference numeral 80 denotes a (first) data storage device having the same function as the (second) data storage device 50 provided in the standby system processing device 2.

Next, the operation will be described. FIG. 5 is a flowchart showing the flow of checkpoint processing (operation) of the active processing device 1 according to the second embodiment. CP now
If a change occurs in the task internal data 6a to 6n due to the task execution (ST50) in U11, the data monitor device 30 takes in the changed data and address, and takes the taken data and address into the data in the own processing device. The data is stored in the storage device 80 (ST53). Here, the data monitor device 30 is counting the amount of data that has been taken in. If the amount of data that has been taken in exceeds the capacity of the data storage device 50 (ST54), the storage device full occurrence notification signal 91 is issued to the CPU 11 ( ST55). The CPU 11 receiving the storage device full occurrence notification signal 91 (ST
51), issue a checkpoint instruction signal 92 to the data expansion processing device 60 (ST52).

Next, the processing of the data transfer device 40 will be described. The data transfer device 40 operates while monitoring the state of the data expansion device 60. When there is data in the data storage device 80 (ST56), the state of the data expansion device 60 is judged by the checkpoint status signal 93 (ST57), and the monitor bus 70 is used only when the checkpoint status signal is insignificant. Then, the data is transferred to the standby processing device 2 (ST58). On the other hand, if the checkpoint status signal is significant, the transfer of data to the standby processing device 2 is interrupted (ST57). In this way, the data transfer device 40 becomes the standby processing device 2
If the checkpoint processing is in progress, the CPU 11 keeps the data stored in the data storage device 80 of the active processing device 1 so that the CPU 11 continues without waiting for the completion of data expansion of the standby processing device 2. Then, the task can be executed.

If the writing performance from the data expansion device 60 of the standby processing device 2 to the task internal data 7a to 7n is inferior to the performance of the data monitoring device 30 of the active processing device 1, the operating data By mounting the capacity of the storage device 80 according to its performance ratio, the operating system data storage device 80 does not become full. Example 2
The checkpoint process of the standby system processing device 2 is the same as that of the first embodiment, and thus detailed description thereof will be omitted.

Example 3. A third embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram showing a redundant system having a standby redundant configuration according to the third embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. Reference numeral 94 is an equalization start signal from the outside to the active processing device 1, and 95 is an equalization completion interrupt signal.

Next, the operation will be described. FIG. 7 is a flow chart showing the flow of automatic equalization processing according to the third embodiment. Since the active processing device 1 is now executing, the task is executed (ST201). When the timing of the automatic equalization is required during the execution of the task, the equalize start signal 94 is set to the high level, the automatic equalize instruction is given, and the DRAM data of the active system is read / written (ST202). The inter-system DMA starts operation, and the above DR
The contents of AM are transferred to the standby system, and the standby system monitors the data and fetches the data (ST203). When the DMA ends, the data equalization is completed (ST204). When the data equalization is completed, the active system is notified. Therefore, the equalization completion interrupt signal 95 is used to interrupt the active system (ST205). In the active system that has received the interrupt, the interrupt process is activated (ST206), and this interrupt process performs post-processing after completion of automatic equalization of the active system. The automatic equalization is a function that makes the contents of the memory of the active system and the contents of the memory of the standby system have the same value and does not require a checkpoint instruction signal.

Example 4. A fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a configuration diagram showing a redundant system having a standby redundant configuration according to the fourth embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted.

Next, the operation will be described. FIG. 9 is a flowchart showing the flow of processing of the fourth embodiment. A task is executed on the active processing device 1 (ST301).
The task accesses the memory of the main memory 12 (ST3
02). The accessed data is sent to the data storage device 80 (ST303). That is, the data sent to the main memory 12 is also transferred to the data storage device 80 at the same time. The data sent to the data storage device 80 is sent to the standby system through the monitor bus 70 (ST304). The standby system receives the transmitted data (ST305). The received data is expanded on the main memory 22 (ST3
06). In this way, the data sent to the main memory 12 is also transferred to the standby system, and at the same time, the main memory 22 of the standby system 22 is transferred.
Expanded on. Therefore, the storage device full occurrence notification signal 91, the checkpoint instruction signal 92, and the checkpoint status signal 93 of the first embodiment are not provided.

Example 5. A fifth embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a configuration diagram showing a redundant system having a standby redundancy configuration according to the fifth embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. Reference numeral 98 is a standby system status signal for notifying the state of the standby system.

Next, the operation will be described. FIG. 11 is the fifth
5 is a flowchart showing a flow of processing according to the embodiment of FIG. The active processing device 1 executes the task (ST60
1). The standby system processing device 2 monitors the data of the active system processing device 1 and fetches the data (ST602). When the standby processing device 2 is operating normally, the standby status signal 98
Is significant (ST603). A failure occurs in the standby processing device 2 (ST604). Standby system due to failure
The task signal 98 becomes insignificant (ST605). Since the standby system status signal 98 becomes ineffective, the active system processing device 1 recognizes the failure of the standby system processing device (ST60).
6). The function of the data monitoring device 30 of the active processing device 1 is stopped due to the failure of the standby processing device 2 (ST607). As a result, the transfer of the data of the active processing device 1 to the standby processing device 2 is stopped.

Example 6. A sixth embodiment of the present invention will be described below with reference to the drawings. FIG. 12 is a configuration diagram showing a redundant system having a standby redundancy configuration according to a sixth embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. Reference numeral 99 is a monitor bus parity generation device, 100 is a monitor bus parity detection device, and 101 is a bus occupation time monitoring device.

Next, the operation will be described. FIG. 13 is the sixth
5 is a flowchart showing a flow of processing according to the embodiment of FIG. The active processing device 1 executes the task (ST70
1). The data monitor device 30 takes in the changed data and address. When the data transfer device 40 transfers the fetched data and address, the monitor bus parity generation device 99 adds parity to the data on the monitor bus 70 (ST702). It is transmitted to the standby processing device 2 (ST703). In the active processing device 1, the bus occupation time monitoring device 101 constantly monitors the bus occupation time of the monitor bus 70 (ST704). When the monitoring time of the monitor bus 70 is over, a retry process of data transfer is performed (ST705), and an output is output due to a retry failure. In the standby processing device 2, the monitor bus parity detection device 100 checks the sent data (ST706). If there is an error, it is output (involuntarily) to the standby system status signal 98 of the monitor bus 70 (ST707). The logical sum of the output of the retry failure of the bus occupation time monitoring device 101 due to the monitoring time of the monitor bus 70 being exceeded and the output (unintentional) of the standby system status signal 98 of the monitor bus 70 is calculated (ST.
708). If there is an output in any of them, it is considered that the standby processing device 2 has failed, and the function of the data monitoring device 30 of the active processing device 1 is stopped (ST709).
As a result, the transfer of the data of the active processing device 1 to the standby processing device 2 is stopped.

Example 7. A seventh embodiment of the present invention will be described below with reference to the drawings. FIG. 14 is a configuration diagram showing a redundant system having a standby redundancy configuration according to the seventh embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. 102 is an operating system status signal for notifying the state of the operating system processing device, 103 is a disconnecting device for disconnecting acceptance of data from the operating system processing device 104, 104 is equalization data accumulated in the data accumulating device 50, Is a data expansion device for expanding data in the main memory 22 of the standby processing device 2.

Next, the operation will be described. FIG. 15 shows the seventh
5 is a flowchart showing a flow of processing according to the embodiment of FIG. The active processing device 1 executes the task (ST80
1). A failure occurs in the active processing device 1 (ST80
2). The failure causes the operating system status signal 102 to become insignificant (ST803). The standby-system processing device 2 recognizes the failure of the active-system processing device 1 because the operating-system status signal becomes ineffective (ST804). Disconnecting device 1
03 disconnects the process of accepting data from the active processing device 1 (ST805). The data expansion device 104 expands the equalized data stored in the data storage device 50 of the standby system processing device 2 to the main memory 22 as normal data (ST806).

Embodiment 8 FIG. An eighth embodiment of the present invention will be described below with reference to the drawings. FIG. 16 is a configuration diagram showing a redundant system having a standby redundancy configuration according to the eighth embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. 300 is a main processor, that is, an active processor, 301 is a slave processor, that is, a standby processor, 302A and 302B are central processing units (CPU), 303A and 303B are main memories, 304A and 304B are equalizer circuits, and 305 is An equalizing bus connecting the active processing device 300 and the standby processing device 301, and 320A and 320B are CPUs 302
A, 302B output address signals, 321A, 32
1B is a data signal.

FIG. 17 is a detailed view of FIG.
A is an address signal transferred between the active processor 300 and the standby processor 301, 305B is a data signal, 30
5C is a control signal. Areas 310A and 310B are area setting units 311-1A to 311-NA and 311-1B to 31.
Reference numeral 1-NB is an equalization area setting register in which the upper limit value of the equalization area set by the area setting units 310A and 310B is registered. 312-1A to 312-NA,
Reference numerals 312-1B to 312-NB denote equalization area setting registers in which the lower limit values of the equalization areas set by the area setting units 310A and 310B are registered. Reference numeral 330 is a region coincidence signal.

FIG. 18 shows an example of setting the equalizing area, and shows a case where the upper limit value and the lower limit value are set to three types. The "equalize" portion is equalized and the active processing unit 30 is shown.
Although 0 and the standby processing device 301 have the same value, the "not equalize" portion is not equalized and remains a different value.

Next, the operation will be described. FIG. 19 shows the eighth
5 is a flowchart showing a flow of processing according to the embodiment of FIG. The upper limit value / lower limit value of each equalization area is set from the area setting unit 310A to the equalization area setting register 311-.
1A to 311-NA and 312-1A to 312-NA are registered (ST900). When the active CPU 302A accesses the active main memory 303A (ST901), each equalize area setting register 311-1A to 311-N.
A, 312-1A to 312-NA check whether or not the address is in the area of the upper limit value to the lower limit value set for each (ST902). Each equalize area setting register 311-1A to 311-NA, 312-1A to 312-
The NA outputs the area coincidence signal 330 to the equalize circuit 304A when the address is in its own area. (No output if outside the area) (ST903). When the equalizing circuit receives the area coincidence signal 330, it takes in the address signal 320A from the CPU 302A and the data signal 321A from the main memory 303A, and outputs it together with the control signal 305C to the equalizing circuit 304B of the standby processing device 301 (ST904). . The equalizing circuit 304B of the standby processing device 301 equalizes the standby main memory 303B with the address signal and the data signal received from the equalizing circuit 304A of the active processing device 300 by the control signal 305C (ST905). In this case, the equalizer circuit 304B notifies the CPU 302B of the main memory 30.
3B or may be expanded directly from the equalizing circuit 304B to the main memory 303B.

Equalize area setting register 311-1A
-311-NA, 312-1A to 312-NA have N pieces, can set an arbitrary space, and when there is a setting error such as overlapping setting, the area setting unit 310A
It is possible to set it as a setting error or not. In the above, the case of writing from the active processing device 300 to the standby processing device 301 has been described, but the same operation is performed when equalizing from the standby processing device 301 to the active processing device 300.

Example 9. A ninth embodiment of the present invention will be described below with reference to the drawings. FIG. 20 is a configuration diagram showing a redundant system having a standby redundant configuration according to a ninth embodiment of the present invention. The same reference numerals as those described above are the same as or equivalent to those described above, and thus detailed description thereof will be omitted. 400
A and 400B are write signals output from the CPUs 302A and 302B, and 401A and 401B are CPU 302.
A read signal output from A, 302B, 410A, 41
0B is a mode designation signal for setting the equalize mode.

Further, FIG. 21 shows the equalizer circuit 3 of FIG.
In a detailed view of a portion of 04A, 420A is a write signal 40.
0A, a read signal 401A, and a mode designation signal 410A are compared, and a mode selection unit 430A that checks whether the access modes from the CPU match, a mode selection unit 420A.
Is an equalize instruction signal for notifying the mode match. The standby system processing device 301 also has these functions and configurations.

Next, the operation will be described. FIG. 22 shows the ninth
5 is a flowchart showing a flow of processing according to the embodiment of FIG. First, the equalizing circuit 304A is designated by the mode designating signal 410A (ST910). CP
C for U302A to access main memory 303A etc.
Write signal 400A or read signal 4 from PU 302A
01A is output (ST911). The mode selection section 420A in the equalizing circuit 304A uses the mode designation signal 410A and the write signal 400A or the read signal 401A.
(ST912). Mode designation signal 41
If 0A matches the write signal 400A or the read signal 401A, the equalize instruction signal 430A is output (ST913). As a result, the address signal 305A, the data signal 305B, and the control signal 305C are transferred from the active system equalizing circuit 304A to the standby system equalizing circuit 304B.
Is sent and the equivalence processing is executed (ST914). In this way, not only the write operation to the main memory of the CPU but also the read operation can be used for the same value, and the restart of the standby processing device can be supported.

[0059]

As described above, according to the first aspect of the present invention, the selection of checkpoint data by the active central processing unit at the checkpoint and the transfer of the checkpoint data are performed by the task execution processing of the central processing unit. Since it is processed in parallel or omitted, the system throughput can be improved.

According to the second invention, even when the data accumulated in the standby processing device is being expanded and the data cannot be transferred to the standby system, the task can be executed in the active processing device, so that the system throughput can be further increased. Can be improved.

According to the third aspect of the invention, the equalization request can be operated from the program and the completion of equalization can be recognized by the program. Equalize in place.

According to the fourth invention, when the central processing unit of the active processing unit accesses the main memory, the accessed data is transferred to the standby processing unit and the data is transferred to the standby main memory. Since the data is expanded, the data accessed by the central controller of the operating system can be expanded in the main memory of the standby system at all times.

According to the fifth aspect of the present invention, when the standby system fails, the transfer of the data of the active system processing device is stopped, so that the influence of the failure in the standby system on the active system can be suppressed. .

According to the sixth aspect of the present invention, when the monitor bus fails, the transfer of the data of the active processing device is stopped, so that the effect on the active system due to the failure on the monitor bus can be suppressed. .

According to the seventh aspect, when the operating system fails, the standby processing device disconnects the data reception from the operating system processing device and blocks the input of the abnormal data from the operating system to prevent the failure. The standby system can be executed as an operating system based on the normal data received in the above, and a highly reliable duplex system can be obtained.

According to the eighth invention, in the same H / W, the area to be equalized between both main memories can be registered and set in the equalize area setting register from the area setting unit, so that it is possible to change the system or to another system. When applying
It is not necessary to redesign / W, and the cost can be reduced. Further, since it is not necessary for the application program accessing the main memory to consider whether or not the respective areas are to be equivalenced, the duplication system does not impose a load on the user.

According to the ninth aspect of the invention, when the data is equivalenced, the read operation from the active system treatment device is also possible, so that the equivalence can be performed without rewriting the main memory. The reliability is improved, and even if only the standby processing device is restarted, it becomes easy to make the equivalency with the active processing device, and the duplex system is easy to maintain.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a redundant system having a standby redundant configuration according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a flow of checkpoint processing of the active processing device according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a flow of checkpoint processing of the standby processing device according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram showing a redundant system having a standby redundant configuration according to a second embodiment of the present invention.

FIG. 5 is a flow chart showing the flow of checkpoint processing of the active processing device according to the second embodiment of the present invention.

FIG. 6 is a configuration diagram showing a redundant system having a standby redundant configuration according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing a flow of automatic equalization processing according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram showing a redundant system having a standby redundant configuration according to a fourth embodiment of the present invention.

FIG. 9 is a flowchart showing the flow of processing according to the fourth embodiment of the present invention.

FIG. 10 is a configuration diagram showing a redundant system having a standby redundant configuration according to a fifth embodiment of the present invention.

FIG. 11 is a flowchart showing the flow of processing according to the fifth embodiment of the present invention.

FIG. 12 is a configuration diagram showing a redundant system having a standby redundant configuration according to a sixth embodiment of the present invention.

FIG. 13 is a flowchart showing the flow of processing according to the sixth embodiment of the present invention.

FIG. 14 is a configuration diagram showing a redundant system having a standby redundant configuration according to a seventh embodiment of the present invention.

FIG. 15 is a flowchart showing a processing flow according to a seventh embodiment of the present invention.

FIG. 16 is a configuration diagram showing a redundant system having a standby redundant configuration according to an eighth embodiment of the present invention.

FIG. 17 is a detailed view of FIG. 16.

FIG. 18 is an example of setting an equalize area according to an eighth embodiment of the present invention.

FIG. 19 is a flowchart showing the flow of processing according to the eighth embodiment of the present invention.

FIG. 20 is a configuration diagram showing a redundant system having a standby redundant configuration according to a ninth embodiment of the present invention.

FIG. 21 is a detailed view of a part of the equalize circuit of FIG. 20.

FIG. 22 is a flow chart showing the flow of processing according to the ninth embodiment of the present invention.

FIG. 23 is a configuration diagram showing a conventional redundant system having a standby redundant configuration.

FIG. 24 is a flowchart showing the flow of checkpoint processing of a conventional operating system processing apparatus.

FIG. 25 is a flowchart showing the flow of checkpoint processing of a conventional standby processing device.

FIG. 26 is a configuration diagram of another conventional duplex system.

FIG. 27 is a flowchart showing the operation procedure of FIG. 26.

[Explanation of symbols]

1 active processor, 2 standby processor 11, 21
Central processing unit, 12,22 Main memory, 18,2
8 task management information, 4a to 4n, 5a to 5n tasks, 6a to 6n, 7a to 7n task internal data, 30
Data monitor device, 40 data transfer device, 50 data storage device, 60 data expansion device, 70 monitor bus, 80 data storage device, 91 storage device full occurrence notification signal, 92 checkpoint instruction signal, 93 checkpoint status signal, 94 equalize Start signal, 95 equalization completion interrupt signal, 98 standby system status signal, 99 monitor bus parity generation device,
100 monitor bus parity detector, 101 bus occupation time monitor, 102 operating status signal, 10
3 separation device, 104 data expansion device, 300
Operating system processor, 301 Standby system processor, 302A,
302B Central processing unit, 303A, 303B main memory, 304A, 304B equalizing circuit, 305
A address signal, 305B data signal, 305C
Control signal, 310A, 310B area setting unit, 311-
1A to 311-NA, 311-1B to 311-NB equalize setting register, 312-1A to 312-NA,
312-1B to 312-NB equalize setting register, 320A, 320B address signal, 321A, 3
21B data signal, 400A, 400B write signal, 401A, 401B read signal, 410A, 410
B mode designation signal, 420A, 420B mode selection section, 430A, 430B equalize instruction signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoshi Nagao 1-2-1, Wadasakicho, Hyogo-ku, Kobe Sanryo Electric Co., Ltd.

Claims (9)

[Claims] 1. An active processor and a standby processor each having a central processing unit and a main memory are provided in parallel,
In a redundant system with a standby redundancy configuration that transfers the data necessary for taking over the processing at the time of a failure from the active processing device to the standby processing device, a monitor bus for intersystem connection and the active processing device A data monitoring device that captures data accessed by the central processing unit to the main memory, a data transfer device that transfers the captured data to the standby processing device using the Morita bus, and a data monitoring device that transfers data from the active processing device. A duplex system having a standby redundancy configuration, comprising: a data storage device for storing data; and a data expansion device for writing the data stored in the data storage device into a main memory of the standby processing device. 2. The operating system processing device is provided with a first data storage device for storing the data taken in by the data monitor device,
While the data expansion device is expanding the data stored in the second data storage device of the standby system processing device into the main memory, the data taken in by the data monitor device is stored in the first data storage device of the active system processing device. The duplex system having a standby redundant configuration according to claim 1, wherein 3. An equalizing process for starting the equalization of the contents of the main memory of the active processing device and the contents of the main memory of the standby processing device to the same value is started by an instruction to the active processing device, and the standby system is completed when the equalization is completed. The duplex system of the standby redundancy configuration according to claim 1 or 2, wherein an interrupt notification is given from the processing device to the operating system processing device. 4. When the central processing unit of the active processing unit accesses the main memory, the accessed data is transferred to the standby processing unit and the data is expanded to the main memory of the standby system, and the data is transferred between the systems. Claim 1 wherein the equalization is performed simultaneously.
Alternatively, the duplex system having the standby redundant configuration according to claim 2. 5. When a failure occurs in the standby system processing device, the standby system status signal notifies the active system processing device of the failure of the standby system processing device, and the standby system processing device of the data of the active system processing device. The redundant system having the standby redundant configuration according to any one of claims 1 to 4, wherein the transfer to the destination is stopped. 6. A bus occupancy time monitoring device for a monitor bus is provided in an active processing device, and when the bus occupancy time monitoring device detects that the monitor bus monitoring time has expired, a retry process for data transfer is performed and a wait is made due to a retry failure. The redundant system of the standby redundant configuration according to any one of claims 1 to 5, wherein the system processing device stops the transfer of the data of the operating system processing device to the standby system processing device as a failure. . 7. When a failure occurs in the active processing device, an active system status signal is used to notify the standby processing device of the failure of the active processing device, and the standby processing device notifies the standby processing device of the failure from the active processing device. Cut off data acceptance,
7. The data stored in the data storage device of the standby system processing device at that time is expanded as normal data in a main memory of the standby system processing device. The redundant system with the standby redundant configuration described in. 8. An active processing unit and a standby processing unit each having a central processing unit and a main memory are provided in parallel,
In a redundant system with a standby redundancy configuration in which data necessary for taking over the processing when a failure occurs is transferred from the active processing device to the standby processing device and the two main memories are equivalenced An area setting unit for setting an area to be equalized, an equalizing area setting register for registering the area set by the area setting unit, and an address at which the central processing unit accesses the main memory are set in the equalizing area setting register. A redundant system having a standby redundant configuration, which operates if it is in a reserved area and is provided with an equalizing circuit for transferring the address and data necessary for taking over to the standby processing device. 9. A mode designation signal for setting whether the access type of the central processing unit is to be equalized is write or read, and a write signal or read signal from the central processing unit to receive the mode designation signal. A mode selection unit is provided to determine whether the access type of the central processing unit is the set mode. If it is the set mode, the equalizer circuit is activated and the standby processing unit needs the address and takeover. 9. A redundant system having a standby redundant configuration according to claim 8, wherein different data is transferred.