JPH0832083B2 - Selective call receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a selective call receiving device that switches and uses a plurality of reception frequencies.

(Prior Art) Conventionally, this type of selective call receiving apparatus is compatible with a signaling system as shown in FIG. 2, for example. In the signaling system shown in FIG. 2, one frame is divided into 15 groups, each group is composed of one sync word and eight selective call words, and the sync word is a frame sync signal common to each group and for group identification. 31-bit BCH (3
1, 16) code, which is composed of codes excluding all 0s and all 1s.

FIG. 3 is a configuration example of a conventional selective call receiving device.
In the figure, the signal received by the antenna 31 and the receiving unit 32 becomes an NRZ signal in the waveform shaping unit 33, and the bit synchronizing unit 34 performs bit synchronization between the internal clock of the clock generating unit 35 and the input signal to perform frame synchronization. The detection unit 36 receives the frame synchronization signal, the group signal detection unit 37 receives the group signal, and then the calling signal detection unit 38 compares and detects with the own calling signal based on the data from the ROM 39 and the control unit 40, and matches. In this case, the speaker 42 is driven through the buffer unit 41 to notify the call. On the other hand, according to the reception state of the frame synchronization signal and the group synchronization signal, the control unit 40 and the battery saving control unit 43 are controlled to intermittently supply power to the reception unit 32 and the channel data in the ROM 39. As a result, the control unit 40 sends data according to the local oscillation frequency to the PLL oscillation unit 44 to control the reception frequency of the reception unit 32. 45 is a battery.

Next, the switching operation of a plurality of channels will be described with reference to FIG. For the signal (a) transmitted from the base station at two frequencies f ₁ and f ₂ , when the selective call receiver receives the frequency f ₁ , for example, as shown in (a), the battery saving At the same time that the
Send ₁ data and try to receive the frame sync signal at f ₁ . When the film synchronization signal can be received, the battery saving is turned off next, and it tries to receive its own group signal. When it can be received, the battery saving is turned on at the self group end.

On the other hand, when the electric field of f ₁ is very weak and f ₂ is strong (b)
Is. Similar to (a), it tries to receive the frame synchronization signal at f ₁ , but if the electric field is weak and cannot be received, for example,
F ₂ data for receiving the f ₂ frequency is sent to the PLL oscillating unit 44 in a period of about two groups, and the same receiving operation as (a) is started at f ₂ . In this way, f ₁ and f ₂ are switched.

(Problems to be Solved by the Invention) In the above-mentioned conventional selective call receiving device, since the reception frequency is switched by detecting the frame synchronization signal, it takes at least one group of time to switch the frequency, and in the above example. , F ₁ is at the limit of receiving the frame synchronization signal, for example, a in FIG.
When there was a point, there was a fault that it received at f ₁ and did not switch to f ₂ .

An object of the present invention is to solve the conventional drawbacks and to provide a selective call receiving device capable of receiving the strongest frequency of an electric field in a short time and not requiring a special signal for electric field detection.

(Means for Solving the Problem) A selective call receiving device of the present invention includes a receiving unit that receives a selective call signal from a base station and outputs the signal as a digital signal, and a change point detection that detects a change point of the digital signal. Section, a counter for counting the changing points of the digital signal, and a count value of the changing points by the counter is compared with a plurality of preset setting values as a parameter of the strength of the electric field of the receiving frequency to receive a plurality of received signals. Of a plurality of comparators for discriminating the strength of the electric field of the reception frequency, and to the receiving unit or the like according to the output of the comparator having the maximum set value among the plurality of comparators whose count value exceeds the set value. A battery saving control unit that controls the power-on time, and a control that controls data for switching a plurality of reception frequencies according to the outputs of the plurality of comparators whose count values exceed a set value A PLL oscillating unit that oscillates a variable frequency based on the data, and a detection unit that detects a frame period and a calling signal when the calling signal is received. Further, when the receiving operation is performed, a plurality of comparator outputs are determined at a plurality of frequencies, and a control unit for controlling the receiving operation at the frequency corresponding to the comparator having the maximum set value is included. Furthermore, when the comparator output is determined at a plurality of frequencies and it is determined that the count values are the same, the control unit controls to perform the reception operation at the frequency at which the reception operation was performed last time.

(Operation) According to the present invention, it is possible to switch a plurality of frequencies by determining the strength of the electric field of a plurality of frequencies using the number of change points of the digital signal as a parameter. The receiving operation becomes possible, and since no special signal code is used for detecting the electric field strength, the air time can be reduced and the system can be simplified.

(Embodiment) An embodiment of the present invention will be described with reference to FIGS. 1, 4, and 8.

FIG. 1 is a block diagram of a bit synchronization unit and an electric field detection unit of the selective call receiving apparatus of the present invention. In the figure, 1
Is an NRZ input, 2, 3 and 5 are control inputs from the control unit, 4 is a primary comparator output, 6 is a secondary comparator output, 7 is a change point detection unit, 8
Is a phase comparison unit, 9 is an integration unit, 10 is a clock generation unit, 11 is a pulse adjustment unit, 12 is a frequency division unit, 13 is a latch, 14 is a counter, 15 is a windowing signal generation unit, and 16 is a primary comparator. Yes, 17
Is a secondary comparator.

FIG. 1 mainly shows a configuration corresponding to the bit synchronizing unit 34 of the conventional example shown in FIG.
Similar to the No. receiving device, it operates as follows.

Change point detection unit 7, phase comparison unit 8, integration unit 9, pulse increase / decrease unit
11, adding clock generation unit 10 to frequency division unit 12
The changing point detecting means including the LL unit A is configured. 13 is a latch, 14 is a counter for counting up / down in hexadecimal, 15 is a window opening signal generator, 16 is a primary comparator, 17 is a secondary comparator, and 2, 3 and 5 are references from the controller 40, respectively. Value input terminals, and 4 and 6 are output terminals to the control unit 40. In the above configuration, the window opening signal generator 15 is for determining the position where the change point should exist and the position where it should not exist when the desired reception signal is input.
The internal timing pulse obtained from the above is input, and it is constituted by a counter, a gate, etc., and is reset by the counter reset signal (d) of FIG.

Next, referring to the timing charts of FIG. 5 and FIG. 6 for the operation, the NRZ signal (Non-Return
POCSAG signal formation (1 word = 62.5ms, to zero signal)
An example in the case of 1batch = 1.0625s) will be described. Fifth
The figure shows N for changes in the NRZ signal input (a) shown in FIG.
The changes of the RZ change point (b), the window opening signal (c), the latch output signal (d), and the latch reset signal (e) are shown. Here, the unit bit length of the NRZ signal (a) is 1.9.
If the detection is performed for 5 ms, or 1/16 of the change point unit bit, the change point is located at 122 μs. When an NRZ signal is input from the input terminal 1 as the output of the waveform shaping section 33 in FIG. 1, the digital PLL section A generates a reproduced clock with bit synchronization. As shown in FIG. 5 (c), the output of the window opening signal generator 15 is such that the ratio of "H" and "L" is selected to be, for example, 6:10, and the NRZ is almost at the center of the "H" portion. It is designed to detect the change point of the signal. The detection output of the change point of the NRZ signal is sent to the counter 14 and latched.
Latch 13 is also sent to 13, and when there are multiple NRZ transition points in each of the "H" and "L" sections, the second and subsequent ones are ignored, and the latch 13 is latched by the windowing signal generator 15 output. The latch 13 is reset by issuing a reset signal (e). Next, the counter 14 outputs the window opening signal (c) to the output of the latch 13 according to the output of the window opening signal generator 15.
When is "H", it counts up, and when it is "L", it counts down. The counter 14 maintains O when the output is O and down-counting, and maintains F when F (= 16) and up-counting. The output of the counter 14 is input to the primary comparator 16 and the secondary comparator 17, respectively, is compared with the reference value set by the input terminals 3 and 5, and is output to the control unit 40 when the counter output exceeds the reference value. Then, the power supply from the battery 45 to the receiving unit 32 and the like is controlled via the battery saving control unit 43 in different modes. The reference values may be set to 3 and 7 for the primary and secondary comparators 16 and 17, respectively. FIG. 6 shows how the battery is saved with respect to the output of the counter 14. In the figure, the primary comparator 16 compares at the timing (62.5 ms) of the primary determination clock (e). Since noise is randomly generated when there is no signal, the values of the up counters cancel each other and never exceed 3. Therefore, the output 4 of the primary comparator 16 is intermittently received at "L". ) Mode 1 shown in FIG. On the other hand, when the call signal is received, the output of the primary comparator 16 becomes "H", and at this time, the power supply of the receiving unit 32 and the like continues to be on for 62.5 ms more than in the case of the mode 1 (FIG. 6). The mode 2 shown in b) is entered. next,
Based on the timing of the secondary determination input 5 in FIG. 6 (f), the secondary comparator 17 determines whether the value of the counter 14 is 7 or more. When the output is "L", the mode 1 is selected, and when the output is "H" In case of ", it is assumed that the reception is completely performed, and the mode is changed to the mode 3 shown in FIG. 6 (c), and the power supply of the receiving unit is turned on for about 2 seconds,
The next step of frame sync signal matching is entered.

According to the above configuration, as shown in FIG. 7, even if the battery is saved in the mode 1 when there is no signal shown in (c) due to fading or the like during transmission of the call signal (a) from the base station, the conventional example is used. As shown in (b), the pre-ampoule detection is performed by pattern matching, while the position of the change point of the received ringing signal, that is, the establishment of the bit period also serves as the pre-ampoule detection. It becomes possible to detect. Further, in the past, bit synchronization was performed and then preamplifier pattern matching was performed, but with the above configuration, bit synchronization can also serve as preamplifier matching, and therefore power supply until synchronization is established. It has the advantage of saving supply.

Others are the same as those in FIG. 3, but the operation of the control unit 40 changes in accordance with the operation in FIG. 1, so that part will be mainly described. The operation shown in FIG. 1 can be applied to any signal speed by changing only the basic clock, and therefore the description thereof will be omitted.

For example, when the value of the primary comparator 16 is 3 and the value of the secondary comparator 17 is 7, (value of primary comparator <value of secondary comparator)
The operation shown in FIG. 4C can be performed. That is, if the previously received frequency f ₁ data is sent to the PLL oscillation unit 44 and received, and both the primary comparator 16 and the secondary comparator 17 are NG, that is, “L”, then the data of the f ₂ frequency is next. PLL oscillator 4
Send and receive to 4, similarly primary comparator 16 or secondary comparator 1
If 7 is OK, that is, "H", the process goes to the frame sync signal detection as it is. In this case, to determine the result of the comparator,
Since the BCH code is used as a signal system, it is sufficient if it is about 1 to 2 words. 2 of reception frequency f ₁ and f ₂
The general operation in the case of frequency is shown in FIG.

As shown in the flow chart of FIG. 8, when the previously received frequency is f ₁ , the PLL oscillator 44 shown in FIG. 3 and FIG.
The control unit 40 sets f ₁ data to and the reception at f ₁ is performed. First, the result of the secondary comparator 17 is judged, and if OK, f ₁
It is determined that the electric field of is strong and the receiving operation at f ₁ is performed. When the result of the secondary comparator 17 is NG, the result of the primary comparator 16 is judged, a flag is set when it is OK, and when it is NG, it is left as it is.
Set f ₂ data in the PLL oscillator 44. When f ₂ is received and the result of the secondary comparator 17 is judged in the same manner, if it is OK, it is f _{2 as it is.}
Enter the receiving operation with. If the flag is NG, the flag is checked. If the flag is set, the f ₁ data is sent to the PLL oscillator 44, and the reception operation is started at the f ₁ . If the flag has been set, to determine the result remains the primary comparator 16 f _2, If OK in f ₂ enters the receiving operation. If the result of the primary comparator 16 is also NG, it is reset to f ₁ which was used for the reception operation last time, and the reception operation is started at f ₁ . By performing the above operation, the receiving operation can always be started at the frequency with the strongest electric field.

According to the present embodiment, an example in which two comparators are used and two reception frequencies are switched has been shown, but a plurality of comparators can be used to switch a plurality of frequencies in a similar method.

(Effect of the Invention) According to the present invention, a plurality of frequencies can be switched by determining the strength of an electric field of a plurality of frequencies using the number of change points of a digital signal as a parameter. It becomes possible to receive at
In addition, because no special signal code is used to detect the electric field strength, air time can be reduced and the system can be simplified. Furthermore, the receiving frequency can be switched by monitoring only bit synchronization. Therefore, the detection time can be shortened as compared with the conventional one, and the practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram of a bit synchronization unit and an electric field detection unit of a selective call receiver according to an embodiment of the present invention, FIG. 2 is a conventional signaling system diagram, and FIG. 3 is a block diagram of a conventional selective call receiver. , FIG. 4 is a receiving operation diagram of the present invention showing a signal sequence similar to that of FIG. 1, and FIG. 5 is an NRZ signal 1 of the apparatus of FIG.
Timing charts for explaining the operation between bits, FIGS. 6 and 7 are timing charts when the battery saving operation of the apparatus is performed, FIG. 8 is a reception flowchart of the present invention, and FIG. 9 is a plurality of frequencies. FIG. 3 is a schematic diagram of a service area of a selective call receiving device that simultaneously calls in the. 1 ... NRZ input, 2,3,5 ... control input from control unit, 4 ...
… Primary comparator output, 6 …… Secondary comparator output, 7 …… Change point detector, 8 …… Phase comparator, 9 …… Integrator, 10 …… Clock generator, 11 …… Pulse adjuster, 12 ... divider, 13
...... Latch, 14 …… Counter, 15 …… Window opening signal generator, 16 …… Primary comparator, 17 …… Secondary comparator.

Claims (3)

[Claims] 1. A receiving unit for receiving a selective calling signal from a base station and outputting it as a digital signal, a changing point detecting unit for detecting a changing point of the digital signal, and a counter for counting changing points of the digital signal. And comparing the count value of the change points by this counter with a plurality of preset values as a parameter of the electric field strength of the reception frequency to determine the strength of the electric field of the plurality of reception frequencies to be received. And a battery saving control unit that controls the power-on time to the receiving unit or the like according to the output of the comparator having the maximum setting value among the plurality of comparators whose count value exceeds the setting value, A control unit that controls data for switching a plurality of reception frequencies according to outputs of the plurality of comparators whose count values exceed a set value, and a P that oscillates a variable frequency by the data. A selective call receiving device comprising: an LL oscillating unit; and a detecting unit for detecting a frame period and a calling signal when the calling signal is received. 2. A control unit for judging a plurality of comparator outputs at a plurality of frequencies when performing a receiving operation and controlling so as to perform the receiving operation at a frequency corresponding to a comparator having a maximum set value. The selective call receiving device according to item (1). 3. A control unit for controlling to perform a receiving operation at the frequency at which the previous receiving operation was performed, when the comparator output is determined at a plurality of frequencies and it is determined that the count values are the same. ) The selective call receiving device described.