JPH0831981B2 - Image information reduction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] An image information reducing apparatus, particularly an apparatus for reducing image information of a television image or the like in a horizontal direction or a vertical direction, in which a line memory for temporarily storing the image information is provided with a low-pass filter or an image. Without providing it individually in the reduction circuit,
The noise is removed from the reduced image information D1 based on the image information D2 delayed by at least one display line in order to reduce the number of line memories occupied in one chip by sharing the noise. A signal removal calculation means 11 for outputting the image output information D3 from which
A delay means 12 for thinning out a display line in the vertical direction of the display screen from the image output information D3 of the signal removal calculating means 11 according to a predetermined thinning rate, and delaying one display line before the display line remaining by the thinning, The image information of the display line remaining by the thinning of the delay unit 12 is multiplied by the first correction coefficient, and the image information of the display line before the display line left by the thinning of the delay unit 12 is multiplied by the second correction coefficient. And reducing operation means 13 for obtaining reduced image information D4 by adding the image information multiplied by the first correction coefficient and the image information multiplied by the second correction coefficient. Configure.

[Industrial applications]

The present invention relates to an image information reducing device, and more specifically, to a device for reducing image information such as a television image in a horizontal direction or a vertical direction.

2. Description of the Related Art In recent years, a semiconductor integrated circuit device used for reducing and transmitting a television image in a video conference system has been developed.

According to this, there is a demand for an apparatus capable of reducing the number of line memories installed by sharing a part of a low-pass filter that removes aliasing noise generated during image reduction processing and a part of an image reduction circuit. .

[Conventional technology]

 8 and 9 are explanatory views according to a conventional example.

FIG. 8 shows a block diagram of a conventional image information reducing apparatus.

In the figure, an image information reducing device is a digital low-pass filter 1 for removing a high band component of a digital image information input Din, an image reducing circuit 2 for reducing a digital image information input Din, and writing / reading of reduced image information. It comprises a writing / reading control circuit 3 and an image memory 4 for storing reduced image information.

The function is, for example, when a television image or the like is reduced in the vertical direction, first, unnecessary lines are thinned out in the digital image information input Din at a given reduction ratio, and folding noise generated at that time is reduced by the digital low-pass filter 1. The digital image information line that has been removed through the above process is then subjected to reduction calculation for each pixel, and the calculation result of the one line is written in the image memory 4, and after the completion of one line, the reduced image information reduction is performed. The output Dout is read from the image memory 4.

[Problems to be Solved by the Invention]

9 (a) and 9 (b) are diagrams for explaining the problems associated with the conventional image information reducing device. FIG. 9 (a) is a digital low-pass filter 1 and image reducing circuit 2 shown in FIG.
The circuit configuration of FIG.

In FIG. 1A, the digital low pass filter 1
Is a recursive filter such as an IIR (Infinite Inpulse Response) filter and includes an adder 1a, a multiplier 1b, an adder 1c and a line memory 1d. The line memory 1d has a function of temporarily storing the high band component when removing the high band component from the extracted one line of digital image information. Further, the line memory 1d is composed of registers of the number obtained by dividing one line into one pixel unit.

The image reduction circuit 2 is composed of an adder 2a, a multiplier 2b, an adder 2c and a line memory 2d. Line memory 2d
Has a function of temporarily storing the extracted one-line digital image information and the adjacent-line digital image information when the reduction operation is performed. Also, line memory 2d
Is the line memory 1d of the digital low-pass filter 1.
In the same manner as the above, the number of registers is such that one line is divided into one pixel unit.

FIG. 3B is a diagram illustrating a television image displayed on the monitor 5.

In the figure, 6 is a horizontal scanning line, which is one of the TV images.
The case where the line is divided into, for example, 1000 pixels is shown. As a result, in order to remove the high band component for one line of the television image, the digital low pass filter 1
The line memory 1d requires 1000 registers. Generally, a multi-bit memory (register) is required for one pixel for luminance and color information of a television, and 1000 registers are required to configure the line memory 2d of the reduction circuit 2 for image reduction.

Therefore, when the image information reducing device is made into an LSI by using the circuit configuration as shown in FIG. 9 (a), the register of the line memory 1d of the digital low-pass filter 1 and the register of the line memory 2d of the reducing circuit 2 are 2000 in total. You need one. As a result, the line memories 1d and 2d occupy a large chip area, which makes it difficult to integrate the semiconductors.

The present invention was created in view of the problems of the related art, and a line memory for temporarily storing image information is not separately provided in a low-pass filter or a reduction circuit,
An object of the present invention is to provide an image information reducing device which can share the same and reduce the number of line memories occupied in one chip.

[Means for solving the problem]

FIG. 1 shows a principle diagram relating to the image information reducing apparatus of the present invention.

The apparatus removes noise from the reduced image information D1 based on at least one display line delayed image information D2,
The signal removal calculation means 11 for outputting the image output information D3 from which the noise is removed, and the display line in the vertical direction of the display screen is thinned from the image output information D3 of the signal removal calculation means 11 according to a predetermined thinning rate, and by the thinning By a delay means 12 for delaying the display line before the remaining display line by one line, a first correction coefficient is calculated for the image information of the display line remaining by thinning out the delay means 12, and by thinning out the delay means 12. The image information of the display line before the remaining display line is multiplied by the second correction coefficient, and the image information obtained by multiplying the first correction coefficient and the image information obtained by calculating the second correction coefficient are added. Reduction calculation means 13 for obtaining reduced image information D4
The above-mentioned object is achieved.

[Operation] The operation of the layer information reducing apparatus of the present invention will be described. First,
The signal removal calculation means 11 to which the reduced image information D1 and the delay information D2 obtained by delaying the image information by one display line are input,
Noise is removed from the reduced image information D1 based on D2. Then, the signal removal calculation means 11 outputs the image information D3 obtained by removing noise from the reduced image information D1 to the delay means 12 and the reduction calculation means 13.

The delay means 12 that has input the image information from which noise has been removed is
The display lines in the vertical direction of the display screen are thinned out from the image output information of the signal removal calculation means 11 according to a predetermined thinning rate, and the display line before the display line remaining by this thinning is set to 1
Delay line.

Then, the reduction calculation means 13 multiplies the image information of the display lines remaining by the thinning-out of the delay means 12 by the first correction coefficient. Further, the reduction calculation means 13 multiplies the image information of the display line before the display line left by the thinning-out of the delay means 12 by the second correction coefficient. After that, the reduction calculation means 13
The reduced image information is obtained by adding the image information multiplied by the first correction coefficient and the image information multiplied by the second correction coefficient.

As described above, according to the image information reducing apparatus of the present invention, the reduced image information D1 from which noise is removed and the delay information D2 obtained by delaying the reduced image information D1 are multiplied by a predetermined correction coefficient, and these correction coefficients Since the reduced image information is obtained by adding the image information multiplied by, even if the thinning rate changes within one screen, the brightness per pixel after the screen reduction can be optimized. It is possible to output the reduced image information necessary for not only reducing the screen by a fraction of an integer but also reducing the screen by a fraction of a positive number including a decimal point in the denominator.

The signal removal calculation means 11 and the reduction calculation means 13 can use the delay means 12 at the same time. Therefore, the signal removal calculation means 11 can use the delay information D2 from the delay means 12 to remove noise from the reduced image information D1.
The reduction calculation means 13 is the image information from the signal removal calculation means 11.
The reduced image information D4 can be obtained by calculating D3 and the delay information D2 from the delay means 12 with a predetermined reduction coefficient.

As a result, it is possible to reduce the number of line memories (delay means) for temporarily storing image information to half that of the conventional one.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

2 to 7 are diagrams for explaining the image information reducing apparatus according to the embodiment of the present invention, and FIG. 2 is a block diagram of the image information reducing apparatus according to the embodiment of FIG. 1 of the present invention. ing.

In the figure, reference numeral 21 surrounded by a one-dot chain line is signal removal calculation means.
11, a digital low-pass filter which is an embodiment of the delay means 12, and includes a digital image information input Din and delay data D
Input 21 and to input image data D31
Has the function of outputting.

The digital low pass filter 21 includes multipliers 21a, 21c,
An IIR filter including an adder 21b and a line memory 25 is configured. The multiplier 21a receives the digital image information input Din, multiplies the parameter X, and outputs the weighted operation image data D11. The adder 21b inputs the operation image data D11 and adds it with the operation delay data D22. The multiplier 21c inputs the delay data D21, multiplies the parameter (1-X), and outputs the weighted calculation delay data D22.

The line memory 25 is one of the digital image information input Din.
The pixel data for lines is temporarily stored, and the image (DIN) 31 from which the high band component (folding noise or the like) is removed is input and the delay data D21 is output. For example, when one line is divided into 1000 pixels, it is composed of 1000 registers.

Reference numeral 22 surrounded by a broken line is an image reduction circuit which is an embodiment of the delay means 12 and the output calculation means 13, and inputs the image data D31 from which the high band component is removed and the delay data D21 to obtain the reduced image data D33. Has the function of reducing.

The image reduction circuit 22 includes multipliers 22a and 22c, an adder 22b and a line memory 25. The multiplier 22a inputs the image data D31 from which the high band component has been removed, multiplies it by the parameter Z, and outputs the weighted operation image data D32. The multiplier 22c receives the delay data D21, multiplies it by the parameter (1-Z), and weights the calculated delay data.
It outputs D23. The adder 22b adds the operation image data D32 and the operation delay data D23 and outputs reduced image data D33. The line memory 25
Is shared by the digital low-pass filter 21 and the image reduction circuit 22.

An image memory 23 is for temporarily storing the reduced image data D33.

Reference numeral 24 is a write / read control circuit, which reduces the reduced image data D3.
3 is written to the image memory 24 or the image memory 2
The read control of the image information output Dout reduced from 4 to the outside is performed.

FIG. 3 shows a multiplier arithmetic circuit for outputting the correction coefficients Z and 1-Z to the multiplier 22a according to the first embodiment of the present invention.

In the figure, the multiplier arithmetic circuit is composed of adders 201, 203 registers 202, 204 and comparison detector 205, and has a function of outputting parameters Z, 1-Z and coincidence detection data D4 when reduction ratio data is input. For example, when 1 / 3.2 is set as the reduction rate data, that is, `` 3.
2 ”, when the adder 203 is set to“ 1 ”, the comparison detector 20
Every time 5 outputs the match detection data D4, the register 202 reads `` 3.
2 ”is cumulatively added, and using the decimal part of the output of the register 202, the parameters Z = 0.2, 0.4, 0.6 ... Or 1-Z =
0.8,0.6,0.4,0.1 ... can be output. In addition,
The coincidence detection data D4 is output to the write / read control circuit 24, and the data D4 is the reduced image data D33 in the image memory 25.
Becomes the control data for writing. Reduced image data D3
3 is written in the image memory 25 each time the output R1 of the register 202 and the output R2 of the register 204 match.

With these, the image information reducing apparatus according to the first embodiment of the present invention is configured.

 Next, the operation of the device of the present invention will be described.

FIG. 4 is an explanatory diagram relating to the image information reducing method according to the first embodiment of the present invention. Input image information and output image when vertically reducing image information such as a television image to 1 / 3.2 The figure which shows information and is shown.

In the figure, DA is input image information, which is data such as a television image before being reduced, for example, a line number of a horizontal scanning line.
(Input line No.) 0 to 525 are divided into pixels for each line. DB is output image information, and a line N of a new horizontal scanning line when the input image information DA is thinned out by the image information reducing apparatus of the present invention and reduced to 1 / 3.2 in the vertical direction.
o (output line No.) 1 to n are divided into pixels for each line. In the output image information DB, the reduced image data of the output line No. 0 becomes the input line No. 0 × 1, and the input line No. 0 of the input image information DA is written in the image memory 23 as it is.

The next output lines are input line No. 3 and input line No. 4.
Is extracted, and these are taken as A and B, they can be obtained by multiplying them by the parameters Z = 0.8,1-Z = 1-0.8 = 0.2 and adding the multiplied input lines A and B, respectively.
The reduced image data of the output line No. 1 is written in the image memory 23.

Therefore, the output image information of the output line Non is (line A) × (1-Z) + (line B) × Z. However, Z
Is the fractional part of K, and K is the value obtained by adding the output line No. n to the denominator 3.2 of the reduction ratio 1 / 3.2. This relationship is shown in Table 1.
Is shown in.

FIG. 5 is an operation time chart of the image reduction circuit according to the first embodiment of the present invention.

In the figure, A and B are input lines, and the image reduction circuit 2
It is the reduced image information input to 2. R1 is register 202
And the K value output from the register 202 of the multiplication operation circuit. R2 is the output of the register 204, and the input line A output from the register 204 of the same circuit
Is the count information. D4 is coincidence detection data, which is a write control signal for outputting output image information. Z, 1-Z
Is a parameter, which is obtained by calculating the decimal part of the register 202. No. 0 to No. n are output image information, which are reduced image data to be written in the image memory 23.

It should be noted that when writing of the reduced image data for one screen to the image memory 23 is completed, the image is read out and input to a monitor or the like, whereby an image reduced to 1 / 3.2 in the vertical direction can be displayed. .

FIG. 6 is a comparative explanatory diagram of the image information reducing apparatus according to the first embodiment of the present invention and a conventional example. FIG. 6A shows line memories 1d and 2d according to the conventional example with a low-pass filter and an image reducing device. The block diagram used for a circuit is shown.

In the figure, when the transfer function is calculated by Z conversion when the input a, the parameter of the multiplier 1b are 1-j, the parameter of the multiplier 2b is 1-k, the input of the line memory 1d is b, and the output is c. It looks like this:

That is, the transfer function indicating the input / output of the low-pass filter is Becomes

Substituting this into the transfer function of the image reduction circuit and rearranging the input a and output c, Becomes

FIG. 2B shows a configuration diagram in which the line memory 25 according to the first embodiment of the present invention is shared by a low pass filter and an image reduction circuit.

In the figure, input a, the parameter of the multiplier 21a is j, the parameter of the multiplier 21c is 1-j, the parameter of the multiplier 22a is k,
The transfer function in the case where the parameter of the multiplier 22c is 1-k, the input part of the line memory 25 is b, and the output is c is similarly obtained as follows.

That is, the output of the line memory 25 is bZ ^-1H .
However, Z ^-1H is a symbol indicating a delay of one line.

The input b of the line memory 25 is And the output c is Becomes

Here, comparing equations (1) and (2), equation (1) yields
Equation (2) only includes the term Z ^-1H . This Z ^-1H
Is an operator indicating a delay of one line. Therefore, even if the line memories 1d and 2d of the conventional example are shared like the line memory 25 of the embodiment of the present invention, it is clear that the transfer function does not change.

In this way, according to the first embodiment of the present invention, the line memory 25 is provided between the adder 21b and the multiplier 22c, and the delay data D21 from the line memory 25 is transferred to the multiplier 21c. Via adder 21b via multiplier 22c via adder 2
It is output to 2b.

Therefore, the digital low-pass filter 21 receiving the digital image information input Din inputs the delay data output function when removing the aliasing noise by the delay data D21 from the line memory 25, and the image data D31 from which the high band component is removed. As a delay data output function when the image reduction circuit 22 outputs the reduced image data D33 by the delay data D21 from the line memory 25, a digital low pass filter is provided.
21 and the image reduction circuit 22 can share the line memory 25.

As a result, the input image information DA of 1 line is compared to the conventional one.
It is possible to reduce the number of line memories 25 for temporarily storing the number of lines to half.

FIG. 7 shows a block diagram relating to the image information reducing apparatus of the second embodiment of the present invention.

In the figure, the difference from the first embodiment is that in the second embodiment, the signal removal calculation means of the digital low-pass filter 31 is composed of adders 31a, 31c and multiplier 31b, and the reduction calculation means of the image reduction circuit 32 is Adders 32a and 32c and multiplier 32b
It is composed of

As a result, the line memory 33 is used as in the first embodiment.
Can be shared by the digital low-pass filter 31 and the image reduction circuit 32. Further, compared to the first embodiment, the second embodiment has two multipliers 31b and 32b, so that the circuit configuration can be simplified.

〔The invention's effect〕

As described above, according to the image information reducing apparatus of the present invention, the reduced image information from which noise is removed or the image information obtained by delaying this reduced image information is multiplied by a predetermined correction coefficient, and these correction coefficients are calculated. Since the reduction calculation means for adding the multiplied image information is provided, even if the thinning rate changes within one screen, the brightness per pixel after the screen reduction can be optimized, and the integral part Not only the screen reduction of 1, but also the reduced image information of a positive fraction including a decimal point in the denominator can be output.
Therefore, the range in which the screen can be reduced becomes wider.

This greatly contributes to the manufacture of a semiconductor integrated circuit device in which the image information reducing device is made compact.

[Brief description of drawings]

FIG. 1 is a principle diagram of the image information reducing apparatus of the present invention, FIG. 2 is a configuration diagram of the image information reducing apparatus of the first embodiment of the present invention, and FIG. 3 is a first diagram of the present invention. FIG. 4 is a configuration diagram of a multiplier arithmetic circuit that outputs a correction coefficient to a multiplier according to the embodiment, FIG. 4 is an explanatory diagram related to an image information reducing method according to the first embodiment of the present invention, and FIG. An operation time chart of the image reduction circuit according to the first embodiment, FIGS. 6 (a) and 6 (b) are comparative explanatory diagrams of the image information reduction device according to the first embodiment of the present invention and a conventional example, FIG. 7 is a block diagram of an image information reducing apparatus according to a second embodiment of the present invention, FIG. 8 is a block diagram of an image information reducing apparatus of a conventional example, and FIGS. 9 (a) and 9 (b). [FIG. 8] is a diagram for explaining a problem with a conventional image information reducing device. (Explanation of symbols) 11 ... Signal removal calculation means, 12 ... delay means, 13 ... reduction calculation means, D1 ... reduced image information, D2 ... delay information, D3
...... Image information with high band components removed, D4 ...... Reduced image information.

Claims (1)

[Claims] 1. A signal removal calculation means for removing noise from image information to be reduced based on image information delayed by at least one display line, and outputting the image information from which the noise is removed, and the signal according to a predetermined thinning rate. The vertical display line of the display screen is thinned from the image output information of the removal calculation means,
The display line before the display line left by the thinning is 1
A delay unit that delays the line; a first correction coefficient is calculated for the image information of the display line remaining by the thinning of the delay unit; and the image information of the display line before the display line remaining by the thinning of the delay unit is used. A reduction calculation unit that multiplies a second correction coefficient and adds image information obtained by multiplying the first correction coefficient and image information obtained by calculating the second correction coefficient to obtain reduced image information is provided. An image information reducing device characterized by the above.