JPH08316466A - MOS semiconductor device and manufacturing method thereof - Google Patents
MOS semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH08316466A JPH08316466A JP7120995A JP12099595A JPH08316466A JP H08316466 A JPH08316466 A JP H08316466A JP 7120995 A JP7120995 A JP 7120995A JP 12099595 A JP12099595 A JP 12099595A JP H08316466 A JPH08316466 A JP H08316466A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- sidewall
- insulating film
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 13
- 238000005121 nitriding Methods 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 claims abstract description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 12
- 230000003647 oxidation Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 15
- 239000012535 impurity Substances 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
Landscapes
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【目的】 ＭＯＳ型半導体装置の製造方法に関し、ゲー
ト絶縁膜の絶縁破壊、ホットキャリアによる劣化耐性を
向上する手段を提供する。
【構成】 ゲート絶縁膜３の上にゲート電極４を形成
し、このゲート電極４の直下の一部およびサイドウォー
ル８を形成する領域の少なくとも一部にシリコン窒化膜
またはシリコン窒化酸化膜６，７を形成し、ゲート電極
４の側壁からシリコン窒化膜またはシリコン窒化酸化膜
７の上にかけてサイドウォール８を形成する。ゲート絶
縁膜の上にゲート電極を形成し、このゲート電極の側壁
からゲート絶縁膜の上にかけてサイドウォールを形成
し、これをアンモニアガス等による窒化と酸素等による
酸化またはＮ2 Ｏによる等の窒化酸化物系のガスによる
窒化酸化を行って、ゲート電極の直下の一部およびサイ
ドウォールの直下の少なくとも一部にシリコン窒化膜ま
たはシリコン窒化酸化膜を形成する。
(57) [Summary] [PROBLEMS] To provide a method for improving a dielectric breakdown of a gate insulating film and resistance to deterioration due to hot carriers in a method for manufacturing a MOS type semiconductor device. A gate electrode 4 is formed on a gate insulating film 3, and a silicon nitride film or a silicon oxynitride film 6, 7 is formed on a portion immediately below the gate electrode 4 and at least a portion of a region where a sidewall 8 is formed. And a sidewall 8 is formed from the sidewall of the gate electrode 4 to the silicon nitride film or the silicon oxynitride film 7. A gate electrode is formed on the gate insulating film, a sidewall is formed from the side wall of the gate electrode to the gate insulating film, and the sidewall is formed by nitriding with ammonia gas or the like or oxidizing with oxygen or N 2 O or the like. Nitrid oxidation is performed using an oxide-based gas to form a silicon nitride film or a silicon oxynitride film on a portion immediately below the gate electrode and at least a portion immediately below the sidewall.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳ型半導体装置と
その製造方法に関する。近年、ＭＯＳＦＥＴ、ＭＯＳＦ
ＥＴを用いた集積回路装置等のＭＯＳ型半導体装置の集
積化、微細化が進むにともない、ＭＯＳ型半導体装置の
ゲート絶縁膜の膜厚も益々薄くなりつつある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method for manufacturing the same. In recent years, MOSFET, MOSF
With the progress of integration and miniaturization of MOS type semiconductor devices such as integrated circuit devices using ET, the film thickness of the gate insulating film of the MOS type semiconductor devices is becoming thinner and thinner.
【０００２】[0002]
【従来の技術】そのような極微細ＭＯＳ型半導体装置に
おいては、ゲート絶縁膜の絶縁破壊、ホットキャリアに
よる性能の劣化が重大な問題となっている。これらの極
微細ＭＯＳ型半導体装置に生じる諸問題を解決する方法
の一つとして、ゲート絶縁膜に窒素を含有したシリコン
酸化膜（シリコン窒化酸化膜）を用いる方法がある。2. Description of the Related Art In such an ultra-fine MOS semiconductor device, dielectric breakdown of a gate insulating film and deterioration of performance due to hot carriers are serious problems. As one of methods for solving various problems occurring in these ultrafine MOS semiconductor devices, there is a method of using a silicon oxide film (silicon oxynitride film) containing nitrogen as a gate insulating film.
【０００３】[0003]
【発明が解決しようとする課題】極微細ＭＯＳ型半導体
装置においては、絶縁破壊もホットキャリアによる劣化
もゲート電極とサイドウォールの境界近傍で生じること
が多い。したがって、ゲート電極とサイドウォールの境
界近傍にシリコン窒化酸化膜を形成することが前記の問
題を解決する上での鍵となる。ところで、極微細ＭＯＳ
型半導体装置のゲート絶縁膜は、ゲート長０．２μｍで
５ｎｍ程度と極めて薄いため、ゲート電極の加工時およ
び後処理においてサイドウォールの下になるゲート絶縁
膜が消失してしまうことがある。In an ultra-fine MOS semiconductor device, dielectric breakdown and deterioration due to hot carriers often occur near the boundary between the gate electrode and the sidewall. Therefore, forming a silicon oxynitride film in the vicinity of the boundary between the gate electrode and the sidewall is the key to solving the above problem. By the way, ultra-fine MOS
Since the gate insulating film of the semiconductor device has a gate length of 0.2 μm and is as thin as about 5 nm, the gate insulating film under the sidewall may disappear during the processing of the gate electrode and the post-treatment.
【０００４】すなわち、極微細ＭＯＳ型半導体装置で
は、ゲート電極とサイドウォールの境界近傍のサイドウ
ォールの下にはシリコン窒化酸化膜が無いことになり、
そのために特性の劣化が生じることになる。本発明は、
ゲート電極の直下の一部とサイドウォールの下の少なく
とも一部にシリコン窒化酸化膜を形成して前記の特性の
劣化を防ぐことを目的とする。That is, in the ultrafine MOS type semiconductor device, there is no silicon oxynitride film under the sidewall near the boundary between the gate electrode and the sidewall.
As a result, the characteristics are deteriorated. The present invention
It is an object of the present invention to form a silicon oxynitride film on a portion immediately below the gate electrode and at least a portion below the side wall to prevent the deterioration of the above characteristics.
【０００５】[0005]
【課題を解決するための手段】本発明にかかるＭＯＳ型
半導体装置においては、ゲート電極の中央部の下のゲー
ト絶縁膜がシリコン酸化膜からなり、該ゲート電極の周
辺部の下のゲート絶縁膜がシリコン窒化膜またはシリコ
ン窒化酸化膜からなる構成を採用した。In the MOS semiconductor device according to the present invention, the gate insulating film below the central portion of the gate electrode is made of a silicon oxide film, and the gate insulating film below the peripheral portion of the gate electrode. Is a silicon nitride film or a silicon oxynitride film.
【０００６】本発明にかかるＭＯＳ型半導体装置の製造
方法においては、ゲート絶縁膜の上にゲート電極を形成
する工程と、該ゲート電極の直下の一部およびサイドウ
ォールを形成する領域の少なくとも一部にシリコン窒化
膜またはシリコン窒化酸化膜を形成する工程と、該ゲー
ト電極の側壁から該シリコン窒化膜またはシリコン窒化
酸化膜の上にかけてサイドウォールを形成する工程を採
用した。In the method of manufacturing a MOS type semiconductor device according to the present invention, a step of forming a gate electrode on a gate insulating film, and a portion immediately below the gate electrode and at least a portion of a region where a sidewall is formed are formed. A step of forming a silicon nitride film or a silicon oxynitride film and a step of forming a sidewall from the side wall of the gate electrode to the silicon nitride film or the silicon oxynitride film are adopted.
【０００７】また、本発明にかかる他のＭＯＳ型半導体
装置の製造方法においては、ゲート絶縁膜の上にゲート
電極を形成する工程と、該ゲート電極の側壁から該ゲー
ト絶縁膜の上にかけてサイドウォールを形成する工程
と、該ゲート電極の直下の一部および該サイドウォール
直下の少なくとも一部にシリコン窒化膜またはシリコン
窒化酸化膜を形成する工程を採用した。Further, in another method for manufacturing a MOS type semiconductor device according to the present invention, a step of forming a gate electrode on the gate insulating film and a sidewall from the side wall of the gate electrode to the gate insulating film are formed. And a step of forming a silicon nitride film or a silicon oxynitride film on a portion immediately below the gate electrode and at least a portion immediately below the sidewall.
【０００８】これらの場合、アンモニアガスによる窒化
と酸素による酸化、または、Ｎ2 Ｏガス等窒化酸化物系
のガスによって窒化酸化膜を形成することができる。In these cases, the oxynitride film can be formed by nitriding with ammonia gas and oxidization with oxygen, or nitriding oxide-based gas such as N 2 O gas.
【０００９】また、これらの場合、アンモニアガスによ
る窒化および酸素による酸化、または、窒化酸化物系の
ガスによる窒化酸化を、８５０℃以下の温度で行うこと
ができる。また、これらの場合、アンモニアガスによる
窒化、酸素による酸化、または、窒化酸化物系のガスに
よる窒化酸化を、高温短時間熱処理によって行うことが
できる。In these cases, the nitriding with ammonia gas and the oxidization with oxygen, or the nitriding oxidation with the oxynitride-based gas can be performed at a temperature of 850 ° C. or lower. In these cases, nitriding with ammonia gas, oxidation with oxygen, or nitriding oxidation with a nitride oxide gas can be performed by high-temperature short-time heat treatment.
【００１０】[0010]
【作用】前記のように、ゲート絶縁膜の上にゲート電極
を形成する工程と、該ゲート電極の直下の一部およびサ
イドウォールを形成する領域の少なくとも一部にシリコ
ン窒化膜またはシリコン窒化酸化膜を形成する工程と、
該ゲート電極の側壁から該シリコン窒化膜またはシリコ
ン窒化酸化膜の上にかけてサイドウォールを形成する工
程を用いると、ホットキャリア耐性を向上することがで
きる。As described above, the step of forming the gate electrode on the gate insulating film, and the silicon nitride film or the silicon oxynitride film on at least part of the region directly below the gate electrode and the region where the sidewall is formed. A step of forming
The hot carrier resistance can be improved by using the step of forming the sidewall from the sidewall of the gate electrode to the silicon nitride film or the silicon oxynitride film.
【００１１】また、ゲート絶縁膜の上にゲート電極を形
成する工程と、該ゲート電極の側壁から該ゲート絶縁膜
の上にかけてサイドウォールを形成する工程と、該ゲー
ト電極の直下の一部および該サイドウォール直下の少な
くとも一部にシリコン窒化膜またはシリコン窒化酸化膜
を形成する工程を用いると、ホットキャリア耐性を向上
することができる。Further, a step of forming a gate electrode on the gate insulating film, a step of forming a side wall from the side wall of the gate electrode to the upper surface of the gate insulating film, a part immediately below the gate electrode and the gate electrode. The hot carrier resistance can be improved by using the step of forming the silicon nitride film or the silicon oxynitride film on at least a portion immediately below the sidewall.
【００１２】これらの場合、アンモニアガスによる窒化
と酸素による酸化、または、Ｎ2 Ｏガス等の窒化酸化物
系のガスによって窒化酸化膜を形成すると、高純度のガ
スが安価に得られ、工程にも困難な点を生じなることな
く、現実的である。In these cases, when a nitriding oxide film is formed by nitriding with ammonia gas and oxidation with oxygen, or a oxynitride-based gas such as N 2 O gas, a high-purity gas can be obtained at low cost. Is realistic without causing any difficulties.
【００１３】また、これらの場合、アンモニアガスによ
る窒化および酸素による酸化、または、窒化酸化物系の
ガスによる窒化酸化を、８５０℃以下の温度で行うか、
高温短時間熱処理によって行うと、ソース領域、ドレイ
ン領域等の不純物分布に悪影響を与えない。In these cases, the nitriding with ammonia gas and the oxidization with oxygen, or the nitriding and oxidization with a nitride oxide gas are performed at a temperature of 850 ° C. or lower,
The heat treatment performed at a high temperature for a short time does not adversely affect the impurity distribution in the source region, the drain region, and the like.
【００１４】[0014]
【実施例】以下、本発明の実施例を説明する。 （第１実施例）図１は、第１実施例のＭＯＳ型半導体装
置の製造工程説明図であり、（Ａ）〜（Ｄ）は各工程を
示している。この図において、１はシリコン基板、２は
フィールド酸化膜、３はゲート絶縁膜、４はゲート電
極、５はシリコン窒化膜、６はシリコン窒化酸化膜、７
はシリコン窒化酸化膜、８はサイドウォールである。こ
の工程説明図において、第１実施例のＭＯＳ型半導体装
置の製造方法を説明する。Embodiments of the present invention will be described below. (First Embodiment) FIGS. 1A to 1C are views for explaining a manufacturing process of a MOS type semiconductor device according to the first embodiment, and FIGS. In this figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate insulating film, 4 is a gate electrode, 5 is a silicon nitride film, 6 is a silicon nitride oxide film, and 7 is a silicon nitride oxide film.
Is a silicon oxynitride film, and 8 is a sidewall. A method of manufacturing the MOS type semiconductor device according to the first embodiment will be described with reference to the process diagram.
【００１５】第１工程（図１（Ａ）参照） シリコン基板１の上面に素子形成領域を画定するフィー
ルド酸化膜（ＬＯＣＯＳ酸化膜）２を形成し、この素子
形成領域のシリコン基板１の表面を熱酸化してシリコン
酸化物からなるゲート絶縁膜３を形成する。このゲート
絶縁膜３の上にＣＶＤによってポリシリコン層を形成
し、このポリシリコン層をＲＩＥによってパターニング
してゲート電極３を形成する。このゲート電極４のパタ
ーニングによってゲート電極４の周囲のゲート絶縁膜３
が除去される。First step (see FIG. 1A) A field oxide film (LOCOS oxide film) 2 that defines an element formation region is formed on the upper surface of a silicon substrate 1, and the surface of the silicon substrate 1 in this element formation region is formed. The gate insulating film 3 made of silicon oxide is formed by thermal oxidation. A polysilicon layer is formed on the gate insulating film 3 by CVD, and the polysilicon layer is patterned by RIE to form the gate electrode 3. By patterning the gate electrode 4, the gate insulating film 3 around the gate electrode 4 is formed.
Are removed.
【００１６】第２工程（図１（Ｂ）参照） 第１工程でゲート電極４を形成したシリコン基板１をア
ンモニアガス中で、温度８００℃で１０分間加熱する。
その結果、ゲート電極４の表面と露出しているシリコン
基板の表面にシリコン窒化膜５が形成され、ゲート電極
４の下の内周のゲート絶縁膜３がシリコン窒化酸化膜６
に変換される。Second step (see FIG. 1B) The silicon substrate 1 having the gate electrode 4 formed in the first step is heated in ammonia gas at a temperature of 800 ° C. for 10 minutes.
As a result, the silicon nitride film 5 is formed on the surface of the gate electrode 4 and the exposed surface of the silicon substrate, and the gate insulating film 3 on the inner circumference below the gate electrode 4 is formed by the silicon nitride oxide film 6.
Is converted to.
【００１７】第３工程（図１（Ｃ）参照） 第２工程でシリコン窒化膜５が形成されたシリコン基板
１を、酸素ガス中で、８００℃２０分間加熱する。その
結果、シリコン窒化膜５がシリコン窒化酸化膜７に変換
される。Third Step (see FIG. 1C) The silicon substrate 1 having the silicon nitride film 5 formed in the second step is heated in oxygen gas at 800 ° C. for 20 minutes. As a result, the silicon nitride film 5 is converted into the silicon nitride oxide film 7.
【００１８】第４工程（図１（Ｄ）参照） 第３工程で窒化酸化膜７が形成されたシリコン基板１の
上にＣＶＤによってシリコン酸化膜を堆積し、このシリ
コン酸化膜をＲＩＥによって異方性エッチングすること
によってゲート電極４の側壁にサイドウォール８を形成
する。Fourth Step (see FIG. 1D) A silicon oxide film is deposited by CVD on the silicon substrate 1 on which the nitride oxide film 7 is formed in the third step, and this silicon oxide film is anisotropically formed by RIE. Side wall 8 is formed on the side wall of the gate electrode 4 by performing the selective etching.
【００１９】この製造工程において、シリコン窒化酸化
膜７を形成する前あるいは後に、ＬＤＤを形成するため
の不純物のイオン注入を行い、サイドウォール８を形成
した後にソース領域とドレイン領域を形成するための不
純物のイオン注入を行い、ソース領域とドレイン領域に
電極を形成してＭＯＳ型半導体装置を完成する。In this manufacturing process, before or after forming the silicon oxynitride film 7, ion implantation of impurities for forming the LDD is performed, and after forming the sidewalls 8, the source region and the drain region are formed. Impurity ions are implanted to form electrodes in the source region and the drain region to complete the MOS semiconductor device.
【００２０】この熱処理によって、ゲート電極４の下の
内周のゲート絶縁膜３がシリコン窒化酸化膜６に変換す
ることができるとともに、チャネルプロファイル、ＬＤ
Ｄ構造等の不純物分布が変化することがなかった。By this heat treatment, the inner gate insulating film 3 under the gate electrode 4 can be converted into the silicon oxynitride film 6, and the channel profile, LD
The distribution of impurities such as D structure did not change.
【００２１】（第２実施例）この実施例においては、第
１実施例の第３工程（図１（Ｃ）参照）の酸化を、酸素
ガス中で、１０００℃で１０秒間の高温短時間熱処理
（Ｒａｐｉｄ Ｔｈｅｒｍａｌ Ｐｒｏｃｅｓｓ：ＲＴ
Ｐ）で行う点が特徴である。この熱処理によって、ゲー
ト電極４の下の内周のゲート絶縁膜３がシリコン窒化酸
化膜６に変換することができるとともに、チャネルプロ
ファイル、ＬＤＤ構造等の不純物分布が変化することが
なかった。(Second Embodiment) In this embodiment, the oxidation in the third step of the first embodiment (see FIG. 1C) is performed by a high temperature short time heat treatment at 1000 ° C. for 10 seconds in oxygen gas. (Rapid Thermal Process: RT
The feature is that it is performed in P). By this heat treatment, the inner gate insulating film 3 under the gate electrode 4 could be converted into the silicon oxynitride film 6, and the impurity distribution such as the channel profile and the LDD structure was not changed.
【００２２】（第３実施例）図２は、第３実施例のＭＯ
Ｓ型半導体装置の製造工程説明図であり、（Ａ）〜
（Ｃ）は各工程を示している。この図において、１１は
シリコン基板、１２はフィールド酸化膜、１３はゲート
絶縁膜、１４はゲート電極、１５はサイドウォール、１
６はシリコン窒化酸化膜である。この工程説明図におい
て、第３実施例のＭＯＳ型半導体装置の製造方法を説明
する。(Third Embodiment) FIG. 2 shows the MO of the third embodiment.
FIG. 9A is an explanatory diagram of the manufacturing process of the S-type semiconductor device,
(C) shows each process. In this figure, 11 is a silicon substrate, 12 is a field oxide film, 13 is a gate insulating film, 14 is a gate electrode, 15 is a sidewall, 1
6 is a silicon oxynitride film. A method of manufacturing the MOS type semiconductor device according to the third embodiment will be described with reference to the process diagram.
【００２３】第１工程（図２（Ａ）参照） シリコン基板１１の上面に素子形成領域を画定するフィ
ールド酸化膜（ＬＯＣＯＳ酸化膜）１２を形成し、この
素子形成領域のシリコン基板１１の表面を熱酸化してシ
リコン酸化物からなるゲート絶縁膜１３を形成する。こ
のゲート絶縁膜１３の上にＣＶＤによってポリシリコン
層を形成し、このポリシリコン層をＲＩＥによってパタ
ーニングしてゲート電極１４を形成する。このゲート電
極１４のパターニングによってゲート電極１４の周囲の
ゲート絶縁膜１３が除去される。First step (see FIG. 2A) A field oxide film (LOCOS oxide film) 12 that defines an element formation region is formed on the upper surface of the silicon substrate 11, and the surface of the silicon substrate 11 in this element formation region is formed. The gate insulating film 13 made of silicon oxide is formed by thermal oxidation. A polysilicon layer is formed on the gate insulating film 13 by CVD, and the polysilicon layer is patterned by RIE to form a gate electrode 14. By patterning the gate electrode 14, the gate insulating film 13 around the gate electrode 14 is removed.
【００２４】第２工程（図２（Ｂ）参照） 第１工程でゲート電極１４が形成されたシリコン基板１
１の上にＣＶＤによってシリコン酸化膜を堆積し、この
シリコン酸化膜を異方性エッチングすることによってゲ
ート電極１４の側壁にサイドウォール１５を形成する。Second step (see FIG. 2B) Silicon substrate 1 having gate electrode 14 formed in the first step
A silicon oxide film is deposited on the first electrode 1 by CVD, and the silicon oxide film is anisotropically etched to form a sidewall 15 on the side wall of the gate electrode 14.
【００２５】第３工程（図２（Ｃ）参照） 第２工程でゲート電極１４の側壁にサイドウォール１５
を形成したシリコン基板１１をＮ2 Ｏガス（亜酸化窒素
ガス、笑気ガス）中で、１０５０℃の温度で１０分間の
熱処理を行い、ゲート電極１４の表面と、サイドウォー
ル１５の下と、露出しているシリコン基板の表面にシリ
コン窒化酸化膜１６を形成する。Third step (see FIG. 2C) In the second step, the sidewall 15 is formed on the side wall of the gate electrode 14.
The silicon substrate 11 on which is formed is heat-treated in N 2 O gas (nitrous oxide gas, laughing gas) at a temperature of 1050 ° C. for 10 minutes to form the surface of the gate electrode 14 and the side wall 15 below. A silicon oxynitride film 16 is formed on the exposed surface of the silicon substrate.
【００２６】この製造工程において、ゲート電極１４を
形成した後に、ＬＤＤを形成するための不純物のイオン
注入を行い、サイドウォール１５を形成した後にソース
領域とドレイン領域を形成するための不純物のイオン注
入を行い、ソース領域とドレイン領域に電極を形成して
ＭＯＳ型半導体装置を完成する。In this manufacturing process, after the gate electrode 14 is formed, ion implantation of impurities for forming the LDD is performed, and after forming the sidewalls 15, ion implantation of impurities for forming the source region and the drain region is performed. Then, electrodes are formed in the source region and the drain region to complete the MOS type semiconductor device.
【００２７】この熱処理によって、ゲート電極４の下の
内周のゲート絶縁膜３がシリコン窒化酸化膜６に変換す
ることができるとともに、チャネルプロファイル、ＬＤ
Ｄ構造等の不純物分布が変化することがなかった。By this heat treatment, the inner gate insulating film 3 under the gate electrode 4 can be converted into the silicon oxynitride film 6, and the channel profile and LD
The distribution of impurities such as D structure did not change.
【００２８】[0028]
【発明の効果】以上説明したように、本発明によると、
極微細ＭＯＳ型半導体装置のホットキャリア耐性（寿
命）を５倍以上にすることができ、経時絶縁破壊までの
寿命を２倍にすることができるため、極微細ＭＯＳ型半
導体装置の実用化に寄与するところが大きい。As described above, according to the present invention,
Since the hot carrier resistance (lifetime) of the ultrafine MOS semiconductor device can be increased five times or more, and the lifetime until the dielectric breakdown with time can be doubled, it contributes to the practical application of the ultrafine MOS semiconductor device. There is a lot to do.
【図１】第１実施例のＭＯＳ型半導体装置の製造工程説
明図であり、（Ａ）〜（Ｄ）は各工程を示している。FIG. 1 is an explanatory diagram of a manufacturing process of a MOS semiconductor device according to a first embodiment, in which (A) to (D) show each process.
【図２】第３実施例のＭＯＳ型半導体装置の製造工程説
明図であり、（Ａ）〜（Ｃ）は各工程を示している。FIG. 2 is an explanatory view of the manufacturing process of the MOS type semiconductor device of the third embodiment, in which (A) to (C) show each process.
１ シリコン基板 ２ フィールド酸化膜 ３ ゲート絶縁膜 ４ ゲート電極 ５ シリコン窒化膜 ６ シリコン窒化酸化膜 ７ シリコン窒化酸化膜 ８ サイドウォール １１ シリコン基板 １２ フィールド酸化膜 １３ ゲート絶縁膜 １４ ゲート電極 １５ サイドウォール １６ シリコン窒化酸化膜 1 Silicon Substrate 2 Field Oxide Film 3 Gate Insulation Film 4 Gate Electrode 5 Silicon Nitride Film 6 Silicon Nitride Oxide Film 7 Silicon Nitride Oxide Film 8 Sidewall 11 Silicon Substrate 12 Field Oxide Film 13 Gate Insulation Film 14 Gate Electrode 15 Sidewall 16 Silicon Nitride oxide film
Claims (4)
がシリコン酸化膜からなり、該ゲート電極の周辺部の下
のゲート絶縁膜がシリコン窒化膜またはシリコン窒化酸
化膜からなることを特徴とするＭＯＳ型半導体装置。1. The gate insulating film below the central portion of the gate electrode is made of a silicon oxide film, and the gate insulating film below the peripheral portion of the gate electrode is made of a silicon nitride film or a silicon nitride oxide film. MOS type semiconductor device.
る工程と、該ゲート電極の直下の一部およびサイドウォ
ールを形成する領域の少なくとも一部にシリコン窒化膜
またはシリコン窒化酸化膜を形成する工程と、該ゲート
電極の側壁から該シリコン窒化膜またはシリコン窒化酸
化膜の上にかけてサイドウォールを形成する工程を含む
ことを特徴とするＭＯＳ型半導体装置の製造方法。2. A step of forming a gate electrode on a gate insulating film, and a silicon nitride film or a silicon oxynitride film is formed in a portion immediately below the gate electrode and at least a portion of a region where a sidewall is formed. A method of manufacturing a MOS type semiconductor device comprising: a step of forming a sidewall from the sidewall of the gate electrode to the silicon nitride film or the silicon oxynitride film.
る工程と、該ゲート電極の側壁から該ゲート絶縁膜の上
にかけてサイドウォールを形成する工程と、該ゲート電
極の直下の一部および該サイドウォール直下の少なくと
も一部にシリコン窒化膜またはシリコン窒化酸化膜を形
成する工程を含むことを特徴とするＭＯＳ型半導体装置
の製造方法。3. A step of forming a gate electrode on a gate insulating film, a step of forming a sidewall from the side wall of the gate electrode to the top of the gate insulating film, and a portion immediately below the gate electrode and the gate electrode. A method of manufacturing a MOS type semiconductor device, comprising the step of forming a silicon nitride film or a silicon oxynitride film on at least a portion immediately below a sidewall.
酸化、または、窒化酸化物系のガスによって窒化酸化膜
を形成することを特徴とする請求項２または請求項３に
記載されたＭＯＳ型半導体装置の製造方法。4. The MOS type semiconductor device according to claim 2, wherein the nitriding with ammonia gas and the oxidization with oxygen, or the oxynitride film is formed with a oxynitride-based gas. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12099595A JP3390895B2 (en) | 1995-05-19 | 1995-05-19 | Method of manufacturing MOS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12099595A JP3390895B2 (en) | 1995-05-19 | 1995-05-19 | Method of manufacturing MOS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08316466A true JPH08316466A (en) | 1996-11-29 |
| JP3390895B2 JP3390895B2 (en) | 2003-03-31 |
Family
ID=14800183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12099595A Expired - Lifetime JP3390895B2 (en) | 1995-05-19 | 1995-05-19 | Method of manufacturing MOS type semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3390895B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6057217A (en) * | 1996-07-25 | 2000-05-02 | Nec Corporation | Process for production of semiconductor device with foreign element introduced into silicon dioxide film |
| WO2005048333A1 (en) * | 2003-11-08 | 2005-05-26 | Advanced Micro Devices, Inc. | Method for integrating a high-k gate dielectric in a transistor fabrication process |
| JP2008515240A (en) * | 2004-10-01 | 2008-05-08 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Gate stack |
| KR100889551B1 (en) * | 2007-06-25 | 2009-03-23 | 주식회사 동부하이텍 | Semiconductor device manufacturing method |
-
1995
- 1995-05-19 JP JP12099595A patent/JP3390895B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6057217A (en) * | 1996-07-25 | 2000-05-02 | Nec Corporation | Process for production of semiconductor device with foreign element introduced into silicon dioxide film |
| WO2005048333A1 (en) * | 2003-11-08 | 2005-05-26 | Advanced Micro Devices, Inc. | Method for integrating a high-k gate dielectric in a transistor fabrication process |
| GB2423636A (en) * | 2003-11-08 | 2006-08-30 | Advanced Micro Devices Inc | Method for integrating a high-k gate dielectric in a transistor fabrication pr ocess |
| GB2423636B (en) * | 2003-11-08 | 2007-05-02 | Advanced Micro Devices Inc | Method for integrating a high-k gate dielectric in a transistor fabrication process |
| JP2008515240A (en) * | 2004-10-01 | 2008-05-08 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Gate stack |
| KR100889551B1 (en) * | 2007-06-25 | 2009-03-23 | 주식회사 동부하이텍 | Semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3390895B2 (en) | 2003-03-31 |
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