JPH08315569A - Semiconductor memory device and data processing device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to improve the yield of a semiconductor memory device having a self-refresh function. [Structure] A register that allows external setting of timer cycle information is provided in the SDRAM 32, and the refresh timer 22 is provided with the SDRAM 32 installed in a data processing device.
1 cycle can be set. As a result, the SDRAM3
In the probe inspection process of No. 2, it is unnecessary to adjust the refresh timer cycle by blowing the fuse,
A yield improvement of 32 is achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a refresh control technique for a semiconductor memory device including dynamic memory cells arranged in a matrix. For example, an SDRAM (synchronous dynamic) capable of operating in synchronization with an external clock. -Random access memory) and a technique effective when applied to a data processing device including the same.

[0002]

2. Description of the Related Art DRAM as an example of a semiconductor memory device
Is an address buffer, a decoder, as described in "LSI Handbook (Page 486-)" issued by Ohmsha, Ltd. on November 30, 1984.
A peripheral circuit such as a sense amplifier uses a dynamic circuit that operates in synchronization with a clock to reduce power consumption. The DRAM requires external clocks of one to three phases, and an internal circuit clock is generated based on these clocks to control or drive the peripheral circuits. In such a DRAM,
Random access is mainly performed, and a memory cell is selected by sequentially reading a row address and a column address for each access. Each part of the peripheral circuit is controlled by an internal clock so as to follow the procedures of row selection, detection of memory cell information, and column selection in order to prevent information destruction of the memory cell. In a normal DRAM mounted on a system, a read / write operation is performed asynchronously with a system clock, while an SDRAM is a semiconductor memory device operated in synchronization with the system clock. This SDRAM has data in synchronization with a clock,
Since the address and control signals can be input / output, a large-capacity memory similar to DRAM can be operated at high speed comparable to SRAM, and some data can be accessed to one selected word line. By designating this by the burst length, a plurality of data can be continuously read or written by sequentially switching the selected states of the column system by the built-in column address counter. In such SDRAMs and DRAMs, since dynamic memory cells are used as memory cells, a refresh operation is required to retain stored information.

[0003]

One of the refresh operations is self-refresh. In the semiconductor memory device, the cycle of the refresh timer can be adjusted to be longer than the standard cycle in order to reduce power consumption during self refresh. This adjustment is made possible by selectively blowing a fuse formed in advance in the probe inspection process. In other words, if the fuse is not blown, the timer period is set to the standard period, but by selectively blowing the fuse, this timer period can be set longer than the standard period. The power consumption during refreshing can be reduced.

In the probe inspection process, defective bits (including refresh defects) are relieved in addition to the cycle adjustment of the refresh timer. That is, the defective bit is relieved by setting the redundant bit to be selected instead of the defective bit. This defect relief is also performed by blowing the fuse, as in the case of adjusting the cycle of the refresh timer.

In the above-described cycle adjustment of the refresh timer or defective bit relief, when defective bit relief is performed after setting the timer period, if the refresh bit refresh capability is lower than the timer period, The relief bit becomes defective refresh. However, the refresh failure occurring at that time cannot be repaired anymore because the defect repair and the timer cycle adjustment are performed by the fuse blowing, which results in the yield of the semiconductor memory device having the self-refresh function. Causing a decline.

An object of the present invention is to improve the yield of semiconductor memory devices having a self-refresh function.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, when the semiconductor memory device (32) is formed including the refresh timer (221) for controlling the refresh cycle of the dynamic memory cell based on the set timer cycle information, the timer cycle information is set. (300A) that enables external setting of
Is provided.

Further, the semiconductor memory device (32) includes a mode register (300) capable of setting various information from the outside and a control system circuit (85) for controlling the operation of each part according to the setting information of the mode register. Is formed, the refresh period for controlling the refresh period of the dynamic memory cell is controlled according to the timer period information setting area (8 to 11) formed in the mode register and the timer period information set in the timer period setting area. A timer (221) is provided.

Furthermore, the semiconductor memory device (3
A data processing device can be formed including 2).

[0012]

According to the above-mentioned first means, it is possible to set the timer period from the system to the above-mentioned register in the state where the semiconductor memory device is mounted in the system, which is the refreshing by fuse blowing in the probe inspection process. An improvement in the yield of a semiconductor memory device equipped with a self-refresh function is achieved by eliminating the need for timer cycle adjustment.

According to the above-mentioned second means, it is possible to set the timer period from the system to the timer period information setting area formed in the mode register in the state where the semiconductor memory device is mounted in the system. This eliminates the need to adjust the refresh timer cycle by blowing the fuse in the probe inspection process, and improves the yield of the semiconductor memory device having the self-refresh function.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows a data processing apparatus according to an embodiment of the present invention.

This data processing device has a system bus BU.
CPU (Central Processing Unit) 31, SDRAM via S
32, SRAM 33, ROM (Read Only Memory) 34, peripheral device control unit 35, display system 36, etc. are connected so that signals can be exchanged with each other, and as a computer system for performing predetermined data processing according to a predetermined program. Composed. The CPU 30 is the logical core of this system, and mainly addresses, reads and writes information, calculates data, sequences instructions, accepts interrupts, activates information exchange between storage devices and input / output devices, etc. It has the function of, arithmetic control unit, bus control unit,
It is composed of a memory access control unit and the like. Above SDR
The AM 32, SRAM 33, and ROM 34 are positioned as internal storage devices. And SDRAM3
2 and the SRAM 33 store programs and data necessary for calculation and control by the CPU 30. The peripheral device control unit 35 controls the operation of the external storage device 38 and the information input control from the keyboard 39 or the like. Further, the display system 36 controls the information display on the CRT display 40.

FIG. 1 shows a configuration example of the SDRAM 32.

Although not particularly limited, the SDRAM 32 shown in the same figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The SDRAM 32 includes a memory array 200A forming a memory bank A and a memory array 200B forming a memory bank B. Each memory array 2
00A and 200B include dynamic type memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the same column are coupled to the word line (not shown) for each column, and the same row is used. The data input / output terminals of the memory cells arranged at are connected to complementary data lines (not shown) row by row.

One word line (not shown) of the memory array 200A is driven to the selection level according to the decoding result of the row address signal by the row decoder 201A. The complementary data line (not shown) of the memory array 200A is coupled to the sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line when data is read from the memory cell. The column switch circuit therein is a switch circuit for individually selecting complementary data lines and bringing them into conduction with the complementary common data line 204. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A. Similarly, the row decoder 2 is also provided on the memory array 200B side.
01B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are provided. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. Input buffer 2
10 input terminals and the output terminal of the output buffer 211 are 1
It is connected to 6-bit data input / output terminals I / O0 to I / O15.

The row address signal and the column address signal supplied from the address input terminals A0 to A11 are fetched in the column address buffer 205 and the row address buffer 206 in the address multiplex format. The supplied address signal is held in each buffer. In the refresh operation mode, the row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal according to an address switching signal ADS from a refresh control circuit 222 described later. The output of the column address buffer 205 is supplied as preset data of the column address counter 207, and the column address counter 207 outputs the column address signal as the preset data or a value obtained by sequentially incrementing the column address signal according to the operation mode. , Column decoder 2
Output to 03A and 203B.

The controller 212 is not particularly limited, but may be a clock signal CLK and a clock enable signal CK.
E, chip select signal CS * (the symbol * means that the signal to which it is attached is a low enable signal), column address strobe signal CAS *, row address strobe signal RAS *, write enable signal WE *, etc. External control signal and address input terminal A
Control data from 0 to A11 is supplied, and SDRA is performed based on the level of these signals and the timing of change.
It forms an internal timing signal for controlling the operation mode of M and the operation of the circuit block, and includes a control logic (not shown) for that purpose and a mode register 300. Various control signals such as the clock signal CLK, the clock enable signal CKE, and the chip select signal CS * are sent from the CPU 31 to the system bus BUS.
Is transmitted through.

The clock signal CLK is used as the master clock of the SDRAM 32, and other external input signals are significant in synchronization with the rising edge of the clock signal CLK. The chip select signal CS * indicates the start of the command input cycle by its low level. When the chip select signal is at high level (chip not selected),
Other signal inputs have no meaning. However, internal operations such as a selected state of a memory bank and a burst operation, which will be described later, are not affected by the change to the chip non-selected state. R
The signals AS *, CAS *, and WE * have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle. The clock enable signal CKE is a signal instructing the validity of the next clock signal. If the signal CKE is at the high level, the rising edge of the next clock signal CLK is valid, and if it is at the low level, it is invalid. . Further, although not shown, an external control signal for controlling output enable to the output buffer 211 in the read mode is also supplied to the controller 212. When the signal is, for example, high level, the output buffer 211 is set to a high output impedance state. It

The row address signal is a clock signal C.
A0 in the row address strobe / bank active command cycle synchronized with the rising edge of LK
~ Is defined by the level of A11.

The input from A11 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A11 is low level, the memory bank A is selected, and when the input of A11 is high level, the memory bank B is selected. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the unselected memory bank side are not selected, the input buffer 210 and the output buffer on the selected memory bank side only. This can be performed by processing such as connection to 211.

A in the precharge command cycle
The input of 11 indicates the mode of the precharge operation for the complementary data line and the like, the high level thereof indicates that the target of the precharge is both memory banks, and the low level thereof is indicated by A11. Memory bank of is subject to precharge.

The column address signal is defined by the levels of A0 to A7 in the read or write command cycle synchronized with the rising edge of the clock signal CLK. The column address thus defined is used as the start address for burst access.

Next, refreshing for holding information in the dynamic memory cell will be described.

A timer period information setting area is formed in the mode register 300. A refresh timer 221 for controlling the refresh cycle of the dynamic memory cell is provided according to the timer cycle information set in the timer cycle area. When the self-refresh mode or the auto-refresh mode is entered, the controller 212 controls the self-refresh signal SF.
R or the auto refresh signal ATR is asserted. In response to this signal, the refresh control circuit 222 controls the path switching of the address taken into the row address buffer 206 by the address switching signal ADS. That is, when the self-refresh signal SFR or the auto-refresh signal ATR is asserted, the output address of the refresh counter 208 passes through the row address buffer 206 and the row decoder 201A.
Or it is transmitted to 201B. Further, the refresh control circuit 222 obtains a logical sum of the auto-refresh signal ATR and the self-refresh activation signal SRS from the refresh timer 221, and transmits the logical sum to the controller 212 as a refresh operation activation signal RFS. When the refresh operation activation signal RFS is asserted, the refresh operation is started under the control of the controller 212. Further, in the self refresh mode, the refresh control circuit 222 instructs the count amplifier of the refresh counter 208.

FIG. 2 shows a configuration example of the mode register 300.

The mode register 30 is not particularly limited.
0 includes an operation mode register 300A and a test mode register 300B, and information can be set (held) by asserting the mode set signal to low level. Although not particularly limited, each of the operation mode register 300A and the test mode register 300B has a 12-bit configuration. The seventh signal A7 is an enable bit, and the setting of the test mode register 300B and the setting of the operation mode register 300A are selected depending on the state of the enable bit. For example, a chip select signal CS *, a row address strobe signal RAS *, a column address strobe signal CAS
When all of *, the write enable signal WE *, and the signal A7 are low level, the operation mode register 300A can be set. At this time, the test mode register 300B is reset. Further, when the chip select signal CS *, the row address strobe signal RAS *, the column address strobe signal CAS *, and the write enable signal WE * are set to the low level and the signal A7 is set to the high level, the test mode register 300B can be set. It is said that

In the operation mode register 300A, bits 0 to 6 are used as the operation mode setting area, although not particularly limited thereto. The operation mode information set in the operation mode setting area includes burst length, burst type (BT), and column address strobe signal CAS *.
Includes CAS latency and the like indicating in what cycle the data is output after the assertion of. The maximum burst length is eight types, the maximum burst type is two types, and the CAS latency is maximum eight types. The burst length is set to bits 0 to 2, the burst type is set to bit 3, and the CAS latency is set to bits 4 to 4.
Set to 6. The set operation mode information is transmitted to the control system circuit 85. This control system circuit 85 is a part of the controller 212 shown in FIG. 1, and based on the operation mode information set in the operation mode register 300A, the synchronous D circuit of the present embodiment.
It controls the operation of each part of the RAM.

In the operation mode register 300A, bits 8 to 11 are normally reserved bits. However, in this embodiment, this reserved bit is positively used as the timer period information setting area. That is, the information set in the bits 8 to 11 is transmitted to the refresh timer 221, and the refresh timer 221 controls the refresh cycle based on the transmitted timer cycle information. Has become. As described above, in this embodiment, since the timer period information is set by using the reserved bits (8 to 11) of the operation mode register 300A, the fuse circuit for setting the timer period is provided. Not not. Therefore, in the probe inspection step, the defective bit is relieved by the redundant configuration, but the timer period adjustment by the fuse blowing is not performed.

The setting of information in the mode register 300 is performed by the CPU 31 shown in FIG. 1 with the SDRAM 32 mounted on the data processing device.
Therefore, in order to reduce the power consumption of the SDRAM 32 during self-refresh, the refresh timer 22
If you want to set the cycle of 1 to be longer than the standard cycle, SD
The setting can be easily performed with the RAM 32 installed in the data processing device.

The test mode information set in the test mode register 300B is not particularly limited, but the first reduction test for checking the circuit characteristics and the second reduction test for checking the fail of the memory cell array. , Memory cell plate stress test, self-refresh timer check, etc. There are up to 16 such tests.

According to the above embodiment, the following operational effects can be obtained.

(1) When it is desired to set the cycle of the refresh timer 221 to be longer than the standard cycle in order to reduce the power consumption of the SDRAM 32 during self-refreshing, the SDRAM 32 can be easily installed in the data processing device. Since the setting is possible, the SDRAM3
In the probe inspection process of No. 2, it is unnecessary to adjust the cycle of the refresh timer. Of course, it is not necessary to form a fuse circuit for adjusting the cycle of the refresh timer on the chip. Therefore, the yield of SDRAM can be improved.

(2) In order to obtain the action and effect of (1), the timer period information is set by using the reserve bit in the operation mode register 300A. Therefore, the register for setting the timer period information is set. Since it is not necessary to newly form the chip, it is possible to suppress an increase in the chip occupation area.

(3) In the data processing device equipped with the SDRAM 32, the CPU 32 causes the SDRAM 32 to operate.
Since the self-refresh cycle can be set and changed, the user can arbitrarily adjust the self-refresh cycle of the SDRAM 32 according to the usage status of the data processing device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the timer period information is set by using the reserved bit in the operation mode register 300A. However, the dedicated register for setting the timer period information is called the operation mode register 300A. Alternatively, it may be separately provided. In particular, a normal D operated asynchronously with the system clock
In RAM, there is no equivalent operation mode register with reserved bits, so a dedicated register for setting timer cycle information is provided, and timer cycle information can be set in this special register via an external pin. It is good to configure it.

In the above description, the invention made by the present inventor is the SDR which is the field of application behind the invention.
Although the case of application to the AM has been described, the present invention is not limited to this and can be applied to a normal DRAM that operates asynchronously with an external clock.

The present invention can be applied on the condition that it includes at least a dynamic memory cell.

[0042]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the timer cycle can be set from the system to the register in the state where the semiconductor memory device is mounted in the system, the timer cycle adjustment by fuse blowing is not necessary, and the self-refresh function can be realized. It is possible to improve the yield of the mounted semiconductor memory device. Further, in the SDRAM, the timer cycle can be set in the mode register from the system in which the SDRAM is installed, so that it is not necessary to adjust the timer cycle by blowing the fuse of the SDRAM.
The yield can be improved. Further, in the data processing device including the semiconductor memory device, the user can arbitrarily adjust the self-refresh cycle according to the usage status of the data processing device.

[Brief description of drawings]

FIG. 1 is an overall configuration block diagram of an SDRAM installed in a data processing device that is an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a configuration example of a mode register included in the SDRAM.

FIG. 3 is a block diagram of an overall configuration example of the data processing device.

[Explanation of symbols]

 31 CPU 32 SDRAM 33 SRAM 34 ROM 35 Peripheral Device Control Unit 36 Display System 38 External Storage Device 39 Keyboard 40 CRT Display 85 Control System Circuit 201A, 201B Row Decoder 202A, 202B Sense Amplifier and Column Selection Circuit 203A, 203B Column Decoder 205 Column Address buffer 206 Row address buffer 207 Column address counter 208 Refresh counter 210 Input buffer 211 Output buffer 212 Controller 221 Refresh timer 222 Refresh control circuit 300 Mode register 300A Operation mode register 300B Test mode register

Claims (3)

[Claims] 1. A semiconductor memory device comprising: dynamic memory cells arranged in a matrix; and a refresh timer for controlling a refresh cycle of the dynamic memory cell based on set timer cycle information. A semiconductor memory device including a register that enables external setting. 2. An external clock including dynamic memory cells arranged in a matrix, a mode register in which various information can be set from the outside, and a control system circuit for controlling the operation of each unit according to the setting information of the mode register. In a semiconductor memory device capable of operating in synchronization with, a refresh for controlling a refresh cycle of the dynamic memory cell according to a timer cycle information setting area formed in the mode register and timer cycle information set in the timer cycle setting area. A semiconductor memory device including a timer. 3. A data processing device comprising the semiconductor memory device according to claim 1 or 2, and a central processing unit capable of accessing the semiconductor memory device.