JPH0831083B2 - Bus control method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method in a bus system such as a computer, and in particular, one data bus managed by a master is shared by a master and a plurality of slaves. The present invention relates to a bus control method in a bus system configured to do so.

[Conventional technology]

For example, in a bus system of a computer, one data bus managed by a master board (hereinafter referred to as a master) is shared by a master and a plurality of slave boards (hereinafter referred to as slaves), and the data bus is time-shared. There are things I tried to use.

FIG. 3 schematically shows a bus system configured in this way, where M is a master for managing the data bus DB,
S _{1 to} S _n are n slaves, and these master M and n slaves S _{1 to} S _n share one data bus DB.

In this bus system, in order to use the data bus DB in a time division manner, conventionally, the bus has been controlled by controlling the bus as follows.

That is, when one slave S ₁ wants to use the data bus DB, the master M sends a bus stop request signal (hereinafter, referred to as BHOLD) for stopping the bus operation and requesting the release of the bus.
Send to. Master M who received this BHOLD
Sends a bus stop confirmation signal (hereinafter, referred to as BHLDA) indicating that the bus operation is stopped and the bus is released, to the slave S ₁ . Then, when the slave S ₁ receives the BHLDA, it knows that the data bus DB has been surrendered, and releases the use of the data bus DB.

[Problems to be Solved by the Invention]

However, in the above conventional bus control method,
If multiple slaves request bus clearing, BHOLD and BHLDA are required for each slave S _{1 to} S _n.
In a bus system in which only one pair of D and BHLDA was prepared, it was not possible to meet the demand for multiple bus passing.

The present invention has been made with the above matters in mind, and its object is to maintain the conventional signal form,
A bus control capable of responding to a plurality of bus passing requests and capable of rationally controlling a bus system configured to share one data bus managed by a master by a master and a plurality of slaves. To provide a method.

[Means for solving the problem]

In order to achieve the above object, the bus control method according to the present invention includes a bus clearing request signal line from which a bus clearing request signal from a slave is output, and a bus clearing request signal line of the bus clearing request signal. A bus clearing destination detection strobe signal line that is set to a strobe state based on the output to the master and a bus clearing destination determining strobe signal line that outputs the bus clearing destination determining strobe signal from the master. A slave ID code unique to each slave is assigned, and when a bus clearing request signal is output from the slave, the slave having a slave ID code that matches the bus clearing destination determination strobe signal output from the master is transmitted from the slave. Based on the bus stop request signal, the master sends a bus stop confirmation signal to the corresponding slave. It

[Action]

According to the above configuration, by adding the three signals of the bus clearing request signal, the bus clearing destination detection strobe signal, and the bus clearing destination determining strobe signal to the control signal in the conventional bus system, a plurality of slaves can be obtained. It is possible to reasonably deal with the bus passing request from
Also, there is almost no need to modify the existing bus system.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a bus system for explaining the bus control system according to the present invention. In this figure, M is a master, which is common to the master M and n slaves S _{1 to} S _n . It has a function to manage the data bus DB,
A slave ID code input circuit 1, a bus clearing destination determination circuit 2, a slave ID code output circuit 3, a slave ID code input / output control circuit 4, a bus clearing control circuit 5 by BHOLD / BHLDA, and the like are provided.

Further, each of the slaves S _{1 to} S _n is assigned with a different 1-bit signal bit (signal line) in the data bus (this is called an ID code), and for example, a bus clearing request signal (hereinafter, An output circuit 6, referred to as BRQ), a slave ID code output circuit 7, a slave ID code input latch circuit 8, a BHOLD output circuit 9, a BHLDA input circuit 10, a slave ID code setting circuit 11 and the like are provided.

12 is a BHOLD signal line, 13 is a BHLDA signal line, 14 is a BRQ signal line, 15 is a bus clearing destination detection strobe signal (hereinafter, referred to as BPR) line, 16 is a bus clearing destination determination strobe signal (hereinafter, BPW) Line),
These signal lines 12 to 16 are provided on a mother board (hereinafter referred to as a mother) together with the data bus DB.

Now, a case will be described in which a bus clearing request occurs in the order in the first slave S ₁ and the second slave S ₂ (not shown).

When a bus clear request is generated in the slave, the signal is added to the BRQ signal line 14 via the BRQ output circuit 6, but since the BRQ output circuit 6 is composed of an open collector type knot element, the BRQ signal line is 14 goes low. The BRQ is wired-OR on the mother, and the BRQ is input to the master M via the slave ID code input / output control circuit 4.

When the master M receives the BRQ, it detects which slave is requesting the bus clearing, so that the master M sets the data bus DB to the input state and the BPR signal via the slave ID code input / output control circuit 4. Line 15
Then, the pulsed BPR () is output. Then, each of the slaves S _{1 to} S _n has its own slave ID code (any one of the bits of the data bus DB is set via the slave ID code setting circuit 11 while the BPR signal line 15 is at a low level). Corresponding low level signal) 1 of data bus DB
Output to bit signal line.

The master M uses the data bus DB at the rising edge of BPR.
Is taken in through the slave ID code input circuit 1 and the low level bit in the slave ID code input circuit 1 detects the slave requesting the bus clearing. For example, when a slave to which bit 0 of the data bus DB is assigned and a slave to which bit 2 is assigned request BPQ at the same time, a low-level signal output to the data bus DB by the BPR (in this case, bit 0 and 2 goes low), the master M can specify which slave requested the BRQ. Also, in this case, the data bus DB may be processed so that the bits for which the ID code is not input by BPR due to pull-up or the like are at the high level.

Then, the master M selects one of these slaves by the bus clearing destination determination circuit 2 and outputs a slave ID code (a low-level signal to be output to any bit of the data bus) corresponding to the selected slave. ) Is output to the data bus DB, and at the same time, a pulsed BPW () is output to the BPW signal line 16 via the slave ID code input / output control circuit 4.

Each slave S _{1 to} S _n latches the bit information of the data bus DB corresponding to each slave S _{1 to} S _n in the slave ID code input latch circuit 8 at the rising edge of BPW. The slave ID code input latch circuit 8 has a low level slave ID while the BPR signal line 15 is at a low level.
The same signal line as the bit of the data bus DB that outputs the code is connected, and if the slave selected by the master M, the slave ID code (low level) can be latched.

The slave that has latched its own slave ID code recognizes that it has acquired the bus use right, and
Low-level BHOLD is output to the BHOLD signal line 12 via the OLD output circuit 9 to request the master M to pass the bus. B
The master M, which has received the BHOLD via the bus clearing control circuit 5 by HOLD / BHLDA, clears the data bus DB and makes BHLDA low level via the circuit 5. The slave can use the data bus DB from the time when BHLDA becomes low level.

When the slave who has acquired the bus use right relinquishes the right, the slave sets BRQ and BHOLD to high level and withdraws them. At this time, if another slave outputs BRQ (low level), the BRQ is wired-or on the mother, so the master M is continuously requested to pass the bus. In the above procedure, the slave requesting the bus handoff is detected by BPR and BPW.

FIG. 2 shows, for example, the first slave S ₁ and the second slave S ₁ .
BRQ ₁ {see (a)} and BRQ ₂ {see ((b)}) are sequentially input from S ₂ to the master M when they are output.
BRQ {see (c)}, BPR output from master M
{See (d)} and BPW {see (e)}, BHOLD1 output from the first slave S ₁ {see (f)}, BHOLD2 output from the second slave S ₂ {see (g)} , BHOLD input to the master M (see (h)}, BHLDA output from the master M (see (i)}, slave ID code in the data bus DB {see (j)} and bus user {(k). Reference} respectively.

〔The invention's effect〕

As described above, according to the present invention, three signals of the bus clearing request signal, the bus clearing destination detection strobe signal, and the bus clearing destination determining strobe signal are added to the control signal in the conventional bus system. A bus system configured so that a single data bus managed by a master can be shared by a master and a plurality of slaves, while maintaining the conventional signal form, and being able to respond to a plurality of requests for bus passing. Can be controlled reasonably.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a bus system for explaining a bus control system according to the present invention, and FIG. 2 is a time chart when there is a bus clearing request from two slaves. FIG. 3 is a diagram for explaining a conventional technique. 14 ...... bus surrender request signal line, 15 ...... bus surrender destination detection strobe signal line, 16 ...... bus surrender destination determining strobe signal line, M ...... master, S ₁ to S _n ...... slave, DB ... … Data bus, BRQ… Bus clear request signal, B
PR: Bus clear destination detection strobe signal, BPW: Bus clear destination determination strobe signal, BHOLD: Bus stop request signal, BHLDA: Bus stop confirmation signal.

Claims (1)

[Claims] 1. A bus clearing request signal for outputting a bus clearing request signal from the slave in a bus system configured to share one data bus managed by the master by the master and a plurality of slaves. A line, a bus clearing destination detection strobe signal line that is put into a strobe state based on the output of the bus clearing request signal to the bus clearing request signal line, and a bus clearing destination determination strobe signal from the master. A bus output destination determining strobe signal line is provided, and a unique slave ID code is assigned to each slave, and when the bus output request signal is output from the slave, the bus output from the master A slave from a slave whose slave ID code matches the destination strobe signal. A bus control method, wherein the master gives a bus stop confirmation signal to the slave based on a stop request signal.