JPH08306934A - Manufacture of multitunnel junction - Google Patents
Manufacture of multitunnel junctionInfo
- Publication number
- JPH08306934A JPH08306934A JP7110423A JP11042395A JPH08306934A JP H08306934 A JPH08306934 A JP H08306934A JP 7110423 A JP7110423 A JP 7110423A JP 11042395 A JP11042395 A JP 11042395A JP H08306934 A JPH08306934 A JP H08306934A
- Authority
- JP
- Japan
- Prior art keywords
- probe
- thin wire
- fine wire
- tunnel junction
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000523 sample Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052747 lanthanoid Inorganic materials 0.000 claims description 4
- 150000002602 lanthanoids Chemical class 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- RHKZVMUBMXGOLL-UHFFFAOYSA-N cyclopentolate hydrochloride Chemical compound Cl.C1CCCC1(O)C(C(=O)OCCN(C)C)C1=CC=CC=C1 RHKZVMUBMXGOLL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 description 5
- 230000015654 memory Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子１個単位で動作が
可能な単一電子トンネル素子に用いられる多重トンネル
接合の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multiple tunnel junction used in a single electron tunnel device capable of operating in units of one electron.
【０００２】[0002]
【従来の技術】情報化社会を支えるＬＳＩは、半導体素
子すなわちトランジスタの微細化により高集積化を行っ
ている。また、素子を微細化することにより、キャリア
の走行距離や容量が縮小され、高速化等、ＬＳＩの高性
能化が可能となる。現在量産が進んでいる１６ＭＤＲＡ
Ｍでは、ゲート長が０．５μｍ、また、サンプル出荷が
行われ始めた６４ＭＤＲＡＭでは、ゲート長が０．３５
μｍ程度となっており、研究段階では０．１μｍ以下の
ゲート長でも動作確認が行われている。2. Description of the Related Art LSIs, which support the information-oriented society, are highly integrated by miniaturizing semiconductor elements, that is, transistors. Further, by miniaturizing the element, the traveling distance and capacity of the carrier can be reduced, and high performance of the LSI such as high speed can be achieved. 16M DRA now in mass production
In M, the gate length is 0.5 μm, and in 64M DRAM, which has started to be sample-shipped, the gate length is 0.35 μm.
It is about μm, and operation has been confirmed at the research stage even with a gate length of 0.1 μm or less.
【０００３】しかし、このような素子の微細化をさらに
進めた場合、ゲート電極と半導体基板間にトンネル漏れ
電流が発生するなど物理的な問題や、さらには、１動作
当りの電子数が減ってくるために、統計的な電子数のゆ
らぎが増大し、誤動作を起こし易くなるといった根本的
な問題が発生する。このために、現在のＬＳＩのよう
に、電子の統計的な性質に動作の基礎をおくのではな
く、個々の電子を制御することにより動作する単一電子
トンネル素子が提案されている。この素子の特徴は、微
細化が進む程、動作が完全になり究極の特性を引き出せ
る点にあり、例えばこれをメモリに応用することによ
り、人間の脳より６桁速く、現在の半導体メモリより６
桁大容量のメモリが得られる。However, when such elements are further miniaturized, physical problems such as generation of tunnel leakage current between the gate electrode and the semiconductor substrate, and further, the number of electrons per operation are reduced. Therefore, there is a fundamental problem that the statistical fluctuation of the number of electrons is increased and a malfunction easily occurs. For this reason, there has been proposed a single-electron tunnel element that operates by controlling individual electrons, rather than using the statistical properties of electrons as the basis of operation, as in the current LSI. The feature of this device is that as the device becomes finer, the operation becomes complete and the ultimate characteristics can be obtained. For example, by applying this to a memory, it is 6 orders of magnitude faster than the human brain and 6 times faster than the current semiconductor memory.
Large-capacity memory can be obtained.
【０００４】[0004]
【発明が解決しようとする課題】単一電子トンネル素子
は、クーロンブロッケード効果にその動作原理を置いて
いるが、この効果を引き出すには、トンネル接合が２個
以上直列に接続された多重トンネル接合が有用となり、
かつ、トンネル接合で挟まれた島の静電容量を小さくす
る必要がある。特に室温動作を考えると、島の静電容量
を１ａＦ以下にする必要があり、このような構造を作製
するためには、ｎｍレベルの構造形成技術が必要であ
る。The operation principle of the single-electron tunnel element is based on the Coulomb blockade effect. To bring out this effect, multiple tunnel junctions in which two or more tunnel junctions are connected in series are used. Becomes useful,
In addition, it is necessary to reduce the capacitance of the island sandwiched by the tunnel junctions. Considering room temperature operation in particular, it is necessary to set the island capacitance to 1 aF or less, and in order to manufacture such a structure, a nm level structure forming technique is necessary.
【０００５】現在、このような微細構造を作製する技術
は乏しく、自然構造を利用した素子がいくつか提案され
ている。例えば、"Appl. Phys. Lett., Vol.61, 1992,
p3145"に記載されているような原子層ドーピングＧａＡ
ｓ細線の横にサイドゲートを設けた多重トンネル接合
や、"Proc. IEDM, 1993, p541"に記載されているような
極薄ポリシリコンをチャンネルとして用いた単一電子メ
モリが作製されている。At present, the technology for producing such a fine structure is scarce, and some devices utilizing a natural structure have been proposed. For example, "Appl. Phys. Lett., Vol.61, 1992,
atomic layer doping GaA as described in p3145 "
Multiple tunnel junctions with side gates beside the s-thin wires and single-electron memories using ultra-thin polysilicon as the channel as described in "Proc. IEDM, 1993, p541" have been produced.
【０００６】しかし、前者はＧａＡｓ細線中に存在す荷
電不純物のランダム配置を利用してトンネル接合を形成
し、また後者はポリシリコン中のグレインを島として利
用し、電子が流れ易い部分をチャンネルとしているた
め、どちらもその構造を制御性良く作製することが難し
く、作製される素子にもその特性にばらつきが現れてい
た。However, the former uses a random arrangement of charged impurities existing in a GaAs thin wire to form a tunnel junction, and the latter uses grains in polysilicon as islands, and a portion where electrons easily flow is used as a channel. Therefore, it is difficult to manufacture the structure with good controllability, and the characteristics of the manufactured devices also vary.
【０００７】本発明は、上記の従来技術の課題を解決
し、その構造を制御することの可能な多重トンネル接合
の製造方法を提供することを目的とする。An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a method of manufacturing a multiple tunnel junction whose structure can be controlled.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明の多重トンネル接合の製造方法は、電気絶縁
性基板上に、金属あるいは半導体で形成された高さ１ｎ
ｍ以上、１０ｎｍ以下、幅１ｎｍ以上１００ｎｍ以下の
細線を作製し、少なくとも酸素あるいは水蒸気を有する
雰囲気中で、前記細線表面に導電性探針を接近あるいは
接触させ、前記細線と前記導電性探針間に電圧を印加す
ることにより少なくとも前記細線の表面に局所的に前記
細線の構成材料の酸化物を形成することを特徴とする。In order to achieve the above object, a method of manufacturing a multiple tunnel junction according to the present invention is provided with a height of 1 n formed of a metal or a semiconductor on an electrically insulating substrate.
A fine wire having a width of 1 m or more and 10 nm or less and a width of 1 nm or more and 100 nm or less is produced, and a conductive probe is brought close to or in contact with the surface of the thin wire in an atmosphere containing at least oxygen or water vapor, and the thin wire and the conductive probe are separated from each other. An oxide of the constituent material of the thin wire is locally formed at least on the surface of the thin wire by applying a voltage to the thin wire.
【０００９】前記構成において、局所的に酸化物が形成
された細線近傍に、電極を作製することが好ましい。In the above structure, it is preferable that the electrode is formed in the vicinity of the fine line where the oxide is locally formed.
【００１０】また、導電性探針側が相対的に負電圧にな
るように電圧を印加することが好ましい。Further, it is preferable to apply the voltage so that the conductive probe side has a relatively negative voltage.
【００１１】さらに、酸化物が、細線の表面から電気絶
縁性基板の表面の深さまで形成されていることが好まし
い。Further, it is preferable that the oxide is formed from the surface of the fine wire to the depth of the surface of the electrically insulating substrate.
【００１２】また、酸化物の最も薄い部分の長さが５ｎ
ｍ以下であることが好ましい。さらに、金属あるいは半
導体がＳｉ、Ｇｅ，ＧａＡｓ、Ｔｉ、Ｔａ、Ａｌまたは
ランタナイド元素から選ばれた少なくとも１種の金属あ
るいは半導体であることが好ましい。The length of the thinnest portion of the oxide is 5n.
m or less. Further, the metal or semiconductor is preferably at least one metal or semiconductor selected from Si, Ge, GaAs, Ti, Ta, Al or lanthanide elements.
【００１３】また、局所的に酸化物が形成された細線を
作製後、前記細線を熱処理することが好ましい。Further, it is preferable to heat-treat the thin wire after producing the thin wire in which an oxide is locally formed.
【００１４】[0014]
【作用】本発明の製造方法によれば、走査トンネル顕微
鏡（ＳＴＭ）や原子間力顕微鏡（ＡＦＭ）を利用して、
構造の制御性が良く多重トンネル接合を作製することが
できる。即ち、金属あるいは半導体で形成された高さ１
ｎｍ以上、１０ｎｍ以下、幅１ｎｍ以上１００ｎｍ以下
の細線を、ＳＴＭやＡＦＭの導電性探針を用いて局所的
に酸化することができるので、前記導電性探針を操作す
ることによって、多重トンネル接合を制御性良く作製で
きる。According to the manufacturing method of the present invention, a scanning tunneling microscope (STM) or an atomic force microscope (AFM) is used,
The structure has good controllability, and a multiple tunnel junction can be manufactured. That is, height 1 made of metal or semiconductor
Since a thin wire having a width of 1 nm or more and 10 nm or less and a width of 1 nm or more and 100 nm or less can be locally oxidized by using a conductive probe of STM or AFM, a multi-tunnel junction can be obtained by operating the conductive probe. Can be manufactured with good controllability.
【００１５】また、局所的に酸化物が形成された細線近
傍に、電極を作製することで、金属あるいは半導体を完
全に切り離さなくても、前記電極に印加する電圧により
ポテンシャル障壁を制御することで、多重トンネル接合
が形成される。Further, by forming an electrode in the vicinity of a thin line where an oxide is locally formed, the potential barrier can be controlled by the voltage applied to the electrode without completely separating the metal or semiconductor. , Multiple tunnel junctions are formed.
【００１６】さらに、導電性探針側が相対的に負電圧に
なるように電圧を印加することによって、陽極酸化を利
用して酸化物を作製できる。Further, by applying a voltage so that the conductive probe side has a relatively negative voltage, an oxide can be produced by utilizing anodic oxidation.
【００１７】また、酸化物を細線表面から電気絶縁性基
板表面の深さまで形成すれば、安定した構造の多重トン
ネル接合が形成される。When the oxide is formed from the surface of the thin wire to the depth of the surface of the electrically insulating substrate, a multiple tunnel junction having a stable structure is formed.
【００１８】さらに、５ｎｍ以下の間隔で切り離すこと
により、低電圧動作が可能となる。また、Ｓｉ、Ｇｅ、
ＧａＡｓ、Ｔｉ、Ｔａ、Ａｌまたはランタナイド元素か
ら選ばれた少なくとも１種の金属あるいは半導体で細線
を作製することで、比較的低電圧で安定な酸化物を形成
することが可能になる。Further, by separating at intervals of 5 nm or less, low voltage operation becomes possible. In addition, Si, Ge,
By forming a thin wire with at least one metal or semiconductor selected from GaAs, Ti, Ta, Al, or lanthanide elements, it becomes possible to form a stable oxide at a relatively low voltage.
【００１９】さらに、細線を熱処理することにより、細
線中の金属あるいは半導体の結晶性が向上するため、所
望の優れた特性のトンネル接合を実現できる。さらに、
酸素あるいは水蒸気中で熱処理することによ、細線に形
成された酸化物の品質や大きさを制御でき、特性の優れ
た接合を形成できる。Further, by heat-treating the thin wire, the crystallinity of the metal or semiconductor in the thin wire is improved, so that a desired tunnel junction having excellent characteristics can be realized. further,
By performing heat treatment in oxygen or water vapor, the quality and size of the oxide formed in the thin wire can be controlled, and a bond with excellent characteristics can be formed.
【００２０】[0020]
【実施例】以下に本発明の多重トンネル接合の製造方法
について説明する。EXAMPLE A method of manufacturing a multiple tunnel junction according to the present invention will be described below.
【００２１】図１は、本発明の実施例における多重トン
ネル接合の製造方法を示したものである。FIG. 1 shows a method of manufacturing a multiple tunnel junction according to an embodiment of the present invention.
【００２２】まずＳｉ酸化膜１表面に形成された厚さ５
ｎｍのＳｉ膜を電子線露光法を用いて、幅５０ｎｍ、長
さ０．５μｍの細線２に加工する。次に作製した細線２
の両端にＡｌ電極３を作製した後、大気中で、ＡＦＭの
導電性探針４を細線２のトンネル障壁を形成したい部分
に接触させる。なお、この時ＡＦＭの導電性探針４は、
カンチレバーと一体化したＳｉＮ探針表面に、５００Å
の金を蒸着したものを用いた。さらに、導電性探針４と
細線２間に探針側が負となるように１０Ｖの電圧を印加
しながら、導電性探針４を５μｍ／秒の速度で、細線２
を横切るように走査する。上記のようにして走査を行な
うと、細線２にはＳｉ酸化膜１表面まで到達する酸化物
５が作製され、これにより完全に絶縁分離を行なうこと
が可能となる。上記の酸化膜は陽極酸化により形成され
ていると考えられるため、上記のように負電圧を印加す
るのが望ましい。作製された酸化物５は、Ｓｉ酸化膜１
表面で一番薄くなり、幅１ｎｍ程度である。このように
本実施例では最も薄い部分の幅は１ｎｍであるが、トン
ネル接合を実現するためには、５ｎｍ以下でなければな
らない。次に導電性探針４を１０ｎｍ離れた位置に移動
し、再び同じ操作により細線２を酸化し、この操作によ
り、Ｓｉで形成された島６を形成し多重トンネル接合を
作製する。First, the thickness 5 formed on the surface of the Si oxide film 1
The Si film having a thickness of 50 nm is processed into a fine wire 2 having a width of 50 nm and a length of 0.5 μm by using an electron beam exposure method. Next thin wire 2
After the Al electrodes 3 are formed on both ends of the wire, the conductive probe 4 of the AFM is brought into contact with the portion of the thin wire 2 where the tunnel barrier is to be formed in the atmosphere. At this time, the conductive probe 4 of the AFM is
500 Å on the surface of the SiN probe integrated with the cantilever
The thing which vapor-deposited gold of was used. Further, while applying a voltage of 10 V between the conductive probe 4 and the thin wire 2 so that the probe side becomes negative, the conductive probe 4 is applied at a speed of 5 μm / sec.
Scan across. When the scanning is performed as described above, the oxide 5 reaching the surface of the Si oxide film 1 is formed in the thin line 2, and thus it is possible to completely perform the insulation separation. Since it is considered that the above oxide film is formed by anodic oxidation, it is desirable to apply a negative voltage as described above. The produced oxide 5 is the Si oxide film 1.
It is the thinnest on the surface and has a width of about 1 nm. As described above, the width of the thinnest portion is 1 nm in this embodiment, but it must be 5 nm or less in order to realize the tunnel junction. Next, the conductive probe 4 is moved to a position separated by 10 nm, the thin wire 2 is oxidized again by the same operation, and the island 6 formed of Si is formed by this operation to form a multiple tunnel junction.
【００２３】作製した多重トンネル接合の両端のＡｌ電
極をそれぞれソース電極、ドレイン電極とし、さらに、
多重トンネル接合表面に絶縁層を成膜し、その表面にＡ
ｌゲート電極を設けることにより、単一電子トンネル素
子を作製し、その特性を測定した。The Al electrodes on both ends of the produced multiple tunnel junction are used as a source electrode and a drain electrode, respectively.
An insulating layer is formed on the surface of the multiple tunnel junction, and A is formed on the surface.
A single-electron tunneling device was prepared by providing a 1-gate electrode, and its characteristics were measured.
【００２４】図２は、上記のように作成された単一電子
トンネル素子のソース電極とドレイン電極間に電圧（ド
レイン電圧）を印加した時の電圧−電流特性を示したも
のである。流れる電流（ドレイン電流）はドレイン電圧
の増加に伴って、階段状に増加することが観測された。
これは、クーロンブロッケード効果により電子が１個づ
つトンネル接合を移動した結果であると考えられる。FIG. 2 shows the voltage-current characteristics when a voltage (drain voltage) is applied between the source electrode and the drain electrode of the single electron tunnel element manufactured as described above. It was observed that the flowing current (drain current) increased stepwise as the drain voltage increased.
It is considered that this is a result of the electrons moving in the tunnel junction one by one due to the Coulomb blockade effect.
【００２５】さらに、ゲート電極に電圧を印加した時の
ドレイン電流を測定した結果を図３に示す。ドレイン電
流は、ゲート電圧によって周期的に変化し、ゲート電極
を用いてドレイン電流を制御することが可能であった。Further, FIG. 3 shows the result of measuring the drain current when a voltage is applied to the gate electrode. The drain current changed periodically with the gate voltage, and it was possible to control the drain current using the gate electrode.
【００２６】上記の実施例では、探針を用いて酸化した
酸化物によって、Ｓｉの島を完全に切り離した構造の多
重トンネル接合を作製したが、深さ方向に対して途中ま
で酸化させた構造により、さらに小さな島を有する多重
トンネル接合を作製することができる。この時の多重ト
ンネル接合の構成を図４に示す。図４に示すように、絶
縁性基板７上に両端にｎ型Ｓｉ電極８を有する厚さ５ｎ
ｍのｐ型Ｓｉ細線９を形成後、ＡＦＭの導電性探針を細
線９表面に接触し、導電性探針に−５Ｖの電圧を印加し
た状態で、導電性探針を５μｍ／秒の速度で、細線９を
横切るように走査しｐ型Ｓｉ細線９を酸化した。作製さ
れた酸化物１０は、深さ約３ｎｍまで達している。前記
操作を５ｎｍ間隔で行った。その後、細線９表面にＳｉ
Ｏ2絶縁層１１を成膜後、Ａｌゲート電極１２を作製し
た。このゲート電極１２に正電圧を印加し、電界効果に
より細線内部に形成される反転層を制御することによ
り、酸化物１０の薄い部分の下部に形成される反転層を
島とした等間隔の島状のチャンネルが形成され、多重ト
ンネル接合を形成することができる。In the above-mentioned embodiment, a multi-tunnel junction having a structure in which Si islands are completely separated by an oxide that has been oxidized using a probe was manufactured. Thus, a multiple tunnel junction having smaller islands can be manufactured. The structure of the multiple tunnel junction at this time is shown in FIG. As shown in FIG. 4, an insulating substrate 7 having n-type Si electrodes 8 at both ends has a thickness of 5 n.
After forming the p-type Si thin wire 9 of m, the conductive probe of the AFM was brought into contact with the surface of the thin wire 9, and a voltage of -5 V was applied to the conductive probe, and the conductive probe was moved at a speed of 5 μm / sec. Then, the p-type Si thin wire 9 was oxidized by scanning so as to cross the thin wire 9. The produced oxide 10 reaches a depth of about 3 nm. The above operation was performed at 5 nm intervals. After that, on the surface of the thin wire 9, Si
After forming the O 2 insulating layer 11, an Al gate electrode 12 was produced. By applying a positive voltage to the gate electrode 12 and controlling the inversion layer formed inside the thin wire by the electric field effect, islands at equal intervals with the inversion layer formed under the thin portion of the oxide 10 as islands. Channels are formed and multiple tunnel junctions can be formed.
【００２７】なお、ｎ型Ｓｉ細線を用いた場合は、ゲー
ト電極に負電圧を印加することで、多重トンネル接合を
形成できた。When an n-type Si thin wire was used, a multiple tunnel junction could be formed by applying a negative voltage to the gate electrode.
【００２８】また、細線を酸化する場合、必ずしも探針
を接触させる必要はない。例えばＳＴＭを用いた場合
は、探針を細線表面に接近させトンネル電流を用いて酸
化させることができた。Further, when oxidizing the fine wire, it is not always necessary to bring the probe into contact. For example, in the case of using STM, it was possible to bring the probe close to the surface of the thin wire and oxidize it using a tunnel current.
【００２９】また、細線材料はＳｉに限られるものでは
なく、Ｇｅ，ＧａＡｓ，Ｔｉ、Ｔａ，Ａｌ、ランタナイ
ド元素など探針と細線間に電圧を印加することにより酸
化される半導体あるいは金属を用いることで多重トンネ
ル接合を形成できた。The fine wire material is not limited to Si, but a semiconductor or metal such as Ge, GaAs, Ti, Ta, Al, or a lanthanide element which is oxidized by applying a voltage between the probe and the fine wire is used. It was possible to form multiple tunnel junctions.
【００３０】さらに、これらの多重トンネル接合は、熱
処理を行なうことにより素子の特性を向上することがで
きた。この熱処理は用いた金属あるいは半導体材料の融
点の５分の１から５分の３の間の温度で行なうのが適切
であった。熱処理により、島部分の材料の歪や欠陥が除
去されるため、特性が向上したものと考えられる。Further, these multiple tunnel junctions were able to improve the characteristics of the device by heat treatment. This heat treatment was suitably performed at a temperature between 1/5 and 3/5 of the melting point of the metal or semiconductor material used. It is considered that the characteristics are improved because the heat treatment removes strain and defects in the material of the island portion.
【００３１】また、酸素あるいは水蒸気中で熱処理する
ことにより酸化物の厚さや幅を増大させることができ、
探針を用いた酸化では制御が困難な微妙な制御が可能と
なり、特性の優れた多重トンネル接合を形成することが
できた。The thickness and width of the oxide can be increased by heat treatment in oxygen or steam,
Oxidation using a probe enabled delicate control, which was difficult to control, and formed a multiple tunnel junction with excellent characteristics.
【００３２】[0032]
【発明の効果】以上説明したように、本発明によれば、
島の大きさやトンネル障壁の厚さを均一に制御した多重
トンネル接合が得られ、その特性を制御した単一電子ト
ンネル素子を再現性よく製造することができる。この単
一電子トンネル素子は、電極構成を変えることで、トラ
ンジスタやメモリとして機能し、アナログ回路あるいは
デジタル回路に応用することができる。As described above, according to the present invention,
It is possible to obtain a multi-tunnel junction in which the size of the island and the thickness of the tunnel barrier are uniformly controlled, and it is possible to reproducibly manufacture a single electron tunnel device in which the characteristics are controlled. This single electron tunnel element functions as a transistor or a memory by changing the electrode configuration, and can be applied to an analog circuit or a digital circuit.
【図１】本発明の実施例における多重トンネル接合の製
造工程図FIG. 1 is a manufacturing process diagram of a multiple tunnel junction according to an embodiment of the present invention.
【図２】本発明の実施例における多重トンネル接合のド
レイン電圧−ドレイン電流特性を示す図FIG. 2 is a diagram showing drain voltage-drain current characteristics of a multiple tunnel junction according to an example of the present invention.
【図３】本発明の実施例における多重トンネル接合のゲ
ート電圧−ドレイン電流特性を示す図FIG. 3 is a diagram showing gate voltage-drain current characteristics of a multiple tunnel junction in an example of the present invention.
【図４】本発明の実施例における多重トンネル接合の概
略断面図FIG. 4 is a schematic sectional view of a multiple tunnel junction according to an embodiment of the present invention.
１ Ｓｉ酸化膜 ２ 細線 ３ Ａｌ電極 ４ ＡＦＭ導電性探針 ５ 酸化物 ６ 島 ７ 絶縁性基板 ８ ｎ型Ｓｉ電極 ９ ｐ型Ｓｉ細線 １０ 酸化物 １１ ＳｉＯ2絶縁層 １２ Ａｌゲート電極1 Si oxide film 2 thin wire 3 Al electrode 4 AFM conductive probe 5 oxide 6 island 7 insulating substrate 8 n-type Si electrode 9 p-type Si thin wire 10 oxide 11 SiO 2 insulating layer 12 Al gate electrode
Claims (6)
で形成された高さが１ｎｍ以上１０ｎｍ以下、幅が１ｎ
ｍ以上１００ｎｍ以下の細線を作製する工程と、前記細
線を少なくとも酸素あるいは水蒸気を有する雰囲気中で
前記細線表面に導電性探針を接近あるいは接触させ、前
記細線と前記導電性探針間に電圧を印加することにより
少なくとも前記細線の表面に局所的に前記細線の構成材
料の酸化物を形成する工程とを有する多重トンネル接合
の製造方法。1. A height of 1 nm or more and 10 nm or less and a width of 1 n formed of a metal or a semiconductor on an electrically insulating substrate.
a step of producing a fine wire of m or more and 100 nm or less, and a conductive probe is brought close to or in contact with the surface of the fine wire in an atmosphere containing at least oxygen or water vapor, and a voltage is applied between the fine wire and the conductive probe. And a step of locally forming an oxide of a constituent material of the thin wire on at least the surface of the thin wire by applying the method.
に電圧を印加して酸化物を形成することを特徴とする請
求項１記載の多重トンネル接合の製造方法。2. The method of manufacturing a multiple tunnel junction according to claim 1, wherein the oxide is formed by applying a voltage so that the conductive probe side has a relatively negative voltage.
表面の深さまで形成されていることを特徴とする請求項
１記載の多重トンネル接合の製造方法。3. The method of manufacturing a multiple tunnel junction according to claim 1, wherein the oxide is formed from the surface of the thin wire to the depth of the surface of the electrically insulating substrate.
であることを特徴とする請求項３記載の多重トンネル接
合の製造方法。4. The method for manufacturing a multiple tunnel junction according to claim 3, wherein the thinnest portion of the oxide has a length of 5 nm or less.
ｉ、Ｔａ、Ａｌまたはランタナイド元素から選ばれた少
なくとも１種の金属あるいは半導体であることを特徴と
する請求項１記載の多重トンネル接合の製造方法。5. The material of the thin wire is Si, Ge, GaAs, T
2. The method for manufacturing a multiple tunnel junction according to claim 1, wherein the method is at least one metal or semiconductor selected from i, Ta, Al or lanthanide elements.
後、前記細線を熱処理することを特徴とする請求項１記
載の多重トンネル接合の製造方法。6. The method for manufacturing a multiple tunnel junction according to claim 1, wherein the thin wire is heat-treated after the thin wire in which an oxide is locally formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7110423A JPH08306934A (en) | 1995-05-09 | 1995-05-09 | Manufacture of multitunnel junction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7110423A JPH08306934A (en) | 1995-05-09 | 1995-05-09 | Manufacture of multitunnel junction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08306934A true JPH08306934A (en) | 1996-11-22 |
Family
ID=14535389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7110423A Pending JPH08306934A (en) | 1995-05-09 | 1995-05-09 | Manufacture of multitunnel junction |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08306934A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007274005A (en) * | 2007-06-05 | 2007-10-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| CN102313625A (en) * | 2011-05-27 | 2012-01-11 | 北京大学 | Pirani vacuum gauge of carbon nanotube and vacuum degree detection method thereof |
-
1995
- 1995-05-09 JP JP7110423A patent/JPH08306934A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007274005A (en) * | 2007-06-05 | 2007-10-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| CN102313625A (en) * | 2011-05-27 | 2012-01-11 | 北京大学 | Pirani vacuum gauge of carbon nanotube and vacuum degree detection method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6310376B1 (en) | Semiconductor storage device capable of improving controllability of density and size of floating gate | |
| US7939398B2 (en) | Method to manufacture silicon quantum islands and single-electron devices | |
| JP2007281489A (en) | Electrostatically controlled tunneling transistor | |
| JP4026191B2 (en) | Method for forming silicon single crystal particles and method for manufacturing flash memory cell | |
| US6010934A (en) | Method of making nanometer Si islands for single electron transistors | |
| JP3761319B2 (en) | Manufacturing method of semiconductor device | |
| KR100444270B1 (en) | Method for manufacturing semiconductor device with negative differential conductance or transconductance | |
| KR100327496B1 (en) | Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof | |
| US5972744A (en) | Quantum effect device, method of manufacturing the same | |
| KR100434534B1 (en) | Single Electronic Transistor Using Schottky Tunnel Barrier and Manufacturing Method Thereof | |
| US20020088969A1 (en) | Single electron transistor using porous silicon and manufacturing method thereof | |
| US6204517B1 (en) | Single electron transistor memory array | |
| JPH08306934A (en) | Manufacture of multitunnel junction | |
| KR100558287B1 (en) | A single electron device, a manufacturing method thereof and a manufacturing method for simultaneously forming a single electron device and a MOS transistor | |
| JPH09191104A (en) | Single electronic element | |
| JP2000164592A (en) | Stacked or composite gate dielectric incorporating nitrogen at the interface | |
| JP2000164735A (en) | Semiconductor device and manufacture thereof | |
| JP2904095B2 (en) | Method of manufacturing single electronic device | |
| JP4309869B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2924699B2 (en) | Single electronic device and method of manufacturing the same | |
| KR100442815B1 (en) | Single electron transistor formed by porous silicon and fabricating method thereof | |
| JP3329627B2 (en) | Semiconductor element | |
| JPH06302806A (en) | Single-electron transistor | |
| JP2007306022A (en) | Silicon thin film, silicon monocrystal particle assemblage, semiconductor device and flash memory cell | |
| KR20000025200A (en) | Single electron transistor and method for fabricating the same |