JPH08297588A - Double collator - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a double collation device for detecting an abnormality of a bus in a duplicated device, by detecting a bus protocol and a traveling signal group, an abnormal state of the duplicated device can be detected. The purpose is to do. [Structure] The accumulated data assembling units 5 and 6 assemble the data of the respective buses and the information of the communication control signal group into a predetermined format, the accumulated memories 7 and 8 accumulate the assembled information, and the collating unit 3 At, the state of each bus is collated, and when they do not coincide, a collation error is detected. Then, the timing control unit 4 controls the start of the collation in the collating unit and causes the storage memory to store the information when the collation does not match. The fault information read control unit 9 outputs the bus state at the time of abnormality by controlling the reading of the information stored in the storage memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double collation device for detecting an abnormality of a bus in a duplexer, and more particularly, to detect an abnormal state of the duplexer by collating a bus protocol and a traveling signal group. The present invention relates to a double collation device configured to do so.

In a system using a control device represented by a processor, a system for ensuring the reliability of the device is adopted by constructing a duplication device with the same components.

The double collating device used to detect an abnormal state of the bus in the duplexer is not only for detecting and notifying the inconsistent state of the operation but also for collating the bus protocol and the traveling signal group. Therefore, it is required that the abnormality can be detected more reliably.

[0004]

2. Description of the Related Art FIG. 10 shows an example of a conventional double collation device. In the figure, 101 and 102 are devices, and 103 and 104 are processors (M
PU), 105 and 106 are components of respective devices, 107 and 108 are buses of respective devices, and 109
Is a double collation unit, and is composed of an exclusive OR (EX-OR) circuit. The double collation unit 109 is provided for each of the buses 107 and 108 of the duplicated devices 101 and 102.
When the two buses are connected to each other and the states of both buses are compared with each other and a collation error detection signal is output when they do not coincide with each other, an alarm is generated to detect an inconsistency state of the operations of both devices.

Generally, a device for ensuring high reliability by adopting such a duplex configuration is not a device for serially communicating a continuous amount, but is represented by a processor or the like. Often it is a controller.

The control device composed of a processor is
Most are operated by large-scale software. Therefore, when a failure such as a program runaway occurs, the restoration process differs depending on the program failure occurrence location and the failure occurrence status. Therefore, the function of reproducing the failure occurrence status is important. In order to classify program failures, intermittent failures due to hardware noise, and permanent failures due to specific causes, it is important to have log information when failures occur as a countermeasure against failures. .

On the other hand, the conventional double collating device in the duplicating device merely detects and informs the operation inconsistency state, and collates the bus protocol and the traveling signal group to detect an abnormality. Since no system is adopted, it is insufficient as a double collating device for a duplexing device including a control device represented by a processor or the like.

The present invention is intended to solve the problems of the prior art as described above, and in the double collating device for the duplexing device, by holding the bus information,
It is possible to identify the bus state when a failure occurs, improve reliability by duplicating the matching device, and eliminate the effect of delay characteristics peculiar to the device by absorbing the bus phase difference to improve the reliability of the matching system. An object of the present invention is to provide a double collation device that can be improved.

[0008]

[Means for Solving the Problems]

(1) In a redundant device composed of the same component, by monitoring the protocol and running signal group on each bus that connects the components inside each device and realizes the communication between the components, this duplication In a double collation device for detecting an abnormal state of the device, storage data assembling units 5 and 6 for assembling data of each bus and information of a communication control signal group into a predetermined format, and a storage memory 7 for storing the assembled information. , 8 and the collating unit 3 for collating the states of the respective buses to detect a collation error when they do not coincide with each other, and controlling collation start in the collating unit, and timing for accumulating information in the accumulation memory when collation does not coincide. Failure information reading for controlling reading of information stored in the storage unit and the control unit 4 And a control unit 9.

(2) In the case of (1), the timing control section and the collation section are duplicated and provided.

(3) In the case of (2), one of both collating units detects a collation match, and the other detects a collation non-coincidence. To detect.

(4) In the case of (1), the timing control unit detects the phase difference between the timings of the buses and instructs the collation unit to start the collation according to this phase difference. To provide.

(5) In the case of (1), the timing control section is provided with bus delay sections 33 and 34 for setting the phase difference according to the external setting at the timing of each bus, corresponding to each bus. .

(6) In the case of (1), in the timing control unit, the bus delay unit 37 for setting the phase difference according to the external setting at the timing of each bus corresponds to one of the selected buses. So that it can be inserted.

(7) By monitoring the protocol and running signal group on each bus in the duplexer constituted by the same component, which connects the components inside each device and realizes the communication between the components In the double collation device for detecting an abnormal state of the duplexer, the accumulated data assembling units 5 and 6 for assembling the data of each bus and the information of the communication control signal group into a predetermined format, and accumulating the assembled information. A collation unit 3 that collates the accumulated memories 7 and 8 with the accumulated information and detects a collation error when they do not match.
And a reception control unit 1 for accumulating information in a corresponding storage memory according to the timing of each bus.
0 and 11, and a collation control unit 12 that causes the collation unit to perform the collation operation when the data accumulation operation in both accumulation memories is completed.

(8) In the case of (1) or (7), the collating unit can permit or prohibit collation for each piece of information corresponding to a plurality of bus lines in each bus.

(9) In the case of (1) or (7), the collation unit detects a pulse level stack error of a pulse in the communication control signal group, and a signal sequence in the communication control signal group. A status detection unit 22 for detecting an error is provided, and at the same time as generation of the verification timing signal in the verification unit, an abnormal operation protocol of the bus control signal can be simultaneously detected.

In the cases of (10) and (7), a plurality of collating units 3 _{1 to} 3 _n for detecting inconsistency corresponding to the information of the plurality of bus lines stored in both storage memories 7 and 8, and An individual error display unit 41 that displays individual errors in a plurality of bus lines by detecting a mismatch in any of the plurality of matching units, and an error aggregation unit that aggregates the mismatch detection results of the plurality of matching units and detects a matching error. And 42.

[0018]

[Action]

(1) The collation unit 3 collates the states of the buses, outputs a collation error detection signal when they do not match, and outputs the data of each bus and the information of the communication control signal group assembled in a predetermined format. The data is stored in the storage memories 7 and 8 and the stored information is read out to the bus according to the access.

Therefore, when an abnormal state of the bus data and the bus communication control signal is detected, the abnormal state can be notified and the bus communication state at the time of detection can be read out on the bus. You can know the communication status.

(2) At this time, by providing the timing control sections 4 _1, 4 ₂ and the collating sections 3 _1, 3 ₂ in a duplicated manner, the reliability of the collating function can be improved and the collating section itself can be abnormal. Can be monitored.

(3) Collation matching is detected in one of the duplicated collating units, and collation inconsistency is detected in the other collating unit, and an abnormality in the collating unit is detected by matching the collation results of both collating units. The reliability of the matching operation can be improved.

(4) The phase difference controller 27 is included in the timing controller.
Is provided, the phase difference between the timings of the buses is detected, and the matching operation in the matching unit is started according to this phase difference, whereby the reliability of the duplicated matching operation can be improved.

(5) In the timing control section, the bus delay sections 33 and 34 are provided for the respective buses, and the phase difference according to the external setting is set at the timing of the respective buses. The phase difference caused by the characteristics on the board can be absorbed and the matching operation can be performed correctly.

(6) In the timing control unit, the bus delay unit 37 can be inserted corresponding to any one of the selected buses, and the phase difference according to the external setting is set in the timing of the bus. Thus, it is possible to share a delay circuit for absorbing the phase difference of the buses and performing a correct matching operation.

(7) The data of each bus and the information of the communication control signal group are assembled into a predetermined format and stored in the storage memories 7 and 8. Upon completion of the accumulation operation of both accumulation memories, the collation unit 3 collates the accumulated information, and outputs a collation error detection signal when they do not coincide.

As described above, since the bus state is stored in the storage memory in advance before the collation, the collation can be correctly performed even when the bus timing deviation (phase difference) is large.

(8) The collation unit permits collation for each information corresponding to a plurality of bus lines in each bus,
Or, by making it possible to prohibit, simplifies the circuit configuration of the collating unit by collating with emphasis.
The matching time can be shortened.

(9) The verification timing in the verification unit is generated according to the bus protocol. The bus communication control signal group can be divided into control pulses and control flags (level signals).
It can be detected by performing a state transition that is not in a normal protocol. The collation timing of the double collating device is not a permanent collation, but bus information is collected and collated in a specific state of the bus protocol. Therefore, it can be said that the collation timing generation and the bus state monitoring are synonymous. That is,
When generating the collation timing in receiving the pulse signal of the bus, it is possible to detect the state of the bus to which the pulse signal is transmitted and the state in which the pulse signal is level-stacked. Similarly, in the level signal, the state before and after a certain specific level is used to determine whether or not the level is the state to be matched. Therefore, it is determined whether the state before and after the level is not defined in the bus protocol. Is possible. Therefore, it is possible to simultaneously regard the bus collation timing generation unit as the bus protocol abnormality detection unit and notify the abnormality when the abnormality occurs.

(10) A plurality of collating units are provided to detect inconsistencies corresponding to the information of a plurality of bus lines stored in both storage memories. In addition to displaying the individual errors in the bus lines and outputting the collation error detection signal by consolidating the mismatch detection results of multiple collation units, the output that identifies the location of the abnormality for each of the bus lines can be output. As well as occurring, an output in which a collation error is detected can be generated.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment (1) of the present invention and shows the basic configuration of a double collating device of the present invention. In the figure, 1 and 2 are a bus, 3 is a collating unit for collating bus states, 4 is a timing control unit for controlling the operation timing of each unit, 5 and 6 are stored data assembling units for assembling data into a predetermined format, 7 , 8 is a storage memory for storing the assembled data, 9 is a storage memory 7,
8 is a failure information read control unit that controls reading of the failure information accumulated in FIG.

The accumulated data assembling units 5 and 6 perform an operation of assembling the bus data (address, data) on the buses 1 and 2 and the state of the bus communication control signal group at the time of data communication into a fixed format, respectively. It is always performed according to the timing of.

The timing control unit 4 controls the start of the matching operation in the matching unit 3 by detecting the timing of the buses 1 and 2. The collation unit 3 compares and collates the states of the buses 1 and 2, and outputs a collation error detection signal to a dedicated communication line when they do not coincide with each other, thereby notifying a processor (not shown) of the bus abnormality and Is returned to the timing control unit 4.

When the timing control section 4 receives a bus transfer instruction signal from each bus, the timing control section 4 accumulates the data assembled by the accumulated data assembling sections 5 and 6 in the corresponding accumulation memories 7 and 8, respectively, and the accumulation operation. When is finished, the collating operation in the collating unit 3 is stopped.

The fault information read control unit 9 reads and holds the data stored in the storage memories 7 and 8 according to the read instruction from the bus, and outputs the data according to the access from the bus.

According to this embodiment, when an abnormal state of the bus data and the bus communication control signal is detected by checking the bus state, this is notified and all the bus communication states at the time of detection are stored, Since the data can be read out on the bus by the bus access to the device, it is possible to know the bus communication state at the time of failure occurrence.

FIG. 2 shows an embodiment (2) of the present invention, in which the timing of data storage is different from that of the configuration shown in FIG. In the figure,
The same parts as those in FIG.
Is a reception control unit for controlling the accumulation of data on the bus, and 12 is a collation control unit for controlling collation of the accumulated data.

The accumulated data assembling units 5 and 6 respectively assemble bus data (address, data) on the buses 1 and 2 and a state of a bus communication control signal group at the time of data communication into a fixed format. Reception control unit 1
0 and 11 accumulate the bus states assembled in a fixed format in the accumulated data assembling units 5 and 6 in the corresponding accumulation memories 7 and 8 in accordance with the timing of the buses 1 and 2.

When the collation control unit 12 knows the end of data storage in the storage memories 7 and 8 from the control timing of the reception control units 10 and 11 for the storage memories 7 and 8,
The collation of the accumulated data in both accumulation memories 7 and 8 in the collation unit 3 is started. The collation unit 3 outputs a collation error detection signal through a dedicated communication line when the comparison and collation results of the data stored in the two storage memories 7 and 8 do not match.

In the case of the configuration shown in FIG. 1, buses 1 and 2 are used.
If the timing deviation (phase difference) of is large, the collation unit may not be able to collate correctly.
In the case of the configuration shown in FIG. 2, since the bus state is stored in the storage memory in advance before the collation, the collation can be performed correctly even when the timing deviation (phase difference) between the buses 1 and 2 is large. it can.

FIG. 3 shows an embodiment (3) of the present invention, in which the timing control section and the collating section are duplicated in the configuration shown in FIG. In the figure, 3 _1, 3 ₂ are collating units, and 4 _1, 4 ₂ are timing control units.

The timing control unit 4 _1, 4 _2, at the timing of the bus 1 and bus 2 respectively, to control the matching operation of the matching unit. Further, the collating units 3 _1, 3 ₂ are respectively the bus 1 and the bus 2
By comparing and collating the states of (1) and (2) when they do not match, a collation error detection signal is output to a dedicated communication line to notify a bus abnormality to a processor or the like (not shown).

As described above, according to the configuration shown in FIG.
Since the timing control unit for performing the collation control and the collating unit for collating the bus state are duplicated, the reliability of the collating function can be improved and the abnormality of the collating unit itself can be monitored.

FIG. 4 shows an embodiment (4) of the present invention.
In the double collation device as shown in FIG.
And the collation unit that improves the reliability of the duplicated collation operation.
Shows the configuration of. In the figure, 15_1,…, 15_n
Is a match detection unit, 16_1,…, 16 _nIs a mismatch detection unit, 17
Is an AND circuit, 18 is an OR circuit, and 19 is a match detection circuit.
is there.

The coincidence detector 15 _1, ..., 15 _n is the bus comprising a plurality of bus lines, detects a match between data in each of the corresponding bus line, the AND circuit 17, coincide at all matching detector Is detected, output 1 is generated, for example. The mismatch detection units 16 _1, ..., 16 _n detect data mismatches on respective corresponding bus lines of a bus composed of a plurality of bus lines, and the OR circuit 18 does not detect mismatches on all the mismatch detection units. When
For example, output 0 is generated.

The output of the AND circuit 17 and the OR circuit 18 is 1
If 0, the collation result is normal, and if 01, a collation error is detected. Further, in the case of 00 and 11, it indicates an abnormality of the collation unit itself. When the match detection circuit 19 detects a match between the outputs of the AND circuit 17 and the OR circuit 18, the match detection circuit 19 outputs a signal indicating an abnormality in the collating unit.

In the embodiment (4), the collation match is detected on the one hand in the duplicated collation operation, and the collation mismatch is detected on the other hand. Therefore, the reliability of the duplicated collation operation is improved. You can

Further, as an embodiment (5) of the present invention, as a control function for the collating unit shown in FIG. 1, the collating unit permits and collates corresponding to signals of a plurality of bus lines of each bus. By providing the instruction signal for setting prohibition, the collation unit can individually select and set the collation target signal.

According to the embodiment (5), it is possible to select the signals of a plurality of bus lines according to the degree of importance and perform the collation. It is possible to simplify the circuit configuration of and reduce the matching time. Note that such a control function is shown in FIG.
It can also be applied to the case of the double collating device shown in FIG.

FIG. 5 shows an embodiment (6) of the present invention, in which the collating unit shown in FIG. 1 monitors each state during the bus access cycle to detect an abnormal protocol. The case where it has a function is shown. In the figure, 21 is a pulse detector for detecting the pulse state of the control signal group, and 22 is a status detector for detecting the status of the control signal group.

When the pulses are stacked at one level (generally high level), the pulse detection unit 21 detects an abnormal pulse state in the control signal group and generates an alarm signal (level stack error). When the sequence of signal level changes in the control signal group is not normal, the status detecting unit 22 detects a status error and generates an alarm signal (sequence error).

Pulse detector 21, status detector 22
Is a normal input, and when these alarm signals are not generated, a control pulse is generated to start the verification operation in the verification unit.

In the embodiment (6), in order to detect a protocol error such as a signal stack, the assertion / negation state of each signal and the signal state in the next cycle are predicted. Regardless of that, I have notified you of the abnormality, so check the normality of the matching operation,
The reliability can be improved. The configuration of such a collating unit is also applicable to the double collating device shown in FIG.

FIG. 6 shows an embodiment (7) of the present invention. In the timing control section shown in FIG.
The configuration is shown in which the phase difference of the clock cycle of the bus is detected, the phase difference at the start of the matching operation is held, and the matching unit is notified. In the figure, 25 is a lead amount detecting section for detecting a phase lead amount between both buses, 26 is a delay amount detecting section for detecting a phase delay amount between both buses, and 27 is a phase difference at the time of starting the matching operation. It is a phase difference control unit for controlling.

The lead amount detector 25 compares the phases of the buses 1 and 2 and detects the phase lead amount of one of the buses. The delay amount detector 26 compares the phases of the buses 1 and 2 and detects the phase delay amount of one of the buses. The phase difference control unit 27 calculates the phase difference between both buses in accordance with the verification start instruction from the timing control unit, holds the calculated phase difference, notifies the verification unit of the verification start, and According to the instruction, the amount of advance or the amount of delay of the phase difference between both buses at that time and the number of phase shift cycles are notified to the collating unit. When the number of phase shift cycles exceeds a predetermined value that makes the collation operation impossible in the collation unit, a timeout error is notified,
The verification operation is prohibited.

According to the embodiment (7), since the phase difference at the start of the collating operation can be held, the phase difference due to the characteristics on the circuit board can be absorbed and the collating operation can be performed correctly. Like

FIG. 7 shows an embodiment (8) of the present invention. In the timing control section shown in FIG.
A configuration is shown in which a phase difference between bus clock cycles is set to perform collation. In the figure, the same parts as those in FIG. 1 are indicated by the same numbers, 31 is a phase difference setting unit for setting the phase difference between both buses, and 32 is the timing delay amount of both buses according to the set phase difference. The delay amount control units 33 and 34 are bus delay units for delaying the timing of the buses 1 and 2.

By setting a known clock cycle phase difference between the buses 1 and 2 in the phase difference setting unit 31, the delay amount control unit 32 controls the delay amounts in the bus delay units 33 and 34. In the collation unit 3, the collation operation can be performed by the preset phase difference (including 0).

According to the embodiment (8), the phase difference during the matching operation can be set to a predetermined value by the external setting.

FIG. 8 shows an embodiment (9) of the present invention. In the timing control section shown in FIG.
When the phase difference between the bus clock cycles is set and the comparison is performed, the circuit is shared. In the figure, the same components as those in FIG. 7 are designated by the same reference numerals, 35 and 36 are selectors, and 37 is a bus delay unit for delaying the timing of the bus.

The delay amount control unit 32 controls the switching of the selectors 35 and 36 according to the advance or delay of the phase difference set by the phase difference setting unit 31, and selects either the bus 1 or the bus 2. The delay unit 37 is inserted and connected to the matching unit 3, and the delay amount in the bus delay unit 37 is adjusted according to the phase difference set in the phase difference setting unit 31.

In the configuration shown in FIG. 7, in order to set the phase difference of the clock cycle of the bus with respect to the matching unit 3,
Although the two bus delay units 33 and 34 are required, the configuration shown in FIG. 8 allows the bus delay unit 37 to be shared by providing the selectors 35 and 36.

FIG. 9 shows an embodiment (10) of the present invention, in which notification of an abnormal portion in a plurality of bus lines in the storage memory shown in FIG. It is something that can be done. In the figure, the same parts as those in FIG.
_1, ..., 3 _n are verification units provided corresponding to a plurality of bus lines, 41 is an individual error display unit for outputting a fault location notification corresponding to an abnormal location, and 42 is an error of each bus line. An error aggregating unit for aggregating and outputting a collation error detection signal.

The collating units 3 _1, ..., 3 _n are composed of the storage memories 7, 8
The outputs of the corresponding bus lines are compared and collated, and when a mismatch is detected, a detection signal is generated. Individual error display section 4
1 outputs a fault location notification indicating each abnormal location in accordance with the detection signal from each collation unit. Error aggregator 42
Generates a matching error detection signal by aggregating the detection signals of the matching units.

According to the embodiment (10), it is possible to generate an output for specifying a location where an abnormality has occurred for each of a plurality of bus lines forming a bus, and to generate an output for notifying the occurrence of an abnormality on the bus. You can

[0065]

As described above, according to the present invention, since the bus information is held in the double collation device for detecting the bus abnormality in the duplexer, the state of the device at the time of failure occurrence Can be specified. Further, since the collating device is duplicated, the reliability of the collating device and the collating operation can be improved. Further, by absorbing the phase difference of the timing between the buses, it is possible to improve the reliability at the time of checking the bus state.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment (1) of the present invention.

FIG. 2 is a diagram showing an embodiment (2) of the present invention.

FIG. 3 is a diagram showing an embodiment (3) of the present invention.

FIG. 4 is a diagram showing an embodiment (4) of the present invention.

FIG. 5 is a diagram showing an embodiment (6) of the present invention.

FIG. 6 is a diagram showing an embodiment (7) of the present invention.

FIG. 7 is a diagram showing an embodiment (8) of the present invention.

FIG. 8 is a diagram showing an embodiment (9) of the present invention.

FIG. 9 is a diagram showing an embodiment (10) of the present invention.

FIG. 10 is a diagram showing an example of a conventional double matching device.

[Explanation of symbols]

 1 bus 2 bus 3 collating unit 4 timing control unit 5 accumulated data assembling unit 6 accumulated data assembling unit 7 accumulated memory 8 accumulated memory 9 fault information read control unit 10 reception control unit 11 reception control unit 12 collation control unit 21 pulse detection unit 22 Status detection unit 25 Lead amount detection unit 26 Delay amount detection unit 27 Phase difference control unit 31 Phase difference setting unit 32 Delay amount control unit 33 Bus delay unit 34 Bus delay unit 37 Bus delay unit 41 Individual error display unit 42 Error aggregation unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Ohno 3-28-1 Joto, Oyama-shi, Tochigi Prefecture Fujitsu Digital Technology Limited (72) Inventor Takashi Arai 3-28-1 Joto, Oyama-shi, Tochigi Prefecture Within Fujitsu Digital Technology Co., Ltd. (72) Inventor Zhang ▲ Odd ▼ 3 28-1 Joto, Oyama City, Tochigi Prefecture Within Fujitsu Digital Technology Co., Ltd. Address Fujitsu Limited (72) Inventor Miyuki Imada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (10)

[Claims] 1. In a duplexer configured by the same component, by monitoring a protocol and a running signal group on respective buses which connect components inside each device and realize communication between the components, In a double collation device that detects an abnormal state of the duplexer, a stored data assembling unit that assembles data of each bus and information of a communication control signal group into a predetermined format,
A storage memory that stores the assembled information, a collation unit that collates the states of the respective buses to detect a collation error when they do not match, and a collation start in the collation unit is controlled. A double collation device comprising: a timing control section for accumulating information in the memory; and a failure information read control section for controlling reading of the information accumulated in the accumulation memory. 2. The double collation device according to claim 1, wherein the timing control unit and the collation unit are duplicated and provided. 3. The double collation device according to claim 2, wherein one of the both collating units detects a collation match.
On the other hand, the double collation device is characterized in that the collation mismatch is detected and the abnormality of the collation unit is detected by the coincidence of the collation results of both collation units. 4. A phase difference control unit is provided in the timing control unit, which detects a phase difference between the timings of the respective buses and instructs the start of matching in the matching unit according to the phase difference. The double collation device according to claim 1. 5. The bus delay unit for setting the phase difference according to an external setting at the timing of each bus in the timing control unit, corresponding to each bus. The described double collation device. 6. The timing control unit, wherein a bus delay unit for setting a phase difference according to an external setting at each bus timing can be inserted in correspondence with any one of the selected buses. Claim 1 characterized by the above-mentioned.
The double matching device described in. 7. In a duplexer configured by the same component, by monitoring a protocol and a running signal group on respective buses that connect components inside each device and realize communication between the components, In a double collation device that detects an abnormal state of the duplexer, a stored data assembling unit that assembles data of each bus and information of a communication control signal group into a predetermined format,
A storage memory that stores the assembled information, a collating unit that collates the stored information and detects a collation error when they do not match, and information in the storage memory that corresponds to the timing of each bus. A double collation device comprising: a reception control unit for accumulating and a collation control unit for performing a collating operation in the collating unit when the accumulation operation of data in both accumulation memories is completed. 8. The duplexer according to claim 1, wherein in the collating unit, collation can be permitted or prohibited for each information corresponding to a plurality of bus lines in each bus. Collator. 9. The collation unit includes a pulse detection unit that detects a level stack error of a pulse in the communication control signal group, and a status detection unit that detects a signal sequence error in the communication control signal group. ,
8. The double collation device according to claim 1, further comprising a function of monitoring a bus operation protocol. 10. The double collation device according to claim 7, wherein a plurality of collation units are provided for detecting inconsistencies in correspondence with the information of the plurality of bus lines stored in the two storage memories, respectively.
An individual error display unit that displays individual errors in a plurality of bus lines by detecting a mismatch in any of the plurality of matching units, and an error that aggregates the mismatch detection results of the plurality of matching units and detects the matching error A double collating device comprising an aggregating unit.