JPH0829488A - I/o pin electronics circuit - Google Patents

Abstract

PURPOSE:To provide an I/O pin electronics circuit which enables device tests, without wasting a comparator circuit, a comparison voltage generating circuit, a waveform shaping circuit and an applied voltage generating circuit and cutting in half the number of DUT measured simultaneously, in conducting, in addition to a conventional I/O common test, an IC separate test for such high-speed devices that an IC dead band becomes problematic. CONSTITUTION:Two drivers DR1, DR2 which have a common applied/terminal voltage generating circuit 10 and a common waveform shaping circuit 11 are provided. Either one of the driver DR1 or the driver DR2 is provided with a comparator CP which is combined with both a comparator circuit 12 and a comparison voltage generating circuit 13. The driver DR2 is subjected to DRE control and the driver DR1 is used at a terminal, so that an O/O common test can be conducted. Also, the driver DR1 is subjected to DRE control and the driver DR2 is used at the terminal of the comparator CP, so that an I/O separate test can be conducted.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an I / O common test and an I / O common test.
The present invention relates to an I / O pin electronic circuit that enables both the I / O separate test.

[0002]

2. Description of the Related Art In semiconductor test equipment, normal I / O
The pin electronics circuit is an I / O common pin having the functions of both a driver (DR) and a comparator (CP) as shown in FIG. The DR and CP and the device under test (DUT) have a propagation delay time T
It is connected with a cable. Write in Figure 5 (b),
The timing chart at the time of repeating a read-out operation is shown. D
The output data DR1 from R reaches the DUT end after the time T and becomes the write data W1. If the read operation continues, the read data R from the DUT
Reaches the CP edge after time T. Furthermore, in order to immediately perform the write operation after the end of the read operation, it is necessary to output the data DR2 from DR earlier by the time T than the write data W2 to the DUT. The data DR2 output from the DR also reaches the CP end without a time delay. Then, at the CP end, read data R from the DUT
Then, there occurs a time when the combined data DR2 output from its own DR is input. This combined time is twice as long as T, and during this period, the CP cannot make a correct comparison judgment. This range is called the I / O dead band, and DR
And the propagation delay time length T between the CP and the DUT.

When testing a high-speed device in which the above-mentioned I / O dead band becomes a problem, a route from DR to DUT and a route from DUT to CP are separately tested and shown in FIG. 6 (a). Such an I / O separate test is performed. As is clear from FIG. 6B, the output data DR1 and D of the read data R and DR from the DUT at the CP end.
R2 is never synthesized. Therefore, the CP can make a correct comparison determination. At the DR end, the output data DR
2 and the read data R from the DUT are combined into a waveform, but the collision of the traveling waves does not affect the other because they only pass each other, and the waveform from the DUT is terminated at the DR end.
It does not affect the P end.

A typical I / O pin electronics circuit is the I / O common pin. So, in Figure 7, DR and DUT
Shows the case where the I / O common pin is used for the I / O separate test in which the DUT and the CP are connected by another route. I
The / O common pin CH1 is used as DR and the I / O common pin CH2 is used as CP.

The I / O separate pin as shown in FIG. 8 is suitable for the I / O separate test, and DR and DU
I / O by connecting T, DUT and CP respectively
Separate test is possible.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As shown in FIG.
The I / O separate test using the / O common pin requires twice as many I / O common pins as compared to the case of using as a normal I / O common pin. Therefore, the number of DUTs that can be simultaneously measured is halved. Further, since CH1 is used as DR, the comparison circuit and comparison voltage generation circuit are wasted, and since CH2 is used as CP, the waveform shaping circuit and applied voltage generation circuit are wasted.

As shown in FIG. 8, in the I / O separate test using the I / O separate pin, no waste occurs in the comparison circuit, the comparison voltage generation circuit, the waveform shaping circuit, and the applied voltage generation circuit, but the I / O common pin is used. I can't test.

In the case of the I / O separate test, since the read cycle is terminated at both ends of the DR side and the CP side, the drive capability of the DUT is required accordingly. DU without drive capability
In T, the I / O separate test cannot be performed, and the I / O common test cannot be avoided. In addition, DR and CP are DUT 1
When testing pins, I / O separate test is I / O
The number of wires between the DUT and the main body of the semiconductor test device is larger than that in the common test. In case of multiple DUT,
An I / O common test may be required to avoid the complexity of wiring.

In addition to the conventional I / O common test, the present invention provides a comparison circuit, a comparison voltage generation circuit, and a waveform shaping circuit when performing an I / O separate test of a high-speed device in which an I / O dead band is a problem. An object of the present invention is to realize an I / O pin electronics circuit that enables device testing without wasting a circuit and an applied voltage generating circuit and reducing the number of simultaneously measured DUTs by half.

[0010]

In order to achieve the above object, in the present invention, a plurality of drivers, for example, two drivers DR1 and DR2 which share an applied / terminating voltage generation circuit and a waveform shaping circuit are provided. . Further, at least one of the plurality of drivers, for example, one of DR1 or DR2, is provided with a comparator configured with a comparison circuit and a comparison voltage generation circuit. The application / termination voltage generation circuit generates three types of voltages. Each voltage is fed through a switch circuit to two drivers, DR1 and DR2.
Is supplied to. Each switch circuit outputs PAT (pattern signal) and DRE (drive enable signal) output from the waveform shaping circuit, and CONT1a, CONT1b, CONT2a and CON in the driver control circuit.
It is controlled by each signal of T2b. The comparator is
It is connected to the output of either DR1 or DR2.

[0011]

With the I / O pin electronics circuit configured as described above, the I / O common test can be executed by setting the DR2 side to DRE control and terminating the DR1 side. Further, the I / O separate test can be executed by setting the DRE control on the DR1 side and terminating the CP on the DR2 side.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an I / O which is a bifurcation of DR according to the present invention.
A schematic block diagram of the pin electronics circuit is shown in FIG. 4, and a detailed block diagram thereof is shown in FIG. Two branched drivers D
R1 and DR2 have a waveform shaping circuit for one channel,
An application / termination voltage generation circuit is assigned, and one of them is connected with a comparison circuit and a CP having a comparison voltage generation circuit. Here, the function of the CP is the same as the conventional one. The waveform shaping circuit is a circuit that generates a driver pattern (PAT) for switching the DR high level / low level and a DRE (DRiver Enable) pattern for switching the DR on / off. When DR is on, PAT signal is output and D
When R is off, the VTT level is output to the driver,
Serves as a termination. As shown in FIG. 4, two-branch DR
Has a common PAT signal, DRE signal, applied voltages VIH and VIL, and termination voltage VTT, and a driver control circuit is provided so that only DR control can be performed independently by DR1 and DR2.

In the I / O common test shown in FIG. 2, CONT1a, CONT1b and CONT2b shown in FIG.
Then, by setting CONT2a to logic 1, the DR2 side becomes D
The RE control is performed and an output according to the PAT signal is generated. On the other hand, the DR1 side is in a termination state to prevent interference. As a result, the operation is similar to that of the conventional I / O common pin.

In the I / O separate test shown in FIG. 3, by setting CONT1b, CONT2a, and CONT2b in FIG. 4 to logic 0 and CONT1a to logic 1, the DR1 side is set to DRE control and an output according to the PAT signal is output. appear.
On the other hand, the DR2 side functions as the CP termination. In either case, the comparison circuit, the comparison voltage generation circuit, the waveform shaping circuit, and the applied voltage generation circuit are not wasted, and the number of simultaneous measurement is not reduced.

[0015]

Since the present invention is constructed as described above, it has the following effects. DR2 and CP allow conventional I / O common test. DR1 and CP allow I / O separate test. No circuits are wasted in both the I / O common test and the I / O separate test. Since the I / O separate test can be performed with one I / O pin electronics circuit, the number of simultaneously measured DUTs will not be reduced by half. Even in the I / O separate test, the number of wirings between the DR and CP and the DUT is increased as compared with the I / O common test, and the number of wirings between the DR and CP and the semiconductor test apparatus main body does not change. Therefore, in the case of a large number of DUTs, the wiring for the I / O separate test is almost the same as that for the I / O common test, and the complexity of the wiring can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an I / O pin electronics circuit of the present invention.

FIG. 2 shows the I / O pin electronics circuit of the present invention.
It is a circuit block diagram when performing an / O common test.

FIG. 3 shows the I / O pin electronics circuit of the present invention.
It is a circuit block diagram when performing an / O separate test.

FIG. 4 is a detailed block diagram and operation explanatory diagram of the I / O pin electronics circuit of the present invention.

FIG. 5 is a connection diagram and a timing diagram in the case of an I / O common test.

FIG. 6 is a connection diagram and a timing diagram in the case of an I / O separate test.

FIG. 7 is a block diagram of an I / O separate test using a conventional I / O common pin.

FIG. 8: I / O using a conventional I / O separate pin
It is a block diagram of a separate test.

[Explanation of symbols]

 10 Applied / Termination Voltage Generation Circuit 11 Waveform Shaping Circuit 12 Comparison Circuit 13 Comparison Voltage Generation Circuit 14 Termination Voltage Generation Circuit 15 Driver Control Circuit 16 DR1 17 DR2 18 CP 19 Switch Circuit 20 Switch Control Circuit

Claims (3)

[Claims] 1. A plurality of drivers sharing an application / termination voltage generation circuit (10) and a waveform shaping circuit (11) are provided, and at least one of the plurality of drivers is provided with a comparison circuit (12) and a comparison voltage generation circuit. An I / O pin electronics circuit provided with a comparator configured with a circuit (13) and comprising the above. 2. Two drivers, DR1 (16) and DR2, to which three kinds of voltages output from the application / termination voltage generation circuit (10) are supplied through a switch circuit (19).
(17) is provided, and the switch control for controlling each switch circuit (19) of the DR1 (16) and DR2 (17) by the signal from the waveform shaping circuit (11) and the signal from the driver control circuit (15). A circuit (20) is provided, a driver control circuit (15) for independently controlling the switch circuits (19) of the DR1 (16) and DR2 (17) is provided, and a comparator is provided at the output of the DR2 (17). An I / O pin electronics circuit having the above features. 3. The I / O pin electronics circuit according to claim 2, wherein a comparator is provided only on the output of DR1 (16).