JPH08293546A - Manufacturing method of multilayer wiring - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a connection technique for multilayer wiring with good step coverage. [Structure] A step of depositing a first wiring layer 14, a step of depositing a contact wiring layer on the first wiring layer 14, and a step of simultaneously etching the first wiring layer 14 and the contact wiring layer. A step of forming a pattern of the first wiring layer 14, a step of etching the contact wiring layer to form a contact portion 13 that electrically connects the first wiring layer 14 and the second wiring layer 16; The step of depositing the interlayer insulating film 11 on the substrate on which the first wiring layer 14 is patterned and the contact portion 13 is formed, and the tip surface of the contact portion 13 is substantially flush with the interlayer insulating film 11. Thus, the step of planarizing the interlayer insulating film 11 and the step of depositing the second wiring layer 16 on the interlayer insulating film 11 are included. Aluminum is used for the first wiring layer 14 and tungsten is used for the contact portion 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer wiring, and more particularly to a technique effective when applied to a multi-layer wiring connection for electrically connecting circuit elements formed on a semiconductor wafer.

[0002]

2. Description of the Related Art Today, for example, in semiconductor integrated circuit devices, the aspect ratio of wiring is remarkably increased due to the demand for finer wiring and higher current density accompanying higher integration and higher speed of the device. On the other hand, multi-layered wiring is an even more important technology because it substantially reduces the wiring area to achieve high device integration, shortens the average wiring length, and suppresses the delay in operating speed due to wiring resistance. Has become.

Under such circumstances, as a technique for electrically connecting two wiring layers in a laminated structure formed on a semiconductor wafer, for example, "LSI Handbook" (Showa 59, published by Ohmsha Co., Ltd.) (Issued on November 30), P280 to P281, as described in P280 to P281, a fine contact hole is formed in the insulating layer formed on the lower wiring layer, and the insulating layer is formed by filling the contact hole. A technique is known in which an upper wiring layer is formed on top of the above to make contact with the lower wiring layer.

[0004]

However, according to such a technique, the step coverage (step coverage) of the contact hole is deteriorated due to the increase in aspect ratio of the contact hole which is proportional to the high aspect ratio of the wiring. There's a problem. Deterioration of step coverage leads to disconnection of wiring and increase of resistance, which directly affects the reliability of the product. It may be possible to improve the step coverage by tapering the contact hole, but it is against the trend of device miniaturization and is difficult to adopt.

Further, as described above, when the aspect ratio of the wiring is remarkably increased, the surface step height is further increased.
Although complicated, it is necessary to form contact holes having different depths because the contact holes must be formed so as to reach the lower wiring layer. Since the etching rate of the insulating layer forming the contact hole is uniform in every surface area, in such a case, the insulating layer is etched according to the deepest contact hole. This is not preferable because in the portion where the shallower contact hole is formed, it becomes over-etching and the lower wiring layer is also etched.

By the way, the flattening of the insulating film has a great influence on the quality of lithography and etching, and is a very important technical problem. Therefore, even in the case of multilayer wiring, if the step difference on the surface due to this can be mitigated, it becomes possible to manufacture a higher quality product.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-layer wiring connection technique with good step coverage.

Another object of the present invention is to provide a technique for connecting multi-layered wiring without etching the wiring layer.

Still another object of the present invention is to provide a connecting technique for a multi-layer wiring which can flatten an insulating film between wiring layers.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, a method of manufacturing a multilayer wiring according to the present invention comprises a step of depositing a substrate side wiring layer, a step of depositing a contact wiring layer on the substrate side wiring layer, a substrate side wiring layer and a contact wiring layer. And simultaneously forming a pattern of the substrate side wiring layer, and a step of etching the contact wiring layer to form a contact portion electrically connecting the substrate side wiring layer and the surface side wiring layer, A step of depositing an insulating layer on a substrate on which a side wiring layer is patterned and a contact portion is formed; and a step of flattening the insulating layer so that the tip surface of the contact portion is substantially flush with the insulating layer And a step of depositing the surface side wiring layer on the insulating layer.

In this case, it is preferable that the wiring layer on the substrate side is made of aluminum and the contact portion is made of a conductive material having a reflectance lower than that of aluminum. As the contact portion, tungsten, titanium-tungsten, titanium nitride, titanium, chromium, molybdenum, gold, or the like is used.

In the method for manufacturing a multilayer wiring according to the present invention, a step of depositing a wiring layer on the substrate side, a step of etching the wiring layer on the substrate side to form a pattern on the wiring layer on the substrate side, and a pattern formation are performed. A step of etching a part of the wiring layer on the substrate side to form a contact portion that electrically connects the wiring layer on the substrate side and the wiring layer on the surface layer; and a step of depositing an insulating layer on the substrate on which the contact portion is formed. , A step of flattening the insulating layer so that the front end surface of the contact portion is substantially flush with the insulating layer, and a step of depositing the surface side wiring layer on the insulating layer.

In this case, aluminum, tungsten, titanium-tungsten, titanium nitride, titanium, chromium, molybdenum, gold or the like is used for the wiring layer on the substrate side and the contact portion.

Further, in the method for manufacturing a multilayer wiring according to the present invention, the above-described method for manufacturing a multilayer wiring is repeated a plurality of times to perform 3
It is intended to form a multi-layer wiring of more layers.

In these cases, a semiconductor wafer can be used as the substrate.

[0018]

According to the above-mentioned means, the board-side wiring layer and the contact portion are formed, and then the insulating layer is formed and flattened to form the board-side wiring layer and the surface-side wiring layer through the contact portion. Since they are electrically connected to each other, good step coverage can be obtained unlike the case where the contact holes are formed in the insulating layer to connect the two.

Since the contact portion is directly formed on the board-side wiring layer to form the laminated structure, there is no risk of etching the board-side wiring layer unlike when a contact hole is formed.

Since the insulating layer is flattened and the surface side wiring layer is deposited and the substrate side wiring layer and the surface side wiring layer are connected through the contact portion, the step difference on the surface is relieved significantly. become.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a cross-sectional view showing a circuit element formed by a method of manufacturing a multilayer wiring according to an embodiment of the present invention, and FIGS. 2 to 10 are manufacturing processes of the multilayer wiring of the circuit element. And FIG. 11 is a plan view showing the main part of the circuit element of FIG.

The circuit element of the present embodiment shown in FIG. 1 is an n-channel type MOS-FET, and in a partial region of a semiconductor wafer (substrate) 1 made of single crystal silicon, a p-type impurity such as B ( Boron) is doped to form the p-well 2. Is active region p- on the well 2 SiO ₂ film 3 is formed, the SiO ₂ film 3
A gate electrode 4 made of, for example, polycrystalline silicon is formed thereon. On both sides of the gate electrode 4, an n-type source region 5 and a drain region 6 are formed by doping with an n-type impurity such as P (phosphorus), and SiO ₂ is formed.
A source electrode (substrate-side wiring layer) 7 and a drain electrode (substrate-side wiring layer) 8 which penetrate the film 3 and contact with the regions 5 and 6 are formed. SiO ₂ is formed around the p-well 2 in order to electrically separate it from other adjacent circuit elements.
A thick field insulating film 9 made of is formed. A wiring portion (substrate side wiring layer) 10 is formed on the field insulating film 9, and the wiring portion 10 is electrically connected to the source electrode 7.

On the MOS-FET, for example, SiO ₂
An interlayer insulating film (insulating layer) 11 made of is deposited.
A wiring portion (surface side wiring layer) 12 is formed on the planarized interlayer insulating film 11, and the wiring portion 12 connects the wiring portion 10 and the source electrode 7 to each other. In order to electrically connect the source / drain electrodes 7 and 8 and the wiring portion 10 and the wiring portion 12 having a laminated structure via the interlayer insulating film 11, the contact portion is formed so as to penetrate the interlayer insulating film 11. 13 is formed. That is, the contact portion 13a for connecting the wiring portion 12 and the source electrode 7, the contact portion 13b for connecting the same wiring portion 12 and the wiring portion 10, and the wiring portion 12
The contact portion 13 for connecting the drain electrode 8 and the drain electrode 8.
c are formed respectively. Then, when a positive voltage is applied to the gate electrode 4 to form an n-type conductive layer under the gate electrode 4, a current flows from the wiring portion 10 to the contact portion 13b, the wiring portion 12, and the contact portion 13a. Flow from the source electrode 7 to the drain electrode 8 and further from the drain electrode 8 to the wiring portion 12 through the contact portion 13c.

A manufacturing process of the multi-layer wiring of the MOS-FET having such a structure will be described with reference to FIGS. 2 to 10 and 11, the S ₁ region of FIG. 1 is shown.

In the S ₁ region of FIG. 1 shown in FIG. 2, Si
With respect to the MOS-FET in which the O ₂ film 3 and the field insulating film 9 are formed and a part of the source region 5 is exposed, as shown in FIG. The side wiring layer) 14 is deposited by the CVD method (first step). Further, as shown in FIG. 4, a contact wiring layer 15 made of, for example, tungsten is similarly formed on the first wiring layer 14 by CV.
Deposition is performed by the D (Chemical Vapor Deposition) method (second step).

First wiring layer 14 and contact wiring layer 15
After depositing, the resist pattern (not shown) is applied on the contact wiring layer 15, the wiring pattern of the first wiring layer 14 is transferred by a photomask, and the pattern of the first wiring layer 14 is etched by an etching technique. Formation is performed (third step). Therefore, in forming this pattern, the contact wiring layer 15 is also etched at the same time. As shown in FIG. 5, when the first wiring layer 14 is patterned, the wiring portion 10 and the source electrode 7 are formed.

Although aluminum, which is the constituent material of the first wiring layer 14, has a reflectance of about 90%, tungsten, which is a constituent material of the contact wiring layer 15, has a low reflectance of about 40%. The wiring pattern of the wiring layer 14 is a contact wiring layer 1 made of tungsten having a low reflectance.
Since it is transferred to the resist coated on 5, the fine resolution can obtain a good resolution without halation even with a fine pattern. As described above, when aluminum is used for the first wiring layer 14, it is desirable that the contact wiring layer 15 be made of a conductive material having a lower reflectance than aluminum, such as tungsten. It is not always necessary to use such a conductive material having a low reflectance, including the case of Example 2 described later.

Next, in order to form the contact portion 13 for electrically connecting the first wiring layer 14 and the second wiring layer (surface side wiring layer) 16 (FIG. 9, FIG. 10) described later, this is formed. A resist is further applied on the resist, the pattern of the contact portion 13 is transferred by a photomask, and tungsten is selectively etched by using, for example, CF ₄ as an etching gas (fourth step). As a result, the contact portion 13 shown in FIG. 6 or 1 is formed.
As shown in FIG. 6, the height of the contact portion 13b formed on the field insulating film 9 is higher than that of the contact portion 13a formed on the SiO ₂ film 3. That is, in this state, the height of each contact portion 13 is different depending on the portion to be formed.

When the contact portion 13 is formed, as shown in FIG. 7, an interlayer insulating film 11 made of, for example, SiO _{2 is} deposited on the semiconductor wafer 1 by the CVD method (fifth step), and this interlayer insulating film is formed. 11 as a whole, for example, CMP (Chemi
The contact portion 1 is etched back by a flattening technique based on the cal mechanical polishing method, as shown in FIG.
It is flattened so that the front end surface of 3 is on the same plane (6th
Process). As illustrated, this flattening allows the contact portions 13 having different heights to be aligned at the same height. The contact portion 13 and the interlayer insulating film 11 do not have to be physically on the same plane, and may have some steps, that is, substantially on the same plane. Further, for planarizing the interlayer insulating film 11, another planarizing technique such as a bias sputtering method can be applied. Further, as the interlayer insulating film 11, BPSG (Boro-Phospho-Silicate Glass) film, PS
G (Phospho-Silicate Glass) film, BSG (Boro-Silicate Glass)
Glass) film, ASG (Arseno-Silicate Glass) film, TE
An OS (Tetra-Ethyl-Ortho-Silicate) film or the like doped with a predetermined impurity may be used.

After the interlayer insulating film 11 is flattened and the heights of the contact portions 13 are made uniform, a second wiring layer 16 is deposited as shown in FIG. 9 (seventh step). Then, by applying a resist and transferring the wiring pattern of the second wiring layer 16 by a photomask and etching this, as shown in FIG. 10, the second wiring layer 16 of, for example, aluminum is formed. Wiring part 1 after pattern formation
2 is formed (eighth step). As a result, the first wiring layer 14 and the second wiring layer 16 are electrically connected by the contact portion 13. For example, as shown in the drawing, the wiring portion 10 and the wiring portion 12, the source electrode 7 and the wiring portion 12 are connected. Are contacted with each other to electrically connect the wiring portion 10 and the source electrode 7. When this is seen in the plan view shown in FIG. 11, the contact portion 13 that connects the first wiring layer 14 and the second wiring layer 16 to each other.
It can be seen that is formed in a cylindrical shape at the position where the wiring layers 14 and 16 intersect. The contact part 1
3 does not have to be cylindrical, but may be formed in a polygonal column such as a square column. That is, the first
Any shape may be used as long as the wiring layer 14 and the second wiring layer 16 can be connected.

By repeating the above-mentioned method, it is possible to form a multi-layer wiring having three or more layers. In this case, the seventh wiring for depositing the second wiring layer 16
Upon completion of the process (1), the process does not move to the eighth process for pattern formation, but to the second process for depositing the contact wiring layer 15. Then, subsequently, the third to seventh steps may be repeated a desired number of times, and finally, the wiring layer on the outermost surface side may be patterned by the eighth step.

As described above, according to the method for manufacturing a multilayer wiring according to the present embodiment, the first wiring layer 14 and the contact portion 13 are formed, and then the interlayer insulating film 11 is formed and planarized. Since the first wiring layer 14 and the second wiring layer 16 are electrically connected to each other through the contact portion 13, the first wiring layer 14 is formed on the interlayer insulating film 11.
Different from the case where the contact hole through which the second wiring layer 16 is formed is formed and good step coverage can be obtained. Thereby, the wiring layer 1 having the laminated structure
The connections 4 and 16 can be performed without causing disconnection of wiring and increase in resistance, and a highly reliable and high-quality product can be manufactured.

In addition, since the aspect ratio of the contact hole does not matter, it is possible to further promote the miniaturization of the device.

The first wiring layer 1 on the semiconductor wafer 1 side
Since the contact portion 13 is directly formed on the wiring layer 4 to form the laminated structure, it is not necessary to form the contact hole, and therefore the wiring layers 14 and 16 are not etched.

Since the interlayer insulating film 11 is flattened to connect the first wiring layer 14 and the second wiring layer 16,
The level difference on the surface is greatly alleviated, lithography and etching can be performed under favorable conditions, and higher quality products can be manufactured.

Since a conductive material having a lower reflectance than aluminum, such as tungsten, is used for the contact wiring layer 15, a pattern with good resolution without halation is formed when forming a circuit pattern. Can be transcribed. Therefore, it becomes possible to sufficiently deal with a fine circuit pattern.

By repeating the method for manufacturing a multilayer wiring according to the present embodiment a plurality of times, it is possible to form a multilayer wiring having three or more layers, and it is possible to achieve high integration and high speed of the device.

(Embodiment 2) FIG. 12 is a cross-sectional view showing a circuit element formed by a method for manufacturing a multi-layer wiring according to another embodiment of the present invention, and FIGS. 13 to 20 are manufacturing multi-layer wiring for the circuit element. It is sectional drawing which shows a process. It should be noted that, in the following, the same members as those of the first embodiment will be described with the same reference numerals.

The circuit element of the present embodiment shown in FIG. 12 is also an n-channel type MOS-FET, and the wiring portion 12 and the source electrode 7 are connected by the contact portion 13a.
The wiring portion 12 and the wiring portion 10 are electrically connected by 3b, and the wiring portion 12 and the drain electrode 8 are electrically connected by the contact portion 13c.

In the manufacturing process of the multilayer wiring according to the present embodiment, the contact portion is formed by utilizing the upper portion of the first wiring layer without depositing the contact wiring layer.
This is different from that of the first embodiment described above.

Here, the manufacturing process in this embodiment is shown in FIG.
The following is a description with reference to FIGS.
13 to 20, the S ₂ region of FIG. 12 is shown.

As compared with the MOS-FET shown in FIG. 13, the first wiring layer (substrate-side wiring layer) 14 is provided as shown in FIG.
Are deposited by the CVD method (first step). Since the upper portion of the first wiring layer 14 becomes the contact portion as described above, it is desirable that the first wiring layer 14 be formed thicker than in the case of the first embodiment.

After the first wiring layer 14 is deposited, the patterning of the first wiring layer 14 is performed using the photoetching technique (second step), and the wiring portion 10 and the source electrode 7 are formed.
Are formed (FIG. 15). Here, as a countermeasure against halation, it is desirable to use a conductive material having a low reflectance, such as tungsten, for the constituent material of the first wiring layer 14.

Next, the first wiring layer 14 is etched to form the contact portion 13 (third step). That is,
A resist is applied to transfer the pattern of the contact portion 13, and the first portion is formed by using, for example, CF ₄ as an etching gas.
The contact layer 13 shown in FIG. 16 is formed by etching the wiring layer 14 by anisotropic etching for a predetermined time.

Then, as shown in FIG. 17, an interlayer insulating film 11 is deposited (fourth step), this is etched back, and as shown in FIG. 18, the tip surface of the contact portion 13 is on the same plane. Are flattened so that the contact portions 13 have the same height (fifth step).

Thereafter, as shown in FIG. 19, a second wiring layer 16 is deposited (sixth step), and as shown in FIG.
Patterning of the second wiring layer 16 is performed (seventh step).

Further, by repeating this method further, it is possible to form a multi-layered wiring having three or more layers as in the case of the first embodiment. In this case, the sixth
In the step of, the second wiring layer 16 is thickly deposited, and then the second step is performed. Then, the third to sixth steps are repeated a desired number of times, and finally the seventh step is performed on the outermost layer side. The wiring layer will be patterned.

As described above, also by the method for manufacturing a multilayer wiring according to the present embodiment, the first wiring layer 14 and the contact portion 13 are formed, and the interlayer insulating film 11 is flattened to form the first wiring layer through the contact portion 13. First wiring layer 14 and second
Since the wiring layer 16 is electrically connected, good step coverage can be obtained. Therefore, the wiring layers 14 and 16 in the laminated structure are connected without causing disconnection of wiring or increase in resistance, and it is possible to manufacture a high-quality product with high reliability.

Further, since the aspect ratio of the contact hole does not matter, the device can be further miniaturized.

It is not necessary to form contact holes in the formation of the wiring layers 14 and 16 having the laminated structure, and the wiring layer 1
There is also no possibility of etching 4,16.

Since the surface level difference is remarkably alleviated by the flattening of the interlayer insulating film 11, lithography and etching can be performed under favorable conditions, and a higher quality product can be manufactured. .

Since the first wiring layer 14 is made of a conductive material having a low reflectance such as tungsten, it is possible to transfer a circuit pattern having a good resolution without halation.

By repeating the method of manufacturing a multilayer wiring according to the present embodiment a plurality of times, it is possible to form a multilayer wiring of three layers or more, and it is possible to achieve high integration and high speed of the device.

(Embodiment 3) FIG. 21 is a cross-sectional view showing a printed circuit board formed by a method of manufacturing a multilayer wiring according to still another embodiment of the present invention.

The illustrated printed circuit board (substrate) 21 is made of, for example, an alumina ceramic which is an insulator, and the first to seventh steps shown in Example 1 are repeated twice on the printed circuit board 21. Finally, the eighth step is applied to form a multilayer wiring having a three-layer structure. The first to sixth steps shown in Example 2 were repeated twice,
Finally, the seventh step may be applied to form a multilayer wiring having a three-layer structure. In addition, the first embodiment
~ By repeating the seventh step or the first to sixth steps in Example 2 three times or more, it is possible to form a multilayer wiring of four layers or more.

Here, in the present embodiment, the wiring layer 22
For example, Mo (molybdenum) is used as a, 22b, 22c, and glass is used as the interlayer insulating film (insulating layer) 23. In the case of forming the first laminated structure, 22a is the wiring layer on the substrate side,
In the case of forming the surface layer side wiring layer 22b and forming the following laminated structure, 22b becomes the substrate side wiring layer and 22c becomes the surface layer side wiring layer.

As described above, the wiring layer having a laminated structure may be formed on the printed board 21 made of an insulator instead of the semiconductor wafer on which a predetermined circuit element is formed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the semiconductor wafer 1 in Examples 1 and 2 is obtained by growing a single crystal silicon film on another semiconductor substrate such as germanium or an insulator such as SOS (Silicon On Sappire). S
OI (Silicon On Insulator) semiconductor substrate,
For example, it may be a semiconductor substrate made of a compound such as GaAs.

Further, each wiring layer 14, 16, 22a, 22
The materials for b and 22c and the contact wiring layer 15 are not limited to those in this embodiment, and various conductive materials can be used. For example, titanium / tungsten, titanium nitride, titanium, chromium, molybdenum, or gold can be used. Note that tungsten may be used for the first wiring layer 14 in the first embodiment, aluminum may be used for the contact wiring layer 15, and aluminum may be used for the first wiring layer 14 in the second embodiment.

Further, each wiring layer 14, 16, 22a, 2
The deposition of 2b and 22c, the contact wiring layer 15, or the interlayer insulating films 11 and 23 may be performed by a physical method such as a sputtering method instead of a chemical method such as a CVD method. Further, for those etchings, either wet etching or dry etching may be used.

The method of manufacturing a multilayer wiring according to the present invention is considered to be most effective if it is applied to a device manufacturing process in a semiconductor integrated circuit device as in the first and second embodiments, but as in the third embodiment. It can be applied to various fields as long as it requires multilayer wiring. Even when applied to the device manufacturing process, the MOS-FE as in the first and second embodiments.
It is needless to say that it is not limited to T and can be applied to the formation of various other devices and wiring layers.

[0064]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.

(1) That is, according to the method for producing a multilayer wiring of the present invention, the wiring layer on the substrate side and the contact portion are formed, and then the insulating layer is formed and planarized to form the contact portion. Since the wiring layer on the substrate side and the wiring layer on the surface side are electrically connected via the contact layer, unlike the case where a contact hole is formed in the insulating layer to connect the two,
Good step coverage can be obtained.

(2) Therefore, it is possible to connect the wiring layers in the laminated structure with no resistance of the wiring and with low resistance, and it is possible to manufacture a reliable and high quality product. .

(3) Further, since the aspect ratio of the contact hole does not matter, it becomes possible to further miniaturize the device.

(4) Since the contact portion is directly formed on the board-side wiring layer to form the laminated structure, there is no risk of etching the board-side wiring layer as in the case of forming a contact hole.

(5) Since the insulating layer is flattened to connect the wiring layer on the substrate side to the wiring layer on the surface side, the step difference on the surface can be remarkably reduced. Therefore, lithography and etching can be performed under favorable conditions, and higher quality products can be manufactured.

(6) When a conductive material having a reflectance lower than that of aluminum is used, a photoresist process is applied to the conductive material to form a pattern with good resolution without halation during the formation of a circuit pattern. Can be transferred. Thereby, it becomes possible to sufficiently deal with a fine circuit pattern.

(7). By repeating such a method of manufacturing a multilayer wiring a plurality of times, it is possible to form a multilayer wiring having three or more layers without a surface step.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a circuit element formed by a method for manufacturing a multilayer wiring according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the multilayer wiring in the S ₁ region of the circuit element shown in FIG.

FIG. 3 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG.

FIG. 4 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG.

FIG. 5 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG.

FIG. 6 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG. 5;

FIG. 7 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG. 6;

FIG. 8 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG.

FIG. 9 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG. 8;

FIG. 10 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG. 9;

11 is a plan view of the S ₁ area in FIG. 1. FIG.

FIG. 12 is a sectional view showing a circuit element formed by a method for manufacturing a multilayer wiring according to a second embodiment of the present invention.

13 is a cross-sectional view showing the manufacturing process of the multilayer wiring in the S ₂ region of the circuit element shown in FIG.

FIG. 14 is a cross-sectional view showing the manufacturing process of the multilayer wiring, which is subsequent to FIG.

FIG. 15 is a cross-sectional view showing the manufacturing process of the multilayer wiring, which is subsequent to FIG.

FIG. 16 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG.

FIG. 17 is a cross-sectional view showing the manufacturing process of the multilayer wiring, which is subsequent to FIG. 16;

FIG. 18 is a cross-sectional view showing the manufacturing process of the multilayer wiring continued from FIG. 17;

FIG. 19 is a cross-sectional view showing the manufacturing process of the multilayer wiring, which is subsequent to FIG. 18;

FIG. 20 is a cross-sectional view showing the manufacturing process of the multilayer wiring, which is subsequent to FIG. 19;

FIG. 21 is a cross-sectional view showing a printed circuit board formed by a method for manufacturing multilayer wiring according to a third embodiment of the present invention.

[Explanation of symbols]

1 semiconductor wafer (substrate) 2 p-well 3 SiO ₂ film 4 gate electrode 5 source region 6 drain region 7 source electrode (substrate side wiring layer) 8 drain electrode (substrate side wiring layer) 9 field insulating film 10 wiring part (substrate) Side wiring layer) 11 interlayer insulating film (insulating layer) 12 wiring part (surface layer side wiring layer) 13 contact part 13a contact part 13b contact part 13c contact part 14 first wiring layer (board side wiring layer) 15 contact wiring layer 16 Second wiring layer (surface side wiring layer) 21 Printed circuit board (substrate) 22a Wiring layer 22b Wiring layer 22c Wiring layer 23 Inter-layer insulating film (insulating layer)

Claims (7)

[Claims] 1. A method of manufacturing a multilayer wiring for electrically connecting a board-side wiring layer and a surface-side wiring layer in a laminated structure formed on a board, the method comprising depositing the board-side wiring layer, Depositing a contact wiring layer on the board-side wiring layer; etching the board-side wiring layer and the contact wiring layer at the same time to form a pattern on the board-side wiring layer; A step of etching to form a contact portion that electrically connects the substrate-side wiring layer and the surface-side wiring layer, and to the substrate on which the contact portion is formed by patterning the substrate-side wiring layer Depositing an insulating layer, flattening the insulating layer so that the tip surface of the contact portion is substantially flush with the insulating layer, and forming a surface wiring layer on the insulating layer. Stack Method for manufacturing a multilayer wiring, comprising the step of. 2. The method of manufacturing a multilayer wiring according to claim 1, wherein the wiring layer on the substrate side is made of aluminum, and the contact portion is made of a conductive material having a reflectance lower than that of aluminum. A method of manufacturing a multi-layer wiring characterized by the above. 3. The method of manufacturing a multilayer wiring according to claim 1, wherein the contact portion is made of tungsten,
Titanium / tungsten, titanium nitride, titanium, chrome,
A method for manufacturing a multilayer wiring, which comprises using molybdenum or gold. 4. A method of manufacturing a multilayer wiring for electrically connecting a substrate side wiring layer and a surface side wiring layer in a laminated structure formed on a substrate, comprising a step of depositing the substrate side wiring layer, A step of etching the substrate side wiring layer to form a pattern of the substrate side wiring layer; and a step of etching a part of the patterned substrate side wiring layer to form the substrate side wiring layer and the surface layer side wiring layer. A step of forming a contact portion for electrically connecting the contact portion, a step of depositing an insulating layer on the substrate on which the contact portion is formed, and a tip end surface of the contact portion being substantially coplanar with the insulating layer. And a step of depositing a surface side wiring layer on the insulating layer, the method for manufacturing a multilayer wiring. 5. The method of manufacturing a multilayer wiring according to claim 4, wherein the wiring layer on the substrate side and the contact portion are made of aluminum, tungsten, titanium-tungsten,
A method of manufacturing a multilayer wiring, which comprises using titanium nitride, titanium, chromium, molybdenum, or gold. 6. A method for manufacturing a multilayer wiring, wherein the method for manufacturing a multilayer wiring according to claim 1, 2, 3, 4 or 5 is repeated a plurality of times to form a multilayer wiring having three or more layers. 7. The method for manufacturing a multilayer wiring according to claim 1, 2, 3, 4, 5 or 6, wherein a semiconductor wafer is used as the substrate.