JPH08288958A - Bus access controller - Google Patents

Abstract

PURPOSE: To inhibit transmission to a network bus on the occurrence of generation of a carrier signal during transmission preparation by generating a transmission enable signal replying with a transmission request, a driver control signal and an unsuccessful notice signal on the occurrence of unsuccessful transmission. CONSTITUTION: A CPU hardware 25 gives a transmission command to a communication LSI 26 and a driver control section 30 monitors detection of a carrier during a window period set by a CPU 25 for a preparation period before the LSI 26 makes a transmission request signal significant. Thus, the CPU 25 is quickly coped with for the transmission unsuccess on the occurrence of the carrier. Furthermore, a driver 27 is closed by the monitor and even when the carrier is caused for the transmission preparation period of the LSI 26, the transmission to a LAN bus S is stopped even on the occurrence of the carrier during the transmission preparation period of the LSI 26. Furthermore, in the case of unsuccessful transmission, a time by a preset flag is not reserved and the communication enable signal is significantly changed, then the time required for the processing of the LSI 26 is shorten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus access control device, for example, a local area network (LAN).
The present invention can be applied to a bus access control device that controls the above bus.

[0002]

2. Description of the Related Art In a LAN, how to guarantee the transmission to a plurality of nodes is one of the technically important points. For example, in a so-called bus type network in which a plurality of nodes are connected to a common bus, when a plurality of nodes simultaneously transmit data to the bus, the data interfere with each other and are destroyed, so that the destination node cannot normally receive. Therefore, various mechanisms for controlling and arbitrating so as to prevent simultaneous transmission to these multiple nodes have been studied, developed, and implemented.

Document "JIS (Japanese Industrial Standard) X525
2, "Local Area Network-CSMA / CD Access Method and Physical Layer Specification", p. 642, pp. 65
4 to 664] As one of them, CS as described in the above-mentioned document
There is MA (Carrier Sense Multiple Access) control.
This is because when a node tries to transmit data, a receiving circuit is used to detect whether or not a carrier carrying the data already exists on the bus, and the transmission is performed only when the carrier is not detected. . If the carrier is detected, the transmission is abandoned and the transmission is retried by a determined process (this is usually called "protocol processing"). This retransmission attempt is repeated until transmission is possible, and if the transmission is not possible even when the number of repetitions reaches a predetermined allowable number, the transmission operation is stopped.

This CSMA control method is also defined and used in a method called Ethernet.

Generally, such a CSMA control mechanism is implemented as an LSI by a manufacturer. Further, it is possible to combine a known technology such as a micro CPU, firmware of a ROM program, and random logic. Although details of these are not disclosed to the public, an example of a bus access control device to which the latter CSMA control mechanism is applied can be configured as shown in FIG. 2, for example.

In FIG. 2, a plurality of nodes (communication terminals)
To the common LAN bus S connected to the node, the driver 27, the receiver 28, and the carrier detection unit 2 of the node.
9 is connected. CPU hardware 25 is CP
Connected to the communication LSI 26 via the U-bus T,
Further, the CPU hardware 25 is adapted to give a driver control signal u to the driver 27 and the receiver 28, and further, the CPU hardware 25 can take in the carrier detection signal V from the carrier detection unit 29. It is made possible.

At the time of standby during transmission and reception, only the receiver 28 is turned on by the driver control signal u, and the signal transmitted by another node is received by this receiver 28.
Is input to the communication LSI 26 via the
It is determined whether or not I26 is addressed to the own node, and if it is addressed to the own node, reception processing such as demodulation and packet assembly is performed, and the received data is given to the CPU hardware 25 via the CPU bus T.

In the program on the CPU hardware 25, the transmission trial process is made into a subroutine.
If you are trying to send, the CPU hardware 25
Advances to a transmission trial subroutine to read the carrier detection signal V input to the port and determine the content thereof.

If the carrier signal does not exist on the LAN bus S, the transmission command and data are given to the communication LSI 26, the driver control signal u is set to the transmission state, the driver 27 is turned on, and the transmission is successful on the program. Set a flag On the other hand, if the carrier is the LAN bus S
, The CPU hardware 25 maintains the receivable state and does not execute the operation of the transmission success flag.

After returning from the subroutine, the CPU hardware 25 performs different processing depending on the state of the transmission success flag. That is, if the transmission success flag is set, it is determined that the transmission is completed and the next process is performed. On the other hand, if the transmission success flag is not set, it is determined that the transmission is unsuccessful, and after waiting for a time, the process is retried.

In this way, when there is a carrier, transmission is suspended and a plurality of transmission signals are prevented from colliding on the LAN bus S.

[0012]

However, the conventional CSMA control method as illustrated in FIG. 2 has the following problems.

(1) The processing of the program intervenes between the time when the carrier detection signal V is read from the carrier detection unit 29 and the time when the driver 27 is actually put into the transmission state. Considering the transfer speed of the CPU bus T, this program processing takes a long time. Therefore, even if it is determined that there is no carrier, carriers from other nodes are starting to be transmitted to the LAN bus S before the transmission signal is output to the LAN bus S via the driver 27.
There is a high risk of collision.

This is a fatal problem in LAN.
In particular, the higher the data transfer rate, the greater the amount of data destroyed, which is a serious problem.

(2) As described above, when the carrier signal on the LAN bus S is detected and it is determined that transmission is impossible, it is desirable to be ready for retransmission as soon as possible. Return to the routine,
After confirming the state of the transmission success flag, the transmission attempt routine is restarted and retry is performed, so that preparation for retransmission takes a considerable time.

Such a problem occurs not only in a bus access control device for a LAN bus but also in a device for a bus on another network, and the network type is a bus type. Not only does this occur in devices in ring-type or lattice-type (or mesh-type in some cases) networks in which a plurality of nodes share the same bus.

[0017]

In order to solve such a problem, in the present invention, a transmission signal from its own node is transmitted to a network bus on condition that there is no carrier signal on the network bus common to a plurality of communication nodes. The bus access control device mounted on the vehicle is configured so as to include the following means.

That is, (A) a communication control means for controlling the communication processing of the own node, and (B) a communication means for converting a signal from this communication control means into a transmission signal to be put on a network bus and outputting it. C) Driver means for controlling passage / non-passage of the output transmission signal from this communication means to the network bus according to the driver control signal, and (D) carrier detection means for detecting that there is a carrier signal on the network bus. And (E) a window period from the time when it is started by the communication control means or the communication means to the significant change of the transmission request signal from the communication means, and when a significant carrier detection signal is given in this window period. In addition to determining that the transmission was unsuccessful, determining that the transmission was successful in other cases, and depending on the determination result, a transmission permission signal that responds to the transmission request signal A driver control signal applied to the stage, characterized in that it comprises a driver control means for forming a failure notification signal for notifying that fact to the communication control unit when transmitting unsuccessful.

[0019]

In the bus access control device of the present invention, the driver control means sets a window period from a time point when it is started by the communication control means or the communication means to a significant change of the transmission request signal from the communication means. It is monitored whether or not a significant carrier detection signal is given to the.

If a significant carrier detection signal is not given during this window period, the driver control means determines that the transmission is successful, and the transmission permission that changes significantly or insignificantly at the timing of success with respect to the transmission request signal. A signal is given to the communication means, and a driver control signal for instructing passage is given to the driver means.

On the other hand, if a significant carrier detection signal is given during the window period, the driver control means determines that the transmission is unsuccessful, and changes significantly or insignificantly at the timing when the transmission request signal is unsuccessful. A transmission permission signal is given to the communication means, a driver control signal for instructing non-passing is given to the driver means, and an unsuccessful notification signal for notifying the transmission failure is given to the communication control means.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bus access control device according to the present invention will be described in detail below with reference to the drawings.

(A) Overall configuration of the embodiment Here, FIG. 3 shows the overall configuration of this embodiment, in which parts that are the same as or correspond to those in FIG. .

In addition to the possible conventional configuration shown in FIG. 2, the bus access control device of this embodiment has the configuration shown in FIG.
The driver control unit 30 showing the detailed configuration is provided.

The newly added driver control unit 30 is
The CPU hardware 25 is connected via the CPU bus T. Further, the driver control unit 30
A transmission request signal and a transmission permission signal, which will be described later, are exchanged as a handshake signal W with the communication LSI 26. Further, the driver control unit 30 takes in the carrier detection signal V from the carrier detection unit 29. Furthermore,
The driver control unit 30 outputs a driver control signal u to the driver 27 and the receiver 28, and C
The PU interrupt signal X is output to the CPU hardware 25.

The communication LSI 26 of this embodiment is
Its main function is to assemble / disassemble packets,
The handshake signal W includes the packet transmission request signal and the packet transmission permission signal as described above. In addition, since the communication LSI 26 actually has a code superimposed on the LAN bus S by a carrier, a coder and a decoder therefor are also incorporated. Further, the communication LSI 26
Is equipped with, for example, a DMAC, and takes in data to be transmitted from the CPU hardware 25.

The driver control unit 30 newly provided in this embodiment has the detailed configuration shown in FIG. That is,
Failure determination / driver ON determination circuit 1, window unit 2, edge detection / timing generation unit 3, preposition flag counter 4, postposition flag counter 5, AND gate 6, I /
It is composed of an O port 7, an unsuccessful holding unit 8 and an edge detection unit 9. The driver control unit 30 uses the clock signals Q and Q * (in this specification, “*” represents an inverted signal of a basic signal or an active low signal) and a reset signal R used by each unit of the control unit 30. It is provided with a * generation circuit or a circuit for receiving these signals from the CPU hardware 25 and delivering them to each unit of the control unit 30. Here, the clock signals Q and Q * are reference clocks for each block, and are selected to have the same frequency as the transfer bit rate to the LAN bus S, for example. Further, the reset signal R * is a system reset input and becomes active at the time of power-on or the like.

(B) Configuration of each part of the driver control section 30 and its operation (B-1) Edge detection / timing generation section 3 The edge detection / timing generation section 3 has a simple internal configuration, but the illustration is omitted. The clock signal Q and the transmission request signal A * from the communication LSI 26 are input, and as shown in FIG. 4, a start detection signal B, a delayed output signal D and an end detection signal C are generated.

That is, the change edge (leading edge) of the transmission request signal A * to the significant level is caught by the falling edge of the clock signal Q to generate the start detection signal B which is significant only for one clock cycle. The start detection signal B is delayed by one clock period to generate the delayed output signal D. further,
The change edge (trailing edge) of the transmission request signal A * to the insignificant level is caught by the falling edge of the clock signal Q, and the significant end detection signal C is generated for one clock cycle.

The start detection signal B is given to the unsuccessful determination / driver ON determination section 1 and the window section 2, the end detection signal C is given to the unsuccessful determination / driver ON determination section 1, and the delayed output signal D is given. , And is given to the failure determination / driver ON determination unit 1 and the AND gate 6.

(B-2) Post-position flag counter 5 The post-position flag counter 5 is composed of a counter, a flip-flop, and a gate in combination, although the detailed structure is omitted in the figure. LSI
As shown in FIG. 5, the transmission request signal A * from the controller 26 is input and the driver OFF signal J * is operated by counting internally.
Is generated.

In the case of this embodiment, a flag pattern (start sequence; preamble signal) is added before the transmission data (packet data), and a flag pattern (end sequence) is also added after the transmission data and output to the LAN bus S. The post-flag counter 5 is provided to secure a predetermined time for the flag pattern to be added after the transmission data.

The post-flag time is conventionally measured by the firmware of the CPU hardware 25, for example. In the case of this embodiment, the failure determination /
It is provided in the driver control unit 30 to give the driver OFF signal J * to the driver ON determination unit 1.

The post-position flag counter 5 has a transmission request signal A
When * changes from insignificant to significant, the internal count value is changed from the reset value "0" to the load value "255-tps", and the load value "2" is maintained during the period when the transmission request signal A * is significant.
55-tps ”and the transmission request signal A * changes insignificantly (meaning that the output of the transmission data has ended as described later), based on the clock signal Q,
When the count value is counted up from the load value "255-tps" and the count value reaches "255" which is a carry condition, the driver OFF signal J * is generated for one clock cycle from the falling edge of the clock signal Q to the next falling edge. And make the count value reset.

As will be described later, a significant change in the driver OFF signal J * causes the driver control signal G to change insignificantly. Even if the transmission request signal A * changes insignificantly, the driver control signal G may change insignificantly immediately due to the functions of the post-position flag counter 5 and the failure determination / driver ON determination unit 1 described later. However, the driver control signal G is changed non-significantly at the time when a period of (tps + 0.5) clocks elapses from the time of non-significant change of the transmission request signal A * to compensate the output of the post-flag pattern. There is. The value tps is determined from the required post-flag length.

(B-3) I / O Port 7 The I / O port 7 intervenes in signal transmission / reception with the CPU hardware 25 via the CPU bus T. CPU
From the hardware 25, via the CPU bus T, a 2-bit window start signal M and an unsuccessful hold release signal N
And the I / O port 7 supplies the window start signal M to the window unit 2 and the unsuccessful holding release signal N to the unsuccessful holding unit 8. The unsuccessful holding signal O from the unsuccessful holding unit 8 is given to the CPU hardware 25 from the I / O port 7 through the CPU bus T.

(B-4) Window Unit 2 The window unit 2 has, for example, the detailed configuration shown in FIG. That is, it is composed of a JK flip-flop 20, two D flip-flops 21 and 22, an AND gate 23, and an inverter gate 24.

The window start signal M is input to the J input terminal and the clock input terminal of the JK flip-flop 20, and "L" is always input to the K input terminal. The reset input terminal RN of the active row of the JK flip-flop 20 outputs the AND signal of the signal B * obtained by inverting the start detection signal B from the edge detection / timing generator 3 by the inverter gate 24 and the reset signal R *. Is entered.

The signal from the non-inverting output terminal Q from the JK flip-flop 20 is input to the D input terminal of the D flip-flop 21, and the signal from the non-inverting output terminal Q from the D flip-flop 21 is The signal from the non-inverting output terminal Q of the D flip-flop 22 is input to the D input terminal of the D flip-flop 22 of FIG. In addition, these D flip-flops 21
A clock signal Q and a clock signal Q * are input to the clock input terminals 22 and 22, respectively, and a reset signal is input to the reset input terminal RN of the active row. That is, these D flip-flops 21 and 22 function only as a latch circuit having a delay function.

Therefore, the operation of only the window section 2 will be described. When the reset signal R * for the entire system changes to a significant level ("L"), all three flip-flops 20-22 are reset. When the window start signal M is given in this state, the JK flip-flop 2
The Q output signal of 0 rises to "H", and after that, the window output signal F becomes significant ("H") after a delay time (0.5 clock period to 1.5 clock period) by the D flip-flops 21 and 22. ). When the transmission request signal A * changes to significant (“L”) and the start detection signal B also changes to significant (“H”), the JK flip-flop 20.
Is reset and its Q output signal returns to "L", and the window output signal F is delayed by the delay time (one clock cycle) by the D flip-flops 21 and 22 from that point.
Also changes to non-significant (“L”) (see FIGS. 8 and 9 described later).
reference). Since the start detection signal B is synchronized with the clock signal Q and has a pulse width of one clock cycle, the start detection signal B falls to the insignificant point and the window output signal. This coincides with the falling time point of F to insignificance, in other words, the last one clock cycle period of the significant period of the window output signal F coincides with the significant period of the start detection signal B (see FIG. 8 described later). And FIG. 9).

The operation of the CPU hardware 25 described later ensures that the window start signal W comes before the start detection signal B changes to a significant level. Moreover, unless the window start signal M is given, the window output signal F does not take a significant level (see FIG. 9 described later).

The operation of the window unit 2 will be performed together with the operation of the unsuccessful judgment / driver ON determination unit 1 and the AND gate 6, but briefly, it will be described as the carrier detection signal E (V in FIG. 3). It defines the time (window period) for making a successful transmission / unsuccessful determination based on the transmission.

(B-5) Failure determination / driver ON determination section 1 and AND gate 6 The failure determination / driver ON determination section 1 has, for example, a detailed configuration shown in FIG. That is, two JK flip-flops 10 and 12, two D flip-flops 11 and 13, and three AND gates 14, 17 and 19,
Two inverter gates 15 and 18 and a logic circuit 16
It consists of and.

The reset signal R * is input to the reset input terminals RN of the active flips of the four flip-flops 10 to 13. The flip-flops 10 to 13 are reset in the initial state. There is. The reset input terminal RN of the JK flip-flop 12 receives not only the reset signal R * but also the driver OFF signal J * from the post flag counter 5 via the AND gate 19. ,
Even when the driver OFF signal J * is significant (“L”), it is reset. Further, the clock input terminals of the two JK flip-flops 10 and 12 are
The clock signal Q is input so as to trigger at the rising edge, and the clock signal Q is input to the clock input terminals of the two D flip-flops 11 and 13 so as to trigger at the falling edge.

The unsuccessful determination / driver ON determination section 1 is mainly divided into a transmission failure signal I generation section and a driver control signal G and front flag counter control signal H generation section.
I can share.

Inverter gate 15, AND gate 14, logic circuit 16 and J are components of the transmission failure signal I generator in the failure determination / driver ON determination unit 1.
The K flip-flop 10 and the D flip-flop 11 correspond.

The logic circuit 16 is a so-called AND-OR type logic circuit consisting of two two-input AND gates 16a and 16b and an OR gate 16c for obtaining an OR output of the AND gates.

The AND gate 14 receives the window output signal F from the window section 2 and the start detection signal B from the edge detection / timing generation section 3 in the inverter gate 15.
And a signal B * which is inverted. As mentioned above,
The last one clock cycle period of the significant period of the window output signal F coincides with the significant period of the start detection signal B. Therefore, from the AND gate 14, the last one clock period from the significant period of the window output signal F. A modified window output signal having a significant period shorter than the cycle period is output, and the modified window output signal is input to one AND gate 16a of the logic circuit 16. The carrier detection signal E from the carrier detection unit 29 is also applied to the AND gate 16a.

The other AND gate 16b of the logic circuit 16
A signal from an inverting output terminal QN of a D flip-flop 13, which will be described later, and a delayed output signal D from the edge detection / timing generator 3 are input to the. The signal from the inverted output terminal QN of the D flip-flop 13 is the inverted signal H * of the signal H obtained by delaying the driver control signal G by 0.5 clock cycle, and is the delayed output signal from the edge detection / timing generation unit 3. D is a signal obtained by delaying the start detection signal B by one clock cycle.

Therefore, from the logic circuit 16, roughly speaking, "a signal in which the carrier detection signal E is significant (" H ") for a significant period within the significant period of the modified window output signal", or A "signal that becomes significant (" H ") for one clock cycle period from when the start of the transmission request signal A * is detected when the driver control signal G is insignificant indicating reception" is output. It is applied to the J input terminal of the JK flip-flop 10.

On the other hand, the K input terminal of the JK flip-flop 10 is supplied with the end detection signal C of the transmission request signal A * from the edge detection / timing generator 3.

Here, the signal applied to the J input terminal is
A signal that becomes significant before the start detection signal B generated from the transmission request signal A * or becomes significant during the same period as the significant period of the delayed output signal D thereof. Since the end detection signal C of * is given, J
The signals to the K input terminal and the K input terminal do not become "H" at the same time.

Therefore, the signal from the non-inverting output terminal Q of the JK flip-flop 10 is "when the carrier detection signal E becomes significant within the significant period of the modified window output signal" or "driver control. From the time when the start of the transmission request signal A * is detected when the signal G is non-significant, it becomes "significant (" H ") and returns to non-significant when the end detection signal C changes to significant. Becomes
In all other cases, the signal from the non-inverting output terminal Q of the JK flip-flop 10 remains in the non-significant state.

Such a signal is given to the front flag counter 4 and the failure holding section 8 as the transmission failure signal I. The unsuccessful transmission signal I is the clock signal Q.
Is latched in the D flip-flop 11 at the falling edge of, and the transmission unsuccessful signal I from its inverted output terminal QN is delayed by 0.5 clock cycle, and its inverted signal is given to the AND gate 17 described later. To be

On the other hand, an inverter gate 18, an AND gate 17, a JK flip-flop 12 and a D flip-flop 13 correspond to the constituent elements of the generator of the driver control signal G and the front flag counter control signal H.

The carrier detection signal E (represented by signal V in FIG. 3) from the carrier detection unit 29 is inverted via the inverter gate 18 and input to the AND gate 17. The AND gate 17 has a transmission request signal A
The start detection signal B from the edge detection / timing generation unit 3 and the output signal from the inverting output terminal QN of the D flip-flop 11 which become significant only for one clock cycle following the significant change of * are also input. Here, since the D flip-flop 11 latches the transmission failure signal I as described above, the output signal from its inverting output terminal QN is paraphrased when the transmission failure signal I is insignificant. Then, when the transmission failure signal I does not indicate the transmission failure, "H" is taken.

Therefore, the output signal from the AND gate 17 is roughly as follows: "The carrier on the LAN bus S is not detected, and the transmission request signal A * is set in the state where the transmission failure is not set. When it changes significantly ”, it changes to“ H ”.

The output signal from the AND gate 17 is
Since it is input to the J input terminal of the JK flip-flop 12 and its K input terminal is always fixed to "L", the signal from the non-inverting output terminal Q of the JK flip-flop 12 is "on the LAN bus S. Carrier is not detected,
In addition, when the transmission request signal A * changes significantly while the transmission failure is not set, the clock signal Q
Changes to "H" in synchronism with. The signal from the non-inverted output terminal Q returns to "L" when the driver OFF signal J * changes significantly except for resetting the entire system. As described above, the driver OFF signal J * changes significantly after the transmission request signal A * changes insignificantly, and the post flag counter 5 outputs (tps + 0.
5) It is the time when only the clock cycle is counted.

That is, the signal from the non-inverted output terminal Q of the JK flip-flop 12 is "the carrier request signal on the LAN bus S is not detected, and the transmission request signal A is set in the state where the transmission failure is not set. "When * changes significantly", "when the post-flag counter 5 counts (tps + 0.5) clock cycles after the transmission request signal A * changes non-significantly" or "transmission failure is set "H", and this output signal is output as the driver control signal G (represented by signal u in FIG. 3).

The driver control signal G is input to the D input terminal of the D flip-flop 13 and latched at the falling edge of the clock signal Q. A signal obtained by delaying the driver control signal G by 0.5 clock cycle from the non-inverting output terminal Q of the D flip-flop 13 is applied to the AND gate 6 shown in FIG. The inverted signal H * of the front flag counter control signal H from the inverted output terminal QN of the D flip-flop 13 is given to the logic circuit 16 as described above.

The AND gate 6 obtains the AND output of the delayed output signal D obtained by delaying the start detection signal B by one clock cycle and the prefix flag counter control signal H, and supplies it as the flag start signal K to the prefix flag counter 4. .

Next, the operation of the window unit 2 described above, and the operation of the unsuccessfulness determination / driver ON determination unit 1 and the AND gate 6 having the above-described configuration will be described.

First, the operation of these constituent elements when there is a carrier signal in the transmission operation and the transmission operation is stopped will be described with reference to FIG.
This will be described with reference to the time chart of.

The program (firmware) on the CPU hardware 25 is
The window start signal M is output (t1). Then C
The program on the PU hardware 25 is a communication LSI
A transmission command is given to 26 to instruct the start of transmission. Note that these orders may be reversed (FIGS. 13 and 14 to be described later show the case of the reverse order). Due to the output of the window start signal M described above, the window output signal F becomes significantly significant. It changes (t2). Further, the communication LSI 26 instructed to start the transmission shifts to the transmission state after a lapse of a predetermined time from the instruction time point, and outputs the significantly changed transmission request signal A * to the driver control unit 30 (t3. ).

The last clock cycle of the window output signal F, that is, the period when the start detection signal B is significant, is special due to the functions of the AND gate 14 and the inverter gate 15. Therefore, the carrier detection signal E is generated in other clock cycles. When significant (t4), the logic circuit 1 connected to the J input terminal of the JK flip-flop 10
The passage condition of the carrier detection signal E of the gate 16a of No. 6 is satisfied, the output signal from the non-inverting output terminal Q of the JK flip-flop 10 becomes significant, and the transmission failure signal I becomes significant (“H”). Even when the carrier detection signal E is already significant when the window start is instructed, the same operation is performed.

The setting condition of the JK flip-flop 12 which determines the driver control signal G is determined from the input of the AND gate 17 by the states of the transmission failure signal I and the carrier detection signal E when the start detection signal B is significant. However, in this case, the condition is not satisfied because the transmission failure signal I is significant. Therefore, the driver control signal G is insignificant ("L") (t5). Therefore, the front flag counter control signal H does not change significantly, and the flag start signal K
Also remains non-significant (“L”).

Even if the unsuccessful transmission signal I becomes significant, as will be described in detail later, the transmission permission signal L * from the front flag counter 4 is predetermined from the time when the transmission request signal A * becomes significant. The communication LSI 26, which has significantly changed after a lapse of time and has received the significantly changed transmission permission signal L *, sends packet data (in this case, to the driver 27 which is closed based on the non-significant driver control signal G at that time). Dummy data)
Is transmitted, and when it ends, the transmission request signal A * is made insignificant (t6). Due to the end detection signal C which is detected and significantly changed, the transmission failure signal I from the JK flip-flop 10 also changes to insignificant (“L”) (t).
7).

Next, the operation of the failure determination / driver ON determination unit 1 and the AND gate 6 etc. in the case where there is no carrier in the transmission operation will be described with reference to the time chart of FIG. Signal in particular).

When there is no carrier detection signal E (when it is insignificant continuously), there is no significant change in the transmission failure signal I based on the significant carrier detection signal E. In such a state, when the start detection signal B changes significantly, since the significant transmission failure signal I and the carrier detection signal E do not exist, the significant condition of the AND gate 17 is established and the non-inversion of the JK flip-flop 12 is performed. The driver control signal G which is an output signal from the output terminal Q becomes significant (t8). That is, ON of the driver 27 is determined.

As a result, the pre-flag counter control signal H which becomes significant 0.5 clock cycles after the significant change of the driver control signal G and the delay output signal D which is delayed 1 clock cycle from the start detection signal B are input. A significant flag start signal K is output from the AND gate 6 (t9).

When the flag start signal K changes significantly, the prefix flag counter 4, which will be described in detail later, counts the prefix flags and makes the transmission permission signal L * significant, so that only the prefix flags are transmitted. The front flag is formed after waiting, and desired packet data is transmitted from the communication LSI 26 during the significant period of the transmission permission signal L *. Communication LSI 26
As shown in FIG. 5 described above, the post-flag counter 5 operates from the time when the transmission request signal A * from the non-significant signal indicates the end of the desired packet data, and after a predetermined time elapses, the driver OFF signal is output. Make J * significant. As a result, the JK flip-flop 12 is reset, the driver control signal G changes insignificantly, and the driver 27 is closed.

When the carrier detection signal E is significant (when there is a carrier), it may be shown in FIG. 9 as a special case.

When the start detection signal B is a significant clock cycle and the carrier detection signal E is significant (t10), the operation of the failure determination / driver ON determination section 1 is slightly different from the above.

At this point, AND gates 16a and 1
Since the output significant condition by 6b is not satisfied, the transmission failure signal I from the JK flip-flop 10 does not change significantly. Further, since the output significant condition of the AND gate 17 is not satisfied, the driver control signal G from the JK flip-flop 12 does not change significantly.

However, the AND gate 16b, which is delayed by 0.5 clock cycle from the insignificant driver control signal G, and whose inverted signal is input, is delayed by 1 clock cycle from the start detection signal B and is significant. When the delayed output signal D changed to is input, the output significant condition is satisfied, and the transmission failure signal I from the JK flip-flop 10 is input.
Changes significantly (t11).

As described above, in this case, the timing at which the transmission failure signal I changes significantly is different from that described above.

As shown in the lower part of FIG. 9, in the situation where the window output signal F is not significant,
Even if the significance of the start detection signal B and the carrier detection signal E overlap (including the case where the significance of the carrier detection signal E starts before the significance of the start detection signal B significantly changes), the same operation is performed. This case corresponds to the case where the CPU hardware 25 having no output function of the window start signal M is connected. However, this example basically
It is assumed that the CPU hardware 25 having the function of outputting the window start signal M is connected.

(B-6) Prefix Flag Counter 4 Although the detailed configuration of the prefix flag counter 4 is omitted,
A combination of a counter, a flip-flop, and a logic gate is configured to realize a time chart as shown in FIGS. It should be noted that the transmission request signal A *, the flag start signal K, the transmission failure signal I, and the clock signal Q are input to the prefix flag counter 4, and the prefix flag counter 4 transmits according to the contents of these signals. The permission signal L * is generated.

The front flag counter 4 is provided for compensating a predetermined time of a flag pattern added before transmission data (packet data). It should be noted that the front-end flag counter 4 is conventionally provided in the communication LSI 26 in many cases, and the same component as that can be applied in this embodiment as well. However, in the case of this embodiment,
Furthermore, a configuration for realizing the time chart shown in FIG. 11 is added. Further, since it is a generation unit of the transmission permission signal L *, it is provided in the driver control unit 30.

FIG. 10 shows a case in which the transmission is successful and the prefix flag is counted. As described with reference to FIG. 8, when there is no carrier on the LAN bus S, the flag start signal K changes significantly 1.5 clock cycles after the transmission request signal A * changes significantly. Based on the clock signal Q, the pre-flag counter 4 detects that the flag start signal K has changed significantly two clock cycles after the transmission request signal A * has changed significantly.

As a result, an internal 8-bit counter, for example, loads the value "256-tpr" and starts counting up. Then, when the count value changes from “255” to “0”, the transmission permission signal L * is changed significantly. As a result, the communication LSI 26 outputs the packet data and changes the transmission request signal A * insignificantly at the end of the packet data. When the transmission request signal A * changes non-significantly, the front flag counter 4 also changes the transmission permission signal L * non-significant in the next clock cycle.

As is apparent from FIG. 10, since the count value takes a value other than "0" for tpr clocks, the transmission permission signal L * becomes significant after the transmission request signal A * becomes significant. It takes (tpr + 3) clocks until it becomes significant. Therefore, it takes (tpr + 2) clocks after the drive control signal G becomes significant until the transmission permission signal L * becomes significant. Since this corresponds to the transmission time of the prefix flag (preamble signal), the load value can be calculated by determining the value of tpr from the required flag length.

On the other hand, FIG. 11 shows a case where the transmission is unsuccessful and the transmission permission signal L * is made significant immediately without counting the prefix flag. The communication LSI 26 of this embodiment
Indicates that the activated transmission operation cannot be terminated unless the transmission permission signal L * becomes significant and the data transmission operation is not executed even once. Therefore, it is necessary to make the transmission permission signal L * significant even when the transmission is unsuccessful.

When a significant transmission failure signal I is given in the situation where the count value after the transmission request signal A * has changed significantly is "0", the transmission permission signal L * is changed significantly. That is, in this case, the significant flag start signal K
Is not given, the above condition is regarded as a significant change condition of the transmission permission signal L *. When the transmission request signal A * changes insignificantly, the front flag counter 4 also changes the transmission permission signal L * insignificantly in the next clock cycle, as in the case of successful transmission.

That is, the front flag counter 4 is set to (1)
The internal counter, which has started counting up due to the arrival of the significant flag start signal K, has output a carry signal,
Or (2) the count value is “0” and the transmission failure signal I
And that the transmission request signal A * is significant may be configured as a significant change condition of the transmission permission signal L *, and the change of the transmission permission signal L * to a non-significant level may be transmitted. It may be configured to be performed when an insignificant change of * is detected. If the internal counter relating to the formation of the transmission permission signal L * is formed so that the flag start signal K is significant, the transmission permission signal L * can be distinguished by distinguishing between the states (1) and (2). Can be changed significantly.

(B-7) Failure holding unit 8 and edge detection unit 9 The failure holding unit 8 and edge detection unit 9 are provided for interfacing with the CPU hardware 25,
The specific circuit is omitted for simplicity, but it has the following functions.

The unsuccessful transmission signal I is latched by the JK flip-flop 10 in the unsuccessful determination / driver ON determination section 1. This unsuccessful transmission signal I is a non-significant change of the transmission request signal A *. It changes non-significantly due to the significant change of the end detection signal C that becomes significant, and this configuration alone cannot guarantee that the CPU hardware 25 has caught that the transmission failure signal I has become significant. .

Therefore, the CPU hardware 25, which holds that the transmission failure signal I from the failure determination / driver ON determination section 1 has changed significantly, is set at an arbitrary timing via the I / O port 7. Of the CPU interrupt signal P (signal X in FIG. 3) by detecting the change edge of the holding and transmission unsuccessful signal O held by the unsuccessful holding unit 8 to significant. Is provided). The significance of the held transmission unsuccessful signal O held in the unsuccessful holding unit 8 can be canceled by the reset signal N from the CPU hardware 25 via the I / O port 7.

The CPU interrupt signal P is the CPU
The rising edge detection mode of the hardware 25 is assumed, and one cycle pulse of active low is assumed. The operations of the failure holding unit 8 and the edge detection unit 9 are performed in synchronization with the clock signal Q.

(C) Operation of CPU Hardware 25 As the CPU hardware 25, various configurations can be connected to the driver control section 30, but the following operation example shown in FIG. 12 is executed. Now, the operation will be described below.

When the need for transmission arises, the CPU hardware 25 starts the processing of the transmission processing routine shown in FIG. 12A, and first sets the transmission number parameter x to the initial value 1 and The transmission result flag FLG is set to "success" which is the initial content (step 100). Thereafter, the command setting operation is performed so that the communication LSI 26 performs the transmission operation, and the window setting operation is performed on the driver control unit 30 (steps 101 and 02). The order of these processes may be reversed. Then, the built-in first timer for observing the communication completion notification set by the communication LSI 26 is started and the process returns to the main routine (step 103).

The interrupt to the CPU hardware 25 is activated when the interrupt signal X is given from the driver control unit 30 (more specifically, the edge detection unit 9) and when the previous transmission is unsuccessful. There is a case where a second timer, which will be described later, for activating the re-transmission in the case of success has timed up, and a built-in first timer for going to the communication completion notification has timed up. In addition,
The time measured by the first timer is considerably shorter than the time measured by the second timer.

When the interrupt signal X from the driver control section 30 is given, the CPU hardware 25 operates as shown in FIG.
Proceeding to the routine shown in (B), the contents held in the unsuccessful holding unit 8 in the driver control unit 30 are fetched, and it is determined whether or not it indicates an unsuccessful transmission (steps 150, 1).
51). If the transmission failure is not instructed, the process shown in FIG.
The routine proceeds to 2 (D). On the other hand, if the transmission failure is instructed, the transmission result flag FLG is reset to "unsuccessful", the transmission count parameter x is incremented by 1, and then the transmission count parameter x exceeds the transmission allowable repetition count TH. It is determined whether or not (steps 152 to 1)
54). The transmission count parameter x is the transmission allowable repetition count T
If it exceeds H, the transmission abnormal completion processing for completely giving up the transmission is executed and the process returns to the main routine (step 15).
5). On the other hand, when the transmission count parameter x is equal to or smaller than the transmission allowable repetition count TH, the contents held in the failure holding unit 8 in the driver control unit 30 are reset, the second timer is activated, and the process returns to the main routine (step 156). 157).
In addition to such a process, a process of changing the transmission data defined by the already transmitted transmission command to instruct a small amount of dummy data so that the current transmission operation of the communication LSI 26 is terminated early. It is preferable to carry out

In the case of an interrupt in which the second timer has timed out, the routine proceeds to the routine shown in FIG.
The U hardware 25 causes the above-described processing of step 101 and subsequent steps to be executed. As a result, the transmission operation for the number of times indicated by the transmission number parameter x at that time is executed.

In the case of an interrupt in which the first timer has timed out, the routine proceeds to the routine shown in FIG.
The U hardware 25 first determines whether or not there is a transmission completion notification (step 200). If there is no transmission completion notification, the first timer is restarted and the process returns to the main routine (step 201). If there is a transmission completion notification, the content of the transmission result flag FLG is determined (step 202).
When the flag FLG indicates "success", the transmission success end process is executed and the process returns to the main routine (step 20).
3). When the flag FLG indicates "unsuccessful", the flag FLG is returned to the initial content "success", the transmission unsuccessful ending process is executed, and the process returns to the main routine (step 2).
04, 205). It should be noted that the transmission unsuccessful ending process also includes a process of resetting the content held in the unsuccessful holding unit 8 in the driver control unit 30.

As described above, the CPU hardware 25
If the transmission is unsuccessful, the transmission operation is repeatedly activated at a predetermined cycle until the transmission is successful, and if the transmission is successful, the success end process is executed, and even if the transmission is repeated by the transmission allowable repetition number TH, it is not possible. If successful, the abnormal transmission completion processing is executed.

(D) Overall Operation of Embodiment Hereinafter, the overall operation of the bus access control device of the embodiment at the time of transmission, that is, the CPU hardware 25 and the communication LSI
Mutual operations of the driver 26, the driver control unit 30, the driver 27, and the like will be sequentially described with reference to FIGS. 13 and 14 for a case where the transmission is successful and a case where the transmission is unsuccessful. In addition,
13 and 14 show the transmission operation at a certain number of times regardless of the number of times the transmission is repeated.
Shows the case where the transmission is successful, and FIG. 14 shows the case where the transmission is unsuccessful.

First, the CPU hardware 25 sets a transmission command to the communication LSI 26 and sets a window. By the window setting operation of the CPU hardware 25, the window of the window unit 2 in the driver control unit 30 opens (makes the window signal F significant). On the other hand, the communication LSI 26 executes a predetermined transmission preparation process in response to the setting of the transmission command to significantly change the transmission request signal A *. The predetermined transmission preparation process also includes, for example, a process of starting the output of the flag pattern transmitted before the original packet data.

The window is closed due to a significant change in the transmission request signal A *, but if there is no carrier on the LAN bus S during the window period until the closing time, the driver control unit 30 determines that the transmission is successful, Almost at the same time as the determination time, the driver control signal u (G) changes significantly and the driver 27 opens the gate. This allows
A flag pattern (prefix flag) is transmitted to the LAN bus S, and the prefix flag counter 4 in the driver control unit 30 is transmitted.
The clock starts. When the time corresponding to the prefix flag length ends, the prefix flag counter 4 in the driver control unit 30
The transmission permission signal L * from 1 changes significantly. In response to this change, the communication LSI 26 sends out packet data. The data length of the packet data changes depending on the contents set by the program (firmware) in the CPU hardware 25.

When the output of the packet data is completed, the communication LSI 26 switches to the transmission of the flag pattern and changes the transmission request signal A * insignificantly. The driver control unit 30 responds to the insignificant change of the transmission request signal A *.
The transmission permission signal L * from is also immediately insignificantly changed,
The gate control signal u (G) from the driver control unit 30 is
Even if the transmission request signal A * changes non-significantly, it changes non-significantly after waiting for the timing of the post-position flag (end sequence) by the post-position flag counter 5. As a result, the flag pattern is output to the LAN bus S subsequently to the packet data.

When the output of the packet data is completed, the communication LSI 26 thereafter carries out an ending process,
A transmission completion notification is issued to the CPU hardware 25 to inform that one transmission sequence has been completed. The CPU hardware 25 confirms that the content stored in the unsuccessful storage unit 8 in the driver control unit 30 indicates “success” and that the transmission completion notification is given, so that the transmission is completed successfully. Upon recognition, a series of transmission operations are completed normally.

Next, the operation when the presence of a carrier is detected during the window period, that is, when the transmission is unsuccessful will be described with reference to FIG.

The CPU hardware 25 is a communication LSI
26, the window is opened in the window section 2 in the driver control section 30, and the communication LSI 26 executes a predetermined transmission preparation process in response to the transmission command setting. The part of the processing that is executed to significantly change the transmission request signal A * and start the output of the flag pattern is similar to the above case.

When a significant carrier detection signal V (E) is given during the window period, the driver control unit 30
The unsuccessful determination / driver ON determination unit 1 outputs a significantly changed transmission unsuccessful signal I.
The CPU interrupt signal X (O) is output to the hardware 25, and the CPU hardware (firmware) 25 recognizes the unsuccessful transmission by the processing based on the output.

After that, even if the communication LSI 26 significantly changes the transmission request signal A * as described above, the driver control unit 30 also outputs a significant driver control signal u (G) due to the transmission failure. The significant front flag counter control signal H is also not output. Therefore, the driver 27 does not open, and the flag pattern from the communication LSI 26 is LAN
It is not output to the bus S. Further, at this time, since the count for the prefix flag is not executed by the prefix flag counter 4, the transmission permission signal L *, which is the output thereof, immediately changes significantly due to the significant change of the transmission request signal A *. The communication LSI 26 immediately starts the output operation of packet data (which becomes dummy data), but since the driver control signal u (G) is insignificant as described above, the packet data is output to the LAN bus S. Not done.

When the output of the packet data is completed, the communication LSI 26 switches to the transmission of the flag pattern and changes the transmission request signal A * insignificantly. In response to the non-significant change of the transmission request signal A *, the transmission permission signal L * from the driver control unit 30 also immediately changes to non-significant. In this case as well, the post-position flag counter 5 performs the counting operation, but since the driver control signal u (G) is already insignificant and it is not necessary to change it insignificantly, the counting operation of the post-position flag counter 5 is meaningless. Therefore, the flag pattern from the communication LSI 26 at that time is also not output to the LAN bus S.

When the output of the packet data is completed, the communication LSI 26 thereafter carries out an ending process,
A transmission completion notification is issued to the CPU hardware 25 to inform that one transmission sequence has been completed. The CPU hardware 25 indicates that the content held in the unsuccessful holding unit 8 in the driver control unit 30 indicates "unsuccessful", and the transmission completion notification is given, so that the transmission ends unsuccessfully. Recognizing that, if the number of allowable transmission repetitions has not been reached, preparation is made for retransmission, and if the number of allowable transmission repetitions has been reached, transmission is abandoned.

As described above, since there is no prefix flag for the operation after the transmission request, if the transmission data length setting by the program (firmware) on the CPU hardware 23 is short, the transmission operation can be completed quickly. Therefore, it is possible to reduce waste when moving to retransmission.

(E) Effects of the Embodiment According to the bus access control device of the above embodiment, the following effects can be obtained.

(1) Driver control section 3 of hardware configuration
0 and the communication LSI 26 transmit and receive the transmission request signal A * and the transmission permission signal L *.
I26 requests transmission, waits for permission of transmission, and waits for LAN bus S
The transmission waiting state for the handshake required to access can be set to the minimum time, and the transmission can be executed quickly.

(2) The CPU hardware 25 is the communication LS
Even in the preparation period before giving a transmission command to I26 and the communication LSI 26 makes the transmission request signal A * significant, the driver control unit 30 detects the carrier during the window period set by the CPU hardware 25. Since the CPU hardware 25 can easily and quickly respond to the transmission failure due to the carrier generation, the driver 27 immediately closes based on the monitoring when the transmission failure due to the carrier generation occurs. So
Even if a carrier occurs during the transmission preparation period of the communication LSI 26, the transmission to the LAN bus S can be surely stopped.

Incidentally, in the past, CPU hardware 25
Controls the driver control signal by the internal program, and therefore, when a carrier is generated during the transmission preparation period of the communication LSI 26, the driver control signal is delayed non-significantly and data flows to the LAN bus S. However, according to this embodiment, the transmission can be reliably stopped as described above.

(3) When the transmission is unsuccessful, the communication permission signal L * is changed significantly without securing the time for the prefix flag, so that the time required for the processing of the communication LSI can be shortened. You can In this case, the CPU
When the hardware 25 is made to execute the processing for shortening the data length on the program, it is possible to quickly move to the preparation for retransmission, and it is possible to expect a great improvement in the bus transfer capability and the resistance against packet congestion. .

(4) Since the driver control section 30 is composed of a combination of logic gates as described above,
The SI can be easily realized, and even if the driver control unit 30 is newly added, the entire configuration of the bus access control device can be made small. Actually, 1/3 to 1 of LSI processing speed
It is possible to control access to the LAN bus S up to a transfer rate of / 2. That is, the LSI processing speed is 4
With 0 MHz, it is possible to target transfer rates up to 13 to 20 Mbit / s. When the LSI is used, the required number of gates is approximately 0.7K when an 8-bit binary counter is used for the built-in counters of the front flag counter 4 and the rear flag counter 5.

(F) Other Embodiments In the above-mentioned embodiment, the one in which the electric LAN bus S is accessed has been shown (the transfer of the baseband code modulated wave by the conductor line is considered), but the optical LAN is used. However, it is also applicable to a wireless LAN. Further, the present invention can be applied to a bus access control device for networks other than LAN (including bus connection in the information processing device), and the network type is not limited to the bus type, but may be a ring type or a lattice type if applicable. There is no problem even if it is a mesh type. Therefore, the communication method is not limited to the packet transfer method.

Further, in the above embodiment, the interface between the CPU hardware 25 and the driver control unit 30 is shown by using the I / O port 7, but it is sufficient if the interface can be established. Other interface forms are also applicable.

Furthermore, in the above embodiment, the window start signal is output from the CPU hardware 25, but it may be output as the first process when the communication LSI 26 receives a communication command.

Further, in FIG. 3, the carrier detecting unit 29 directly takes in the signal from the LAN bus S, but in some cases, the carrier detecting unit 29 may carry out carrier detection from the signal after being taken in by the receiver 28. Is also good.

In the above embodiment, the communication LSI 26 is used.
Although the driver control unit 30 and the driver control unit 30 are configured as separate LSIs, they may be configured on the same LSI, and the CPU hardware 25 and the like may also be mounted on the same LSI. On the contrary, the communication LSI 26 and the driver control unit 30 may be composed of a plurality of integrated circuits or discrete components. That is, in the above-described embodiment, the driver control unit 30 has the same structure as that shown in FIG.
Although the description has been made assuming that the respective units shown in are mounted, some of the elements may be mounted on the communication LSI 26 side.

The present invention is characterized by the configuration of the driver control unit 30 and the provision of the driver control unit 30, and the processing of the CPU hardware 25 and the communication LSI 26 is not the same as that of the above embodiment. It may be a slightly different process.

[0121]

As described above, according to the present invention, in addition to the communication control means, the communication means, the driver means, and the carrier detection means, from the time when the communication control means or the communication means starts and starts, The window period is up to the significant change of the transmission request signal of, and if a significant carrier detection signal is given in this window period, it is determined that the transmission is unsuccessful, and in other cases, it is determined that the transmission is successful, and depending on the determination result. A transmission permission signal returned in response to the transmission request signal, a driver control signal given to the driver means,
Since the driver control means for forming the unsuccessful notification signal for notifying the communication control means at the time of unsuccessful transmission is provided, the transmission to the network bus can be surely prohibited even if a carrier signal occurs during preparation for transmission. Moreover, it is possible to provide a bus access control device that can quickly perform preparations for retransmission.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a detailed configuration of a driver control unit according to an embodiment.

FIG. 2 is a block diagram showing a conventional device.

FIG. 3 is a block diagram showing the entire apparatus of the embodiment.

FIG. 4 is a time chart of the edge detection / timing generation unit according to the embodiment.

FIG. 5 is a time chart of a post flag counter according to the embodiment.

FIG. 6 is a block diagram showing a detailed configuration of a window unit of the embodiment.

FIG. 7 is a block diagram illustrating a detailed configuration of an unsuccessfulness determination / driver ON determination unit according to the embodiment.

FIG. 8 is a time chart (No. 1) of the failure determination / driver ON determination unit and the like in the embodiment.

FIG. 9 is a time chart (No. 2) of the failure determination / driver ON determination unit and the like in the embodiment.

FIG. 10 is a time chart (No. 1) of the front flag counter according to the embodiment.

FIG. 11 is a time chart (No. 2) of the front flag counter according to the embodiment.

FIG. 12 is a flowchart showing the processing of the CPU hardware of the embodiment.

FIG. 13 is a time chart (No. 1) illustrating the overall processing of the embodiment.

FIG. 14 is a time chart (No. 2) explaining the overall processing of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Unsuccessful determination / driver ON determination unit, 2 ... Window unit, 3 ... Edge detection / timing generation unit, 4 ... Prefix flag counter, 5 ... Postfix flag counter, 6 ... AND gate, 7 ... I / O port , 8 ... Failure holding unit, 9 ... Edge detection unit, 25 ... CPU hardware, 26 ... Communication LS
I, 27 ... Driver, 28 ... Receiver, 29 ... Carrier detection unit, 30 ... Driver control unit, S ... LAN bus.

Claims (2)

[Claims] 1. A bus access control device for placing a transmission signal from the own node on the network bus on condition that there is no carrier signal on the network bus common to a plurality of communication nodes, and controls communication processing of the own node. Communication control means, a communication means for converting a signal from the communication control means into a transmission signal to be put on a network bus and outputting the transmission signal, and a passage or non-passage of the output transmission signal from the communication means to the network bus. Driver means for controlling according to a driver control signal, carrier detecting means for detecting the presence of a carrier signal on the network bus, and communication means from the communication control means or the communication means from the time when the communication means is started. The window period is until the significant change of the transmission request signal, and the significant period is changed during this window period. A) When the detection signal is given, it is determined that the transmission is unsuccessful, and in other cases, it is determined that the transmission is successful, and in accordance with the determination result, a transmission permission signal for returning to the transmission request signal, and the driver means. And a driver control means for forming an unsuccessful notification signal for notifying the communication control means when the transmission is unsuccessful, and a bus access control device. 2. The bus access control device according to claim 1, wherein the bus access control device is provided in any one of the communication nodes of a network that requires a flag pattern before a transmission signal body to be transmitted to the network bus. Bus access, characterized in that the control means is provided with a portion for causing the communication means to immediately output the transmission signal main body at the time of transmission failure determination, and for deleting a time conceivable to the prefix flag time at the time of transmission success determination Control device.