JPH08286999A - Semiconductor integrated circuit device and computer system using the same - Google Patents

Abstract

(57) [Abstract] [Objective] A semiconductor integrated circuit capable of performing data transfer by a data transfer device or a data transfer control device in parallel with the processing by the data processing device while minimizing the deterioration of the processing performance of the data processing device by the CPU. Provide a device. [Configuration] CPU, DTC, ROM, RAMI, RAM
P, timer as I / O, pulse output circuit, SCI,
A / D and IOP1-11, interrupt controller, BS
A microcomputer including functional blocks such as C, which includes an internal address bus IAB and a data bus I
DB is connected to CPU, ROM, RAMI, BSC,
Internal address bus PAB and data bus PDB are BSC,
It is connected to RAMP, I / O, and interrupt controller, and when BAB does not connect IAB, IDB to PAB, PDB, between ROM read / write by CPU and RAMP and I / O by DTC. Data transfer is performed in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a semiconductor integrated circuit device suitable for a microcomputer having a data processing device and a data transfer device by a central processing unit or a data transfer control device, and the semiconductor integrated circuit device. The present invention relates to a technique effectively applied to a used computer system.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, a microcomputer is "LSI Handbook" P540 and P issued by Ohmsha, Ltd. on November 30, 1984.
As described in 541, a central processing unit (CPU) is central to a program holding ROM (read only memory), a data holding RAM (random access memory), and an input / output for inputting / outputting data. There is one in which functional blocks such as an output circuit are formed on one semiconductor substrate.

A direct memory access controller (DMAC) is built in such a microcomputer,
Incorporated with data transfer independent of CPU,
March, "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. or Japanese Patent Application No. 4-137954. Such a DMAC can be activated by an interrupt request, can perform a repeat mode, a block transfer mode, and the like, and is suitable for control of a stepping motor and print data control of a printer. In such an example, transfer of up to 8 channels can be performed. Since the DMAC transfer is independent of the CPU, only the bus cycle required for data transfer is C
It suffices to stop the PU, and the CPU can continue the processing being executed except the bus cycle.

However, since the CPU and the DMAC commonly use the bus, the CPU cannot use the bus during the operation of the DMAC, and the CPU is substantially stopped. As one of the methods for reducing the stop ratio, a so-called single address mode DMA can be executed.
There is C. Such a DMAC includes, for example, "SH7032, SH7034" issued by Hitachi, Ltd. in March 1993.
Hardware Manual ”P149 to P181.

In such a single address, an external device is selected by outputting a dedicated acknowledge signal, and data transfer is performed with an external memory selected in a normal bus cycle. In the traditional way,
The operation of sequentially reading the transfer source address and writing the transfer destination address can be performed in one bus cycle. That is, the frequency at which the DMAC uses the bus is set to 1
It can be set to / 2, the rate at which the CPU must be stopped can be set to about 1/2, and it is considered that the decrease in the processing speed of the CPU can be alleviated.

[0006]

However, in the technique for reducing the rate of stopping by the DMAC capable of executing the single address mode as described above, the data transfer to the built-in input / output circuit uses the single address transfer. Transfers are getting harder. That is, the acknowledge signal output from the microcomputer can be arbitrarily connected to the external device depending on the user's board design, but the signal inside the microcomputer must be fixed. .

On the other hand, in the input / output circuit of the microcomputer, generally, there are not necessarily many registers to which data is transferred. The constant register of the timer, the next data register of the pulse output device, the transmission data register / reception data register of the serial communication interface (SCI), the data register of the A / D converter, and the like.

Therefore, an object of the present invention is to enable the data transfer by the data transfer device or the data transfer control device in parallel with the processing by the data processing device while minimizing the deterioration of the processing performance of the data processing device by the CPU. It is an object of the present invention to provide a microcomputer or a semiconductor integrated circuit device which can be used and a computer system using the same.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention has the first storage means for storing the program of the data processing device, the second storage means and the data input / output means built therein, and also has the data transfer device built therein. This data transfer device has a bus control means for designating a single address transfer between the second storage means and the data input / output means, and is independent of the read of the first storage means by the data processing device. The storage means and the data input / output means can be connected.

In this case, an acknowledge signal peculiar to a part of the register means of the data input / output means is provided, and reading or writing of the register means is performed in response to the acknowledge signal, and the data transfer device is further provided. Has an interrupt control means for designating which acknowledge signal is activated, and the first of the data processing devices is provided during the single address data transfer of the data transfer device.
This makes it possible to read the program from the storage means.

Further, in another semiconductor integrated circuit device of the present invention, a data transfer control device is incorporated instead of the data transfer device, and the second data processing device is independent of the read of the first storage means by the data processing device. The storage means and the data input / output means can be connected so that the program can be read from the first storage means of the data processing device during part or all of the single address data transfer of the data transfer control device. .

Further, the computer system of the present invention is
At least an auxiliary storage device, a display device, and an input / output device are connected around the semiconductor integrated circuit device.

[0015]

According to the semiconductor integrated circuit device and the computer system using the same, the data transfer device or the data transfer control device gives an independent acknowledge signal to the data input / output means without designating an address. Since the data input / output means is read / written by the second storage means at the same time, the address signal and the write signal / read signal are given to the second storage means, and the second storage means is written / read. By connecting the input / output means, data can be transferred between the second storage means and the data input / output means in one bus cycle, so that the processing speed can be increased.

At this time, since the data processing device can read the program from the first storage means, the frequency of stalling of the data processing device due to such data transfer can be reduced, and the data processing device and the data processing device The transfer device or the data transfer control device operates simultaneously, so that the processing speed of the microcomputer or the semiconductor integrated circuit can be improved.

Further, since there are not many register means of the data input / output means for data transfer, it is not necessary to make the acknowledge signal or the bit of the register means for designating the acknowledge signal so large.

Furthermore, whether to perform single address transfer,
By having the means for designating whether to perform the dual address transfer, the data transfer can be performed even to the data input / output means having no acknowledge signal.

In this case, in order to increase the frequency at which the data processing device and the data transfer device or the data transfer control device operate simultaneously, the first other storage means is provided, and the data input / output means and the second storage means are provided. Independent of the data transfer of the storage means, the data processing device reads / writes the second storage means.
It is preferable that the data can be written, and even when the data processing device saves / restores the stack in response to an interrupt or the like, parallel operation becomes possible.

As a result, the data transfer by the data transfer device or the data transfer control device can be performed in parallel with the processing by the data processing device while minimizing the deterioration of the processing performance of the data processing device. It can be favorably applied to the improvement of the processing performance of a computer system centering on a semiconductor integrated circuit device.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a main part of a microcomputer which is an embodiment of the present invention, and FIG. 2 is an explanatory view showing a configuration of an address bus and a data bus in the microcomputer of this embodiment. 3, FIG. 3 is an explanatory diagram showing an address map, FIGS. 4 to 10 are block diagrams and explanatory diagrams showing details, FIG. 11 is an explanatory diagram showing an example of an operating state of a bus, FIG. 12 is a flowchart showing an operation of a DTC, FIG. 13 is a timing chart showing an example of single address data transfer, and FIG. 14 is a block diagram showing a specific configuration of the read / write control circuit of the input / output circuit (I / O).

First, the configuration of the microcomputer of this embodiment will be described with reference to FIG.

The microcomputer of this embodiment includes, for example, a central processing unit CPU (data processing unit), a data transfer controller DTC (data transfer unit), a read only memory ROM (first storage means), a random access memory RAMI (first storage unit). 1 other storage means), random access memory RAMP (second storage means), timer, pulse output circuit, serial communication interface SCI, A / D converter A / D, input / output ports IOP1 to IOP11, interrupt controller. (Interrupt control means), a bus controller BSC (bus control means), a clock oscillator CPG, and other functional blocks (or modules), and a timer is composed of two parts, a timer A and a timer B.

These functional blocks are connected to each other by an internal bus. The internal bus includes a read signal / write signal, not shown, a bus size signal, and a system clock in addition to an address bus and a data bus.
The internal address bus is IAB (first bus), DTA
B and PAB (second bus) exist. The internal data bus includes IDB (first bus) and PDB (second bus). These buses are interfaced by the bus controller BSC.

IAB and IDB are CPU, ROM and RAM
I, BSC, and IAB are connected to IOP1 to IOP3 to serve as an external bus address bus.
Is connected to IOPs 4 and 5 to serve as a data bus for the external bus. PAB and PDB are connected to BSC, RAMP, timer, pulse output circuit, SCI, A / D converter, interrupt controller, IOP1 to 11, and PDB is connected to DTC. DTAB connects DTC and BSC. RAMI is connected to IAB and IDB,
RAMP is different in that it is connected to PAB and PDB.

The CPU and DTC can use the internal bus as a so-called bus master. ROM, RAM
I, RAMP, and timer, pulse output circuit, SC
Each functional block of the I, A / D converter, IOP1-11 and interrupt controller is a CPU or D as a bus slave.
Read / write by TC.

The interrupt controller is a timer, SCI, A
The interrupt signal output from the / D converter and the input / output port (IOP11) is input, the interrupt request signal is output to the CPU, and the activation request signal is output to the DTC. Also, the clear signal output from the DTC is input and the interrupt clear signal is output.

The input / output port is also used as an external bus signal and an input / output signal of the input / output circuit. IOP1-3 are address bus outputs, IOP4, 5 are data bus input / output, IOP
OP6 is also used as a bus control signal input / output signal. The external address and the external data are connected to the IAB and IDB via the buffer circuits included in these input / output ports, respectively. PAB and PDB are used to read / write the register of the input / output port and have no direct relation with the external bus.

The bus control signal output includes address strobe, high / low data strobe, read strobe,
There are write strobe, bus acknowledge signal, etc.
Bus control input signals include wait signals and bus request signals. These input / output signals are not shown.
External bus expansion is selected by operating mode,
The functions of these input / output ports are also selected.

IOP7 is a timer input / output and IOP8
Is also a pulse output, IOP9 is an SCI input / output, IOP10 is an analog input, and IOP11 is also used as an external interrupt request (IRQ) input. Input / output signals of the timer, SCI, A / D converter and IOP7, IOP9, IOP10 are not shown.

Besides, power supply terminals Vcc, Vss, analog power supply terminals AVcc, AVss, reset input RE
S, standby input STBY, interrupt input NMI, clock inputs EXTAL, XTAL, operation mode input MD0,
There are input terminals such as MD1 and MD2.

The timer comprises two parts, timer A and timer B.

Next, the connection state of the address bus and data bus of such a microcomputer will be described with reference to FIG.

As described above, the input / output circuit I / O (data input / output means) includes the timer, pulse output circuit, SC shown in FIG.
Includes registers for I, A / D converters, I / O ports, interrupt controller. Functional blocks (or modules) not connected to a bus such as CPG are omitted.

As an address bus, CPU, ROM, R
AMI, IAB connecting to the outside, DT output from DTC
There is a PAB that connects AB, RAMP, and I / O. The address bus is interfaced with the bus controller BSC.

As a data bus, CPU, ROM, RA
MI, IDB for external connection, DTC, RAMP, I /
There is a PDB that connects O. Such data bus IDB,
The PDB is interfaced with the bus controller BSC. If necessary, the IDB and PDB are connected to input / output data.

An independent acknowledge signal is applied from the DTC to the I / O. Since the acknowledge signal corresponds to the register included in I / O,
There are cases where a plurality of acknowledge signals are given to one functional block (or module).

IAB and IDB are buffer circuits BU.
It is connected to the external bus via F. The buffer circuit BUF is included in IOPs 1 to 5.

Next, the address map of the microcomputer will be described with reference to FIG.

The address space is 16 Mbytes, and an address is assigned for each byte. Each functional block has a unique address in the address space of the CPU, regardless of the connected bus. The I / O includes the timer of FIG. 1, the pulse output circuit, the SCI, the A / D converter, the input / output port, and the register of the interrupt controller.

The ROM is not particularly limited, but 3
Addresses from H'000000 to H'00
7FFF, RAMI is 1k bytes, H'FFF78
0 to H'FFFB7F and RAMP are 1 kbytes, and addresses H'FFFB80 to H'FFFF7F and I / O are arranged at addresses H'FFFF80 to H'FFFFFF. H'represents a hexadecimal number.

The vector address of the CPU is in the ROM,
The vector address of DTC is arranged in the area of RAMP.

Next, the register configuration of the DTC will be described with reference to FIG.

The DTC registers are a 32-bit vector address register VAR, a 16-bit mode register DTMR, and a block transfer count register B.
It comprises a TCR, a transfer count register TCR, a source address register SAR, and a destination register DAR. The transfer count register is 8 bits high (T
CRH) and lower (TCRL).

VAR, SAR, and DAR have a length of 24 bits and can specify the entire 16 Mbyte address space area. The upper 8 bits are not regarded as an address, and an acknowledge signal for single address transfer is selected.

BTCR and TCR have a 16-bit length,
Up to 64k transfers can be specified. Maximum value is H'000
0 and considered as 65536.

In these registers, one set of circuits has DTC.
Exists in the CPU and is not particularly limited, but does not exist in the CPU address space. The transfer information to be stored in these is the DTC vector address for VAR, and for the other registers, the required number of sets is the address indicated by the contents of VAR in the CPU address space, for example R.
Placed in AMP. It is also possible to arrange in a memory other than RAMP.

Further, by having only one set of registers in the DTC and reading the registers from the RAMP or the like prior to transfer, the logical scale and physical scale of the DTC can be reduced. By placing a register in RAMP or the like, the restriction on the number of channels that can be supported can be virtually eliminated.

Next, the bit configuration of the DTMR will be described with reference to FIGS.

Bit 15 is an SNG bit and designates single address mode or dual address mode. When the SNG bit is set to "1", the single address mode is set, and when it is cleared to "0", the dual address mode is set.

Bit 14 is a SEL bit and designates the transfer direction in the single address mode. When the SEL bit is cleared to "0", data is transferred from the RAM to the input / output circuit and DAR becomes invalid. When the SEL bit is set to "1", the R
Data transfer to AM and SAR becomes invalid.

Bit 13 is an SZ bit, and selects whether to perform one data transfer in byte size or word size. When the SZ bit is cleared to "0", byte size data transfer is performed, and when it is set to "1", word size data transfer is performed. The word size is 2 bytes.

Bit 11 and bit 10 are MD1 and MD0
This is a bit and selects the data transfer mode in the case of dual address mode.

When the MD1 and MD0 bits are cleared to "0", the normal mode is set. In the normal mode, one data transfer is performed from the address indicated by SAR to the address indicated by DAR by one activation. After this, SM
S based on 1, SM0, DM1, DM0 bit designation
The AR and DAR are operated and the TCR is decremented. This is repeated the number of times specified by the TCR each time an activation factor occurs. When the data transfer of the number of times specified by the TCR is completed, the DTC operation is prohibited, and the CPU, which is the interrupt causing the activation, is requested.

When MD1 is cleared to "0" and the MD0 bit is set to "1", the repeat mode is set. In the repeat mode, one data transfer is performed from the address indicated by SAR to the address indicated by DAR by one activation. The number of transfers is specified by 8-bit TCRH and TCRL. After data transfer, SAR and DAR operations are performed based on the designation of SM1, SM0, DM1, and DM0 bits.
TCRH is decremented. This is repeated the number of times specified by TCRH each time an activation factor occurs. TC
When data transfer for the number of times specified by RH is completed, TC
SAR or DAR, T based on the contents held in RL
The default value of CRH is restored. The transfer is repeated until the CPU prohibits the interrupt that causes the activation or the DTC.

When MD1 is set to "1" and the MD0 bit is cleared to "0", the block transfer mode is set. In the block transfer mode, data is transferred a plurality of times from the address indicated by SAR to the address indicated by DAR by one activation. BTCR is decremented. The number of data transfers performed at one start-up is 8-bit TCRH, TC
Specify by RL. BTC is set every time a start factor occurs.
Repeat the number of times specified by R. When the data transfer for the number of times specified by BTCR is completed, the DTC operation is prohibited, and the CPU that is the cause of the interrupt is requested.

Setting the MD1 and MD0 bits to "1" is a system reservation and is prohibited.

Bit 9 is a DTS bit, and selects either the source side or the destination side as the repeat area or the block area in the repeat mode or the block transfer mode. When the DTS bit is set to "1", it becomes the source side, and when it is set to "0", it becomes the destination side.

Bits 7 and 6 are SM1 and SM0 bits, and specify whether the SAR is incremented, decremented, or fixed after data transfer. S
When the M1 bit is cleared to "0", the SAR is fixed. With the SM1 bit set to "1", SM0
Increment when bit is cleared to "0", SM0
When the bit is set to "1", decrement is performed.

Bits 5 and 4 are DM1 and DM0 bits, and specify whether DAR is incremented, decremented, or fixed after data transfer. D
When the M1 bit is cleared to "0", DAR is fixed. With the DM1 bit set to "1", DM0
Increment when bit is cleared to “0”, DM0
When the bit is set to "1", decrement is performed.

Bit 3 is an NXTE bit and selects whether data transfer should be ended or the next data transfer should be performed for one activation factor. When the NXTE bit is cleared to "0", after reading the register file and transferring the data, the register file is written and the DTC operation is completed. With the NXTE bit set to "1", after reading the register file and transferring the data, the register file is written, the register file is read from consecutive addresses, and the data transfer specified in this register file is performed. Write the register file.

The contents of the data transfer operation in the repeat mode and the block transfer mode are substantially the same as those in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993 or Japanese Patent Application No. 4-137954. Is.

Next, the block configuration of the DTC will be described with reference to FIG.

Control circuit, data buffer DB, address buffer AB, decoder DEC, bus interface M
IF, DTMR, BTCR, TCR, DAR, SAR,
Each block includes a VAR, an arithmetic operation circuit AU, a selector, a shifter, and a vector address generation circuit VAG. These blocks are A bus, B bus, C bus, and IF bus.
The books are bound by the internal bus.

The acknowledge numbers are SAR and DAR.
Stored in the upper 8 bits (bits 31-24) of the.

Acknowledge signals 0-32 are output. The decoder DEC decodes and outputs which acknowledge signal is to be output, according to the designation of the bits 31-24 of the SAR or DAR.

Next, referring to FIG. 8, the DTC register 1
The configuration on the memory for the set will be described.

The vector address register VAR is stored in a DTC vector address unique to each activation factor.

The content (m) of the vector address register is
Mode register DTMR, block transfer count register BTCR, transfer count register TCR, source address register SAR, destination register DA
It is the start address of the area where R exists. These addresses are a continuous area of addresses m to m + 13.
VAR, SAR, and DAR are 24 corresponding to the address space.
Although the bits are valid, the upper 8 bits (bits 31-24) are reserved because they are stored in units of 32 bits.

In the single address mode, since SAR or DAR is not required, it is arranged at addresses m to m + 9. Upper 8 bits of DAR or SAR (bit 3
The acknowledge number is designated in 1-24).

When the DTC is activated, the contents of VAR are read from the DTC vector address unique to the activation factor. Next, the contents of VAR are incremented and sequentially read from DTMR. If the SNG bit is cleared to "0", 14 bytes are read, and if the SNG bit is set to "1", 10 bytes are read. At the end of reading, the VAR in the DTC holds the initial value (m).

After the data transfer, the contents of VAR are incremented and written from DTMR to the address of the forward dimension.
If the SNG bit is cleared to "0", 14 bytes are written, and if the SNG bit is set to "1", 10 bytes are written. At the end of writing, the VAR in the DTC holds the address next to the last address. Note that each register is in units of 16 bits,
Since the internal bus has a 16-bit configuration, the increment is +2.

When the NXTE bit of DTMR is set to "1", after the completion of one transfer, the next data transfer is performed by the same activation factor. The register for the next data transfer is arranged at an address continuous with the register.

The NXTE bit of the second DTMR is set to "1".
When set to, the next register is placed. Similarly, the following registers are arranged until the NXTE bit of DTMR is cleared to "0".

Next, the schematic block configuration of the interrupt controller will be described with reference to FIG.

There are two types of interrupt factors, an internal interrupt and an external interrupt, each having an interrupt factor flag. The internal interrupt factor flag is set to "1" when the input / output circuit of the timer / SCI / A / D converter is in a predetermined state.
The external interrupt factor flag is set to "1" when the external interrupt input terminal reaches a predetermined level or when a predetermined signal change occurs. The interrupt factor flag is cleared to "0" by the write operation of the CPU, and the DTC
It is cleared to "0" when the transfer is completed.

The output of each bit of the interrupt factor flag is input to the interrupt permission circuit. The contents of the interrupt enable register, that is, the interrupt enable bit is further input to the interrupt enable circuit. The interrupt permission register is a register readable / writable by the CPU and selects whether to permit or prohibit the corresponding interrupt. If the interrupt factor flag is set to "1" and the interrupt enable bit is set to "1", an interrupt is requested. That is, the interrupt permission circuit is composed of a logical product circuit to which the corresponding interrupt factor flag and interrupt permission bit are input.

The output of the interrupt permission circuit is input to the interrupt / DTC determination circuit. The contents of the DTC enable register are further input to the interrupt enable circuit. As described above, the DTC enable register selects whether to activate the DTC or allow the CPU to interrupt when an interrupt is requested. If the bit of DTC enable register is set to "1", DTC
Is requested, and no CPU interrupt is required. DT
When the bit of the C permission register is cleared to "0", the CPU interrupt is requested and the DTC activation is not requested. That is, the interrupt / DTC determination circuit is composed of a logical product circuit of the corresponding interrupt signal and the DTC enable bit, and a logical product circuit of the interrupt signal and the inverted signal of the DTC enable bit. The output of the former AND circuit is the DTC activation request signal, and the output of the latter AND circuit is the CPU interrupt request signal.

As for the output of the DTC enable circuit, the CPU interrupt request and the DTC activation request are independently input to the priority determination circuit. The output of the priority register is also input to the priority determination circuit. The priority register sets, for example, two levels of priority for each group of interrupt factors.

The priority is determined for each of the CPU interrupt request and the DTC activation request. As a result of the determination, the highest priority is selected, the vector number is generated, and the CPU
Request signals for the interrupt request and DTC activation request and vector numbers are output.

The CPU interrupt request signal and the vector number are input to the mask level determination circuit. The interrupt mask bit of the CPU is further input to the mask level determination circuit. If the requested interrupt is below the CPU interrupt mask level, it is suspended.

When the interrupt request signal to the CPU becomes active, the CPU starts interrupt exception processing at the end of the instruction being executed, extracts the branch destination address from the vector address corresponding to the vector number, and executes the interrupt processing. Branch to the routine.

Regarding the priority determination and the interrupt mask level, "H" issued by Hitachi, Ltd. in March 1993 is used.
8/3003 hardware manual ”or Japanese Patent Application No. 4-137955, and the detailed description thereof will be omitted.

The DTC activation request is input to the DTC. D
The TC vector number is input to the latch circuit. A DTC start signal and a DTC transfer end signal are output from the DTC,
It is input to the latch circuit. When the DTC starts operating,
The DTC activation signal is activated and latched. D
When the TC data transfer is completed, the DTC transfer end signal becomes active and the latch is released. Therefore, the DTC vector number output from the latch circuit is held during the DTC operation.

Further, the DTC vector number and the DTC transfer end signal are input to the decoder circuit. The factor clear signal is activated for the corresponding interrupt factor flag and the factor flag or the DTE bit is cleared.

Next, the schematic block configuration of the bus controller will be described with reference to FIG.

The bus controller includes a data bus buffer circuit, an address bus buffer circuit, an address determination circuit,
It consists of a bus arbitration circuit and a sequencer. The sequencer controls the data bus buffer circuit and the address bus buffer circuit.

The CPU outputs a CPU bus right request signal, a CPU read request signal, a CPU write request signal, and an IAB, and inputs a CPU bus right acknowledge signal, a CPU wait signal, and an IAB release signal to operate.

Similarly, DTC is a bus request signal, DTC.
Read request signal, DTC write request signal, and DTA
B is output, and the DTC bus acknowledge signal and the DTC wait signal are input to operate. In addition, it outputs a data strobe signal of a CPU or DTC (not shown) or a control signal of a data buffer. Since such a signal can be roughly the same as that in Japanese Patent Application No. 4-137954, detailed description thereof will be omitted.

When either the CPU or the DTC requests the bus right, the bus right acknowledge signal is activated to give the bus right. When both the CPU and DTC request the bus right, the address determination and the bus right arbitration are performed. IAB output by CPU, DT output by DTC
AB is input to the address determination circuit.

CPU is ROM, RAMI, external IDB
When reading / writing the memory or register (IDB side) connected to, and when the DTC reads / writes the memory or register (PDB side) connected to the PDB of RAMP, I / O, both CPU and DTC Give bus rights to.

The CPU reads / writes the memory or register (PDB side) connected to the PDB of RAMP and I / O, or DTC is ROM, RAMI, and external IDB.
When reading or writing the memory or register (IDB side) connected to, the bus right is arbitrated. IDB
Side, when both bus cycles on the PDB side are completed,
The bus right is given to either the DTC or the CPU.
Since the DTC sets the priority of the bus right higher than that of the CPU, if the DTC requests the bus, the bus right is given to the DTC.

For example, if the CPU requests read / write on the PDB side while the DTC is reading / writing on the PDB side, bus arbitration is suspended until the DTC finishes the read / write. Further, since the DTC has a higher priority, the CPU is in a standby state until the DTC relinquishes the bus right.

When the bus right is given, the IDB side, PDB
A read or write bus cycle is activated on one or both sides.

When the CPU is reading / writing the IDB side and the DTC is reading / writing the PDB side, the data bus buffer circuit is in the release state, and the IDB and PDB data are independent of each other. The address bus buffer circuit outputs the contents of DTAB to PAB.

When the CPU is reading the PDB side, the buffer from the PDB to the IDB is turned on.
Further, the address bus buffer circuit sets the content of IAB to PA
Output to B.

When the CPU is writing on the PDB side, the buffer from the IDB to the PDB is turned on.
Further, the address bus buffer circuit sets the content of IAB to PA
Output to B.

When the DTC is reading the IDB side, the buffer from the IDB to the PDB is turned on.
Further, the address bus buffer circuit changes the contents of DTAB to I
Output to AB. An IAB release signal is given to the CPU, and the CPU's IAB output is released.

When the DTC is writing on the IDB side, the buffer from the PDB to the IDB is turned on.
Further, the address bus buffer circuit changes the contents of DTAB to I
Output to AB. Similarly to the above, the CPU is supplied with the IAB release signal, and the IAB output of the CPU is set to the release state.

Next, an example of the operating state of the bus will be described with reference to FIG.

When the CPU reads the program from the ROM or reads / writes the data with RAMI, the operation is performed using IAB and IDB. Although not shown, the external bus can be read / written similarly via the buffer circuit. The CPU does not use PAB or PDB.

At this time, read / write of RAMP by DTC, read / write of I / O, and data transfer between RAMP and I / O are performed using DTAB, PAB, and PDB. The content of DTAB is output to PAB. The PDB and IDB are separated. DTC is IAB,
Do not use IDB. That is, data transfer can be performed without stopping the operation of the CPU.

When performing single address transfer between RAMP and I / O, the address of RAMP is output to DTAB and PAB, and the I / O register is selected by the acknowledge signal.

When the CPU reads / writes ROM or RAMI or the outside and the DTC reads / writes RAMP or I / O, the CPU and DTC can operate in parallel.

Next, the operation flow of the DTC will be described with reference to FIG.

The CPU previously writes the start address (m) of the register file to the DTC vector address on the RAMP, and the initial value of the register file from this address (m). After that, the enable bit of the interrupt factor is set to "1" and the DTC enable bit is set to "1".

When the DTC is activated by the occurrence of a predetermined interrupt request with the DTC enable bit set to "1", first in step 1 (S1), the vector address corresponding to the activation factor is changed to the vector address. The contents of the address register (VAR) are read and stored in a predetermined register inside the DTC. After reading, the state becomes one-state standby state or internal processing state.

At step 2 (S2), the mode register D is read from the address indicated by the contents of the vector address register.
TMR, block transfer count register BTCR, transfer count register TCR, source address register SA
The R and destination registers DAR are sequentially read and stored in a predetermined register inside the DTC. As described above, if the SNG bit of DTMR is set to "1", only one SAR / DAR is read. After reading, the state becomes the 1-state standby state or the internal processing state as described above.

In step 3 (S3), data transfer is performed according to the contents of the read register. In the single address mode, the data transfer source read and the data transfer destination write are performed in one bus cycle. In the dual address mode, the data transfer source read and the data transfer destination write are performed in independent bus cycles. In the dual address mode, the transfer data is temporarily stored in the data buffer DB of the DTC. Along with this, the contents of the register are updated. Data transfer is performed once in the normal mode and the repeat mode. In the block transfer mode, transfer is performed the number of times specified by TCRH and CRL. After the data transfer, the standby state of 1 state or the internal processing state is obtained as described above.

At step 4 (S4), the contents of the register are stored in the original address. At this time, if the NXTE bit is set to "1", the process returns to step 1 (S1), and DTMR, BTCR, TC
R, SAR, and DAR are sequentially read, and the above operation is repeated.

When the NXTE bit is cleared to "0", the operation of DTC is stopped. The content of the transfer counter is 0
If not, the factor clear signal is activated and the interrupt factor flag is cleared to "0" via the interrupt controller.
When the content of the transfer counter is 0, the interrupt factor is not cleared and the DTC enable bit is cleared to "0". The transfer counter is TCR in the normal mode, TCRH in the repeat mode, and BTC in the block transfer mode.
R is used.

After the DTC operation is stopped, the DTC enable bit is cleared to "0" and the interrupt factor is held, so C
The PU interrupt exception handling is executed and the interrupt handling routine is executed. It is necessary to clear the interrupt factor flag to "0" in the interrupt processing routine of the CPU.

The CPU indicates that the transfer by the DTC is completed, especially the registers arranged on the RAM, especially the BTCR.
Alternatively, it can be known by reading the TCR and confirming that the content is 0.

When the CPU reads / writes the PDB side during the operation of DTC, the CPU is temporarily stopped,
As described above, even when the DTC is operating, the bus is released at the break of the operation step, so that it is possible to avoid the CPU from being stopped for a long time. At least, the CPU can operate at the breaks in the operation steps of the DTC except when reading / writing the PDB side continuously. By using the single address mode, the bus cycle required for reading / writing and transferring the contents of the register can be reduced, and the period during which the CPU is stopped can be shortened.

In order to effectively utilize such parallel operation, it is advisable to perform data transfer by DTC between RAMP and I / O. Further, it is preferable that the instructions of the CPU are arranged in the ROM and the work area is arranged in the RAMI. In the CPU bus cycle, reading instructions is more frequent than reading / writing data, so DTC by the CPU
Except for the initial setting of I / O and C, including the case of processing the data stored in RAMP after the end of DTC transfer,
The frequency of read / write of RAMP and I / O by PU is reduced, the decrease of processing speed is reduced, and
And the DTC can operate at the same processing speed as the parallel operation. The processing speed can be improved as compared with the prior art.

Next, an example of the operation timing of the internal bus will be described with reference to FIG. Note that FIG. 13 shows an example of performing data transfer in the single address / normal mode from the RAMP to the I / O.

IAB and DTAB are output in synchronization with φ # which is an inverted signal of φ. CPU ROM and RA
Reading to MI is performed in one state. IAB is output in one state in synchronization with φ #, and is not particularly limited, but is latched in ROM and RAMI in synchronization with φ. The read data corresponding to this is output in synchronization with φ #, and is taken into the CPU while φ is active.

For example, data for an address output to IAB in synchronization with φ # of T1 is output to IDB in synchronization with φ # of T2, and C is output while φ of T3 is active.
Captured by PU.

Read signal MR for ROM and RAMI
DN is activated (low level), and the read cycle is repeated. The ROM or RAMI is read corresponding to the address indicated by IAB.

On the other hand, read / write for RAMP is performed in two states, and read / write for I / O is performed in two states. IAB or DTAB synchronized with φ #
Is synchronized with φ by the bus controller and output to PAB.

The interrupt controller activates the DTC activation request signal to activate the DTC. When activated, the DTC activates the activation signal. This latches the DTC vector number of the interrupt controller.

The DTC activates the DTC bus right request signal and outputs the DTC vector address generated by VAG to DTAB via the A bus. The contents of the A bus are taken into AU and incremented.

When the DTC bus acknowledge signal DTAC is activated, the contents of DTAB are synchronized with φ and set to P.
It is output to AB and RAMP is read by DTC. DAR via BUS increment result via B bus
Stored in.

VAR read from RAMP to PDB
The contents (mH) of the upper 16 bits of are stored in the DTC data buffer (DB). Contents of DAR (DTC
The vector address + 2) is output to DTAB via the A bus. Hereinafter, the vector address and the register information are sequentially fetched. These timing diagrams are omitted.

Based on the register information, single address transfer from the RAM to the I / O is performed in the 2-state period from T2 in FIG.

As described above, DTAB output in synchronization with φ # of T1 is output to PAB in synchronization with φ of T2. The read signal IORDN for RAMP (or I / O) becomes active in synchronization with φ # of T2, and PAB
The data of RAMP shown in is output to PDB. At the same time, of the DTC acknowledge signals DTAC, the designated signal becomes active and the internal register of the I / O is selected, and the PD of the internal register corresponding to IORDN is selected.
The contents of B are written.

The register information is written to the RAMP from T4. The content of DTAB is output to PAB in synchronization with φ of T5. RAMP and I / in synchronization with φ # of T5
The write signal IOWRN for O becomes active and P
The contents of PDB are written to RAMP shown in AB.

Next, referring to FIG. 14, a block configuration of an example of read / write control of the register of the input / output circuit will be described.

The registers to which the acknowledge signal is assigned are, for example, the next data register of the pulse output circuit, the time constant register or output compare register of the timer, the input capture register, the reception data register of SCI, and the transmission data register, There are data registers of the A / D converter.

The contents of PAB are input to the address decoder, and the selection signal is activated when the address where such a register exists is reached. Instead of inputting all the bits of the PAB, for example, the bus controller may decode the module select signal or the functional block signal previously decoded and a part of the PAB.

The read signal of the register is the output of the AND circuit, and the input of the AND circuit is the output of the two OR circuits. One of the OR circuits is used as an inverted signal of the selection signal and the read signal IORDN.
The other of the OR circuits serves as an acknowledge signal output from the DTC and an inverted signal of the write signal IOWRN. The read signal is output to the PDB via a clocked buffer that uses the read signal as a clock.

The write signal of the register is the output of the logical product circuit, and the input of the logical product circuit is the output of the two logical sum circuits. One of the OR circuits is an inverted signal of the selection signal and the write signal IOWRN.
The other of the OR circuits is an inverted signal of the acknowledge signal output from the DTC and the read signal IORDN. The contents of PDB are input through a clocked buffer that uses this write signal as a clock.

That is, when the acknowledge signal is selected during the single address data transfer, IORDN is selected.
The operation opposite to that specified by the IOWRN signal is performed. The IORDN and IOWRN signals are negative logic signals.

Therefore, according to the microcomputer of the present embodiment, the ROM and RAM for storing the program of the CPU
And an input / output circuit, and a DTC.
C designates a single address transfer between the RAM and the input / output circuit, enables the RAM and the input / output circuit to be connected independently of the ROM reading by the CPU, and further provides a unique acknowledge signal to the register of the input / output circuit. By the DTC specifying whether to activate the acknowledge signal, the following operational effects can be obtained.

(1). Since the DTC gives an independent acknowledge signal to the input / output circuit to read / write the input / output circuit without designating an address, the address signal and the write signal / read signal are simultaneously sent to the RAM. (RAM
P) to write / read the RAM, the RAM and the input / output circuit are connected to each other, and RA is performed by one bus cycle.
Data can be transferred between M and the input / output circuit, and the speed can be increased. The time from the occurrence of a DTC activation factor such as an interrupt to the actual end of data transfer can be shortened, and the control accuracy of the device controlled by the microcomputer can be improved.

Without having a register inside the DTC,
The number of CPU stalls is reduced or the period is shortened while reducing the logical size and physical size of the DTC and enjoying the merit of the DTC that virtually eliminates the restriction of the number of transfer channels that can be executed. Therefore, the overall processing performance of the microcomputer can be improved.

(2). Since the CPU can read the program from the ROM, the frequency of stall of the CPU due to the data transfer can be reduced. CPU
The simultaneous operation of the DTC and the DTC can improve the processing speed of the microcomputer or the semiconductor integrated circuit.

(3) By reducing the number of registers of the input / output circuit to which data is transferred, it is not necessary to increase the acknowledge signal or the bits of the register for designating the acknowledge signal. The increase in the physical size of the microcomputer due to the increase in the number of signal lines can be minimized.

(4). By providing the means for designating the single address transfer or the dual address transfer, the data transfer can be performed even for the input / output circuit having no acknowledge signal.

(5). In addition to RAMP, RAMI is provided so that the CPU can operate independently of the data transfer of the input / output circuit and RAMP.
By making it possible to read / write AMI,
The frequency with which the CPU and DTC operate simultaneously can be increased. Even when the CPU saves / restores the stack in response to an interrupt or the like, parallel operation becomes possible.

(6). Particularly in this embodiment, the CPU and D
Since the TCs are connected to different buses, the frequency of stalling the CPU due to data transfer can be reduced.
The processing speed can be further increased.

By the single address mode, the bus cycle required for the DTC register read / write and data transfer can be reduced, the frequency of stall of the CPU can be further reduced, and the processing speed can be further increased.

(Embodiment 2) FIG. 15 is a block diagram showing the main part of a microcomputer which is another embodiment of the present invention, and FIG. 16 is a diagram showing the configuration of the address bus / data bus of the microcomputer of this embodiment. 17 and 18 are timing charts showing an example of single address data transfer.

The microcomputer of this embodiment is different from the microcomputer of FIG. 1 of Embodiment 1 in that the DTC is a direct memory access controller DMAC (data transfer control device) as shown in FIG.
The address output from the MAC is IAB, and the input / output data is IDB. The CPU and the DMAC operate exclusively based on the bus right arbitration of the bus controller BSC.

The dedicated register of the DMAC is the same as in the first embodiment.
Similar to DTMR, BTCR, TCR, SAR, DAR
, The number of supporting channels (for example, 4 channels) is held in the DMAC.

Since the DMAC holds the register information in a dedicated register which has a built-in register, it is not necessary to read the vector or the register information prior to the data transfer or to write the register information after the data transfer is completed. Therefore, D
By operating the MAC, the frequency of stalling the CPU can be reduced.

In order to read / write the dedicated register of the DMAC, the PAB and PDB are DMA
It is connected to C. The other functional blocks are the same as those in the first embodiment, so the description thereof will be omitted.

Next, the connection state of the address bus / data bus of the microcomputer will be described with reference to FIG.

Similar to FIG. 2, the timer shown in FIG.
Includes pulse output circuit, SCI, A / D converter, input / output port, and register of interrupt controller. Functional blocks (or modules) not connected to a bus such as CPG are omitted.

As an address bus, CPU, DMAC,
ROM, RAMI, IAB, RAMP connecting externally,
There is a PAB that connects the I / O. The address bus is interfaced with the bus controller BSC.

As a data bus, CPU, DTC, RO
M, RAMI, IDB for external connection, and RAM
There is a PDB that connects P and I / O. The data buses IDB and PDB are interfaced with the bus controller BSC. If necessary, the IDB and PDB are connected to input / output data.

An independent acknowledge signal is applied from the DMAC to the I / O. Since the acknowledge signal corresponds to the register included in the I / O, there are cases where a plurality of acknowledge signals are given to one functional block (module).

The IAB and IDB are buffer circuits BU.
It is connected to an external bus via F. The buffer circuit BUF is included in IOPs 1 to 5.

Next, an example of the operation timing of the internal bus in the single address mode will be described with reference to FIG.

The interrupt controller activates the DMAC activation request signal to activate the DMAC.

The DMAC activates the DMAC bus right request signal, and when the DTC bus right acknowledge signal becomes active, outputs the contents of the address register SAR (or DAR) to the IAB in synchronization with φ # of T2, and the IAB The contents are output to PAB in synchronization with φ and R by DMAC
Read of AMP is started. That is, the single address transfer from the RAM to the I / O is performed in the 2-state period from T3.

The bus right request signal is deactivated, and T3
The bus right is given to the CPU in synchronization with φ # of
Read / write the ROM and RAM using the IDB. The CPU is stalled in only one state.

As described above, the IAB output in synchronization with φ # of T2 is output to the PAB in synchronization with φ of T3.
The read signal IORDN for RAMP and I / O is activated in synchronization with φ # of T3, and the data of RAMP indicated by PAB is output to PDB. At the same time, D
Of the MAC acknowledge signals, the specified signal becomes active and the internal register of the I / O is selected.
The content of PDB is written to the internal register corresponding to N. In parallel with the single address transfer of the PDB, the CPU can use the IDB to perform ROM / RAMI or external read / write.

Therefore, according to the microcomputer of this embodiment, by incorporating the DMAC in place of the DTC, the following operational effects can be obtained.

(1). Since the DMAC reads / writes the input / output circuit by giving an independent acknowledge signal to the input / output circuit without designating an address, the address signal and the write signal / read signal are simultaneously sent to the RAM. (RAM
P) to write / read the RAM, the RAM and the input / output circuit are connected to each other, and RA is performed by one bus cycle.
Data can be transferred between M and the input / output circuit, and the speed can be increased. The time from the occurrence of a DMAC activation factor such as an interrupt to the actual end of data transfer can be shortened, and the control accuracy of the device controlled by the microcomputer can be improved.

(2). Even during the single address transfer using the PDB, the CPU can read / write the IDB so that only the first one state of the data transfer is stalled, and the other period is the ROM. Since the program can be read from
The frequency of PU stalls can be reduced.
The simultaneous operation of the CPU and the DMAC can improve the processing speed of the microcomputer or the semiconductor integrated circuit.

(3) By reducing the number of registers of the input / output circuit which is the object of data transfer, it is not necessary to increase the acknowledge signal or the bit of the register for designating the acknowledge signal. The increase in the physical size of the microcomputer due to the increase in the number of signal lines can be minimized.

(4). By providing the means for designating the single address transfer or the dual address transfer, the data transfer can be performed even for the input / output circuit having no acknowledge signal.

(5). In addition to RAMP, RAMI is provided so that the CPU can operate independently of the data transfer of the input / output circuit and RAMP.
By making it possible to read / write AMI,
The frequency with which the CPU and the DMAC operate simultaneously can be increased. Even when the CPU saves / restores the stack in response to an interrupt or the like, parallel operation becomes possible.

(6) Especially in this embodiment, since the DMAC has a register, the stall frequency for the CPU can be reduced by the operation of the DMAC.

Although the invention made by the present inventor has been specifically described based on the first and second embodiments, the present invention is not limited to the above-mentioned embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, the program of the CPU may be arranged in the ROM or used as an external memory. The input / output timing of the external address / external data bus can be the same as for PAB and PDB, for example. Similarly,
The memory that is the work area of the CPU is not limited to RAMI and can be an external memory. ROM or RAMI may not be built in. It suffices if the CPU can read the program via a bus that can be separated from the DTC or the DMAC.

Further, the RAMI and RAMP are constituted by one memory module, and a so-called dual port RAM is provided.
It may be. When the CPU and DTC simultaneously read / write the RAM, one of them is waited, but in the other cases, the operation can be performed as in the above embodiment.

Needless to say, the specific circuit configurations of the DTC or DMAC, interrupt controller, bus controller, and input / output circuit can be changed in various ways.

In the above description, the case where the invention made by the present inventor is mainly applied to the microcomputer, which is the field of use thereof, has been described, but the present invention is not limited to this, and other semiconductor integrated circuit devices such as, for example, The present invention is also applicable to a semiconductor integrated circuit device centering on a digital signal processor (DSP) and a computer system centering on this semiconductor integrated circuit device, and the present invention is at least a data processing device and a data transfer device or data transfer. The present invention can be widely applied to semiconductor integrated circuit devices including a control device.

For example, in a printer control system which is an example of a computer system centered on a microcomputer, as shown in FIG. 18, a microcomputer such as a buffer RAM, a character generate ROM (CGROM), and an output buffer are externally provided. A memory, a Centronics interface circuit, an external input / output circuit such as a print head, etc. are connected, and the output of the pulse output circuit drives a line feed motor and a carriage return motor via a buffer circuit. The data transfer by the DTC or DMAC can be used for setting pulse output data (next data register of pulse output circuit), setting pulse output interval (output compare register of timer), and the like.

[0173]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). A first bus in which a data processing device, a bus control means and a first storage means are mutually connected, and a data transfer device, a bus control means, a second storage means and a data input / output means. The bus control means makes it possible to select whether or not the first bus and the second bus are connected to each other, so that the data processing device can be used when the first bus and the second bus are not connected by the bus control means. Since the read / write of the first storage means by the data transfer and the data transfer between the second storage means and the data input / output means by the data transfer device can be performed in parallel, the processing speed of the semiconductor integrated circuit device can be improved. It is possible to improve.

(2). The data transfer device supplies an acknowledge signal to the data input / output means, and the register means is specified by this unique acknowledge signal, so that the data transfer device does not specify the address, but the data input / output means. Since an acknowledge signal can be given to the means to read / write the data input / output means, at the same time, an address signal and a read / write signal are given to the second storage means to read / write the same. Since the second storage means and the data input / output means are connected to each other and data can be transferred between the second storage means and the data input / output means in one bus cycle, the processing speed can be increased.

(3). It has an interrupt control means for inputting an interrupt request signal output by the data input / output means, and the interrupt request signal output by the interrupt control means to the data processing device and the data transfer device. By selectively activating the activation request signal to be output, the data processing device can read the program from the first storage means, so that the frequency of stall of the data processing device due to this data transfer can be reduced. It will be possible.

(4) Limiting the register means of the data input / output means which is the object of data transfer to the output compare register of the timer, the input capture register, the SCI receive data register, the transmit data register, etc.
It is not necessary to increase the acknowledge signal or the bit of the register means for designating the acknowledge signal, and the number of register means can be reduced. In addition, it is possible to minimize the increase in the number of signal lines due to the increase in the acknowledge signal, and thus the increase in the physical scale of the microcomputer.

(5). Since it is possible to specify whether to perform single address transfer or dual address transfer, it is possible to perform data transfer even to data input / output means having no acknowledge signal. .

(6). When the first other storage means connected to the data processing device is provided, the data processing device operates independently of the data transfer of the data input / output means and the second storage means. Since the other storage means of No. 1 can be read / written, the frequency of simultaneous operation of the data processing device and the data transfer device can be increased, and the data processing device saves the stack in response to an interrupt or the like. / Parallel operation is possible even when performing restoration.

(7). A data transfer control device is provided in place of the data transfer device, and the data transfer control device, the data processing device, the bus control means, and the first storage means are mutually connected by the first bus. When the bus control means, the second storage means and the data input / output means are connected to each other by the second bus, the processing performance can be improved as in the case of the data transfer device. ) ~ It is possible to obtain the same effect as (6).

(8) By the above (1) to (7), the data transfer by the data transfer device or the data transfer control device is performed in parallel with the processing by the data processing device while minimizing the deterioration of the processing performance of the data processing device. It becomes possible to improve the execution efficiency, processing performance, etc. of the semiconductor integrated circuit device especially in a computer system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a microcomputer that is Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram showing a configuration of an address bus and a data bus in the microcomputer of the first embodiment.

FIG. 3 is an explanatory diagram showing an address map according to the first embodiment.

FIG. 4 is an explanatory diagram illustrating a register configuration of a data transfer device (DTC) according to the first exemplary embodiment.

FIG. 5 is a DTC mode register (DT according to the first embodiment.
It is explanatory drawing which shows the structure of (MR).

FIG. 6 is a DTC mode register (DT) according to the first embodiment.
It is explanatory drawing which shows the structure (following FIG. 5) of MR).

FIG. 7 is a block diagram showing a DTC according to the first embodiment.

FIG. 8 is an explanatory diagram showing a configuration of a DTC register on a memory in the first embodiment.

FIG. 9 is a block diagram showing an interrupt controller in the first embodiment.

FIG. 10 is a block diagram showing a bus controller according to the first embodiment.

FIG. 11 is an explanatory diagram showing an example of an operating state of a bus in the first embodiment.

FIG. 12 is a flowchart showing the operation of DTC in the first embodiment.

FIG. 13 is a timing diagram illustrating an example of single address data transfer according to the first exemplary embodiment.

FIG. 14 is a block diagram illustrating a specific configuration of a read / write control circuit of an input / output circuit (I / O) according to the first exemplary embodiment.

FIG. 15 is a block diagram showing a main part of a microcomputer that is Embodiment 2 of the present invention.

FIG. 16 is an explanatory diagram showing a configuration of an address bus / data bus of the microcomputer of the second embodiment.

FIG. 17 is a timing diagram illustrating an example of single address data transfer according to the second embodiment.

FIG. 18 is a block diagram showing an example of a computer system using the semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

CPU central processing unit (data processing device) DTC data transfer controller (data transfer device) ROM read only memory (first storage means) RAMI random access memory (first other storage means) RAMP random access memory (second storage device) Storage means) SCI serial communication interface A / D A / D converter IOP1 to IOP11 I / O port BSC bus controller (bus control means) CPG clock oscillator IAB internal address bus (first bus) DTAB internal address bus PAB internal address bus (Second bus) IDB internal data bus (first bus) PDB internal data bus (second bus) I / O input / output circuit (data input / output means) BUF buffer circuit VAR vector address register DTMR model Mode register BTCR block transfer count register TCR transfer count register SAR source address register DAR destination register DB data buffer AB address buffer DEC decoder MIF bus interface AU arithmetic operation circuit VAG vector address generation circuit DMAC direct memory access controller (data transfer control device)

Claims (13)

[Claims] 1. A semiconductor integrated circuit device having a data processing device, a data transfer device, a bus control means, and a data input / output means, wherein the first and second storage means are connectable to the data processing device. The bus control means and the first storage means are mutually connected by a first bus,
And the data transfer device, the bus control means, and the second
Storage means and the data input / output means are mutually connected by a second bus, and the bus control means makes a connection by selecting whether or not to connect the first bus and the second bus. If not, the first of the data processing devices
Read or write using the above bus and data transfer between the second storage means and the data input / output means using the second bus of the data transfer device are performed in parallel. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the data transfer device supplies an acknowledge signal to the data input / output means, register means designated by the acknowledge signal, and the second means. A semiconductor integrated circuit device, wherein data is transferred as one bus cycle to and from the second storage means specified by address information of a bus. 3. The semiconductor integrated circuit device according to claim 1, wherein the data input / output unit can request an interrupt, and has an interrupt control unit for the interrupt request. The control means inputs the interrupt request signal output from the data input / output means, outputs an interrupt request signal to the data processing device, and outputs a start request signal to the data transfer device, and the interrupt request signal. A semiconductor integrated circuit device characterized by selectively activating a signal and a start request signal. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the second storage means is writable and readable. 5. The semiconductor integrated circuit device according to claim 1, 2, 3 or 4, wherein the second storage means is built in. 6. The semiconductor integrated circuit device according to claim 1, 2, 3, 4, or 5, wherein said first memory means is incorporated. 7. A data processing device, a data transfer control device,
A semiconductor integrated circuit device having a bus control means and a data input / output means, wherein the first and second storage means are connectable to each other, and the data processing device, the data transfer control device, the bus control means, and the The first storage means is mutually connected by a first bus, and the bus control means, the second storage means and the data input / output means are mutually connected by a second bus, and the bus control is performed. The means selects whether the first bus and the second bus are connected or not, and when the connection is not made, read or write using the first bus and the data transfer control device A semiconductor integrated circuit device, wherein part or all of the data transfer between the second storage means and the data input / output means using the second bus is performed in parallel. 8. The semiconductor integrated circuit device according to claim 7, wherein the data transfer control device supplies an acknowledge signal to the data input / output means, register means designated by the acknowledge signal, and the second means. Data transfer is performed as one bus cycle with the second storage means specified by the address information of the first bus.
The semiconductor integrated circuit device characterized in that the reading or writing using the bus is performed in parallel with some or all of the periods. 9. The semiconductor integrated circuit device according to claim 7, wherein the data input / output unit can request an interrupt, and has an interrupt control unit for the interrupt request. The control means inputs the interrupt request signal output from the data input / output means, outputs an interrupt request signal to the data processing device, and outputs a start request signal to the data transfer control device, A semiconductor integrated circuit device characterized by selectively activating a request signal and a start request signal. 10. The semiconductor integrated circuit device according to claim 7, 8 or 9, wherein the second storage means is writable and readable. 11. The semiconductor integrated circuit device according to claim 7, 8, 9 or 10, wherein said second storage means is incorporated. 12. The semiconductor integrated circuit device according to claim 7, 8, 9, 10 or 11, wherein said first storage means is incorporated. 13. The method according to claim 1, 2, 3, 4, 5, 6, 7,
A computer system using the semiconductor integrated circuit device according to 8, 9, 10, 11 or 12, wherein at least an auxiliary storage device centering on the semiconductor integrated circuit device,
A computer system in which a display device and an input / output device are connected.