JPH08286886A - Graphics circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable relatively high-speed drawing in a graphics circuit while using an inexpensive circuit configuration. A relatively inexpensive synchronous DRAM 12 similar to a DRAM is used without using an expensive dual port memory as an image memory, and a first control means 11 having the same function as a conventional CRT controller using DRAM is used. , Their peripheral circuits (second control means 15,
The configuration is such that the latch means 13 and the data holding means 16) are added, and the reading from the synchronous DRAM 12 in the display period is made several times faster than that in the case of using a general DRAM, and the continuous reading is drawn. I am trying to extend the period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a CRT or LCD, for example.
The present invention relates to a graphics circuit that displays characters and figures on a display such as.

[0002]

2. Description of the Related Art Generally, in a personal computer or the like, an interface through which a user obtains most information is a display, and a graphics circuit for displaying characters and graphics on this display is always high-definition and high-speed display. Is required.

FIG. 5 is a block diagram of a conventional graphics circuit. In the figure, 50 is a graphics circuit, 60
Is a CPU that controls the graphics circuit 50.

The graphics circuit 50 includes a DRAM 51 for storing image data, a drawing controller circuit 52 for writing drawing data in the DRAM 51, a display controller circuit 53 for reading out the image data of the DRAM 51 and displaying it on a display, and a display controller circuit. The image data read by 53 is provided with a shift register 54 that performs parallel / serial conversion according to a reference clock of display timing and sequentially outputs. A combination of the drawing controller circuit 52 and the display controller circuit 53 described above is called a CRT controller 55.

The operation of the graphics circuit 50 is shown in FIG.
It becomes as shown in the timing chart of. This behavior is
Since it is well known, the description will be simplified. In FIG. 6, (a) is a reference clock CLK for display timing output from the CRT controller 55, (b) is a display / drawing timing signal DISP / DRAW output from the CRT controller 55, and (c) is a CRT controller. 5
5, the display / drawing address ADDRESS output from
(D) to (g) are read / write control signals RAS, CAS, OE, WE output from the CRT controller 55,
(H) is display data and drawing data from the DRAM 51, and (i) is display data output from the shift register 54.

[0006] For example, when a drawing command is received from the CPU 60, the drawing controller circuit 52 generates a write address and drawing data for the DRAM 51 and writes the write address. When the display command is received from the CPU 60, the display controller circuit 53 generates a display address and a horizontal / vertical synchronization signal (not shown), outputs the display data read from the DRAM 51 to the shift register 54, and the shift register 54. Output to the display side according to the reference clock of display timing. In this example, the drawing process is performed during the interval of the display process, but the drawing process from the CPU 60 may be performed during the blanking period during which no display is performed.

The ratio of the display period to the drawing period is D
It is determined by the speed of the RAM 51, the data bus width, the speed of the reference clock CLK for display timing, and the number of data bits per pixel. DRAM
51 speed = reference clock = 4, data bus width = 8
If 1 bit = 1 pixel = 1 bit, the data bus width = 8 bits is read in one display period, and 8-bit data is read. Since 1 pixel = 1, 8 pixels can be displayed. However, since the speed of the DRAM 51 = reference clock = 4, 8 pixels-4 pixels = 4 pixels can be allocated to the drawing period. Therefore, in this example, the ratio of the display period and the drawing period is 1: 1,
With this, the display output from the CRT controller 55
The drawing timing signal DISP / DRAW is set.

[0008]

By the way, in the above conventional example, since the ratio of the display period to the drawing period must be set to 1: 1 due to the use of the DRAM 51, the drawing period is short. However, it takes time to rewrite the display screen. This problem becomes more remarkable because the rewrite data increases as the display becomes finer.

On the other hand, the graphics circuit 5
If the portion of the DRAM 51 of 0 is replaced with a dual port memory and the drawing process and the display process are performed by different data ports, the drawing process time can be increased. However, in this case, the DRAM 51
Due to using a dual port memory that is considerably more expensive than
The circuit configuration will be expensive.

As described above, in the structure using the DRAM,
Although the circuit configuration can be made inexpensive, it takes a long time to rewrite the display screen, and in the configuration using the dual port memory, although the display screen rewriting time is short, the circuit configuration becomes expensive. There is room.

Therefore, an object of the present invention is to make it possible to perform relatively high-speed drawing in a graphics circuit while having an inexpensive circuit configuration.

[0012]

DISCLOSURE OF THE INVENTION According to the present invention, drawing is performed to store drawing data in an image memory in response to a drawing command, and image data stored in the image memory is read in response to a display command. In the graphics circuit for controlling the display output by the display unit and the display displayed on the display unit, it is configured as follows.

The graphics circuit of the present invention includes a synchronous DRAM as an image memory and a display / display unit in which the ratio of the display period and the drawing period is set to 1: n (n is 2 or more).
First control means for outputting a drawing timing signal, a display / drawing address, drawing data, a read / write control signal for DRAM, and a reference clock for display timing;
Based on the read / write control signal for DRAM output from the control means, high-speed continuous read from the synchronous DRAM is performed m times (m is 2 or more) in one display period of the display / drawing timing signal. While generating and outputting a read control signal for performing the writing, a writing control signal for causing the writing of the display / drawing timing signal n = m + (m-1) times is generated and output. Second control means, latch means for latching the display / drawing address output from the first control means in response to a read / write control signal output from the second control means, and the synchronous DRAM
Data holding means for holding the display data for m times continuously read from and sequentially outputting to the display side.

[0014]

In summary, the present invention uses a relatively inexpensive synchronous DRAM similar to the DRAM without using an expensive dual port memory as the image memory, and
The first control means having the same function as that of the conventional CRT controller using the RAM is used, and their peripheral circuits (second
(Control means, latch means, data holding means) is added, and reading from the synchronous DRAM in the display period is performed at a speed several times faster than in the case of using DRAM, and the drawing period is set for the continuous reading. I am trying to expand.

From the above, it is possible to set the ratio of the display period, which is the display / drawing timing, to the drawing period from 1: 1 in the conventional example using DRAM to 1: 2 or more, and as a result. Even if the dual port memory is not used, the drawing processing time can be made longer than in the conventional example using the DRAM.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the embodiments shown in FIGS. 1 to 4 relate to an embodiment of the present invention. FIG. 1 is a block diagram showing a graphics circuit, FIG. 2 is an internal block diagram of the read / write control circuit of FIG. 1, and FIG. Display of example and conventional example
FIG. 4 is a timing chart for comparing drawing timing signals, and FIG. 4 is a timing chart for explaining the operation.

In the figure, 10 is a graphics circuit, and 20 is a CPU for controlling the graphics circuit 10.

The graphics circuit 10 includes a CRT controller 11 as a first control means, a synchronous DRAM 12 as an image memory, and a CRT controller 1.
An address latch circuit 13 as a latch means for latching the drawing / display address from 1, a data buffer circuit 14 for controlling the data input / output direction between the CRT controller 11 and the synchronous DRAM 12, and a second control means. Read / write control circuit 15 and a shift register 16 as a data holding means for parallel / serial converting the image data read from the synchronous DRAM 12 and sequentially outputting it as display data.

As the CRT controller 11, the same one as the conventional CRT controller 55 using a DRAM is used, and the display / drawing timing signal DISP / DR is used.
AW, display / drawing address, drawing data, general DRAM read / write control signals RAS, CAS, W
It outputs E and OE and a reference clock CLK for display timing. Display / draw timing signal DISP here
In / DRAW, the ratio of the display period and the drawing period is 1: n.
(N is 2 or more) is set. Note that n is determined in accordance with the number m (m is 2 or more) of continuous reading in one display period as described below, and n = m +
(M-1). Further, the value of m cannot be increased without limit, and the value of m is determined by determining the display active time t of the display / drawing timing signal DISP / DRAW.
d, the minimum clock cycle time ts of the synchronous DRAM 12 is related, and there is a limit of m <td / ts.
That is, data cannot be read at a speed faster than the minimum clock cycle time ts of the synchronous DRAM 12. For example, when n = 7, the result is as shown in FIG. In FIG. 3, (a) is the display / drawing timing signal DISP / DRAW in the conventional example, (b) is the display / drawing timing signal DISP / DRAW in this embodiment,
The one display / drawing cycle of this embodiment corresponds to the conventional four display / drawing cycles.

The synchronous DRAM 12 is a so-called high-speed DRAM, which is well known, and has two banks of memory cells so that they can be accessed independently of each other. The same row in the same bank can be continuously accessed, and the column address input to data output is further divided into a three-stage pipeline from column address fetching, fetching the corresponding data, and outputting to the output terminal. C of the reference timing for displaying each pipeline
The LK signal can be processed independently.

The read / write control circuit 15 receives the display / drawing timing signal once based on the general DRAM read / write control signals RAS, CAS, WE and OE output from the CRT controller 11. Read control signals CS, SRAS, SCA for performing high-speed continuous read from the synchronous DRAM 12 m times during the display period of
Write control signals CS, SRAS, SCAS, SWE for generating and outputting S, SWE, and a clock SCLK, and writing n times in one drawing period with the display / drawing timing signal DISP / DRAW and The clock SCLK is generated and output. The read / write control signals CS, SRAS, SCAS and SWE output from the read / write control circuit 15 are combined into a row designation command or a column designation command. Clock S
As shown in FIG. 4, six CLKs are output in one display period. The first two of them are for the output timing of the read row designation command and the read column designation command, and the following four are output. It is for data read timing. Further, two clocks SCLK are output in one drawing period, but they are respectively used for the output timing of the write row designation command and the write column designation command.

Here, the read / write control signals RAS, CA for the DRAM output from the CRT controller 11
The truth table in Table 1 below shows the correspondence relationship between S, WE, and OE and the read / write control signals CS, SRAS, SCAS, SWE, and SCLK for the synchronous DRAM output from the read / write control circuit 15. Shown in.

[0023]

[Table 1]

Specifically, the read / write control circuit 15
2, generates an SRAS signal corresponding to CS and RAS for active / inactive selection of the synchronous DRAM 12 and an address latch signal to the address latch circuit 13 based on RAS from the CRT controller 11. Then, the reference clock CLK from the CRT controller 11
The SRT corresponding to the CAS signal is generated based on RAS and CAS from the CRT controller 11 and the first conversion unit 151 that outputs the CRT controller 11
The second conversion unit 152 which outputs in synchronization with the reference clock CLK from the CRT controller 11 and the SWE corresponding to the second conversion unit 152 which generates based on the WE from the CRT controller 11 and outputs the SWE in synchronization with the reference clock CLK from the CRT controller 11. 3 conversion unit 153 and OE from the CRT controller 11
And a reference clock CL from the CRT controller 11 by generating a direction control signal to the data buffer circuit 14 based on the display / drawing timing signal DISP / DRAW.
The fourth conversion unit 154 that outputs in synchronization with K, the fifth conversion unit 155 that generates and outputs the required clock SCLK for the synchronous DRAM 12 based on the reference clock CLK, and the output SCLK from the fifth conversion unit 155. And CR
Display / drawing timing signal D from the T controller 11
AND circuit 156 for generating and outputting an output timing signal of display data to shift register 16 based on ISP / DRAW.

Next, the graphics circuit 10 of the present embodiment.
The operation will be described with reference to FIG. In FIG. 4, (a)
Is a reference clock CLK for display timing output from the CRT controller 11, and (b) is a display / drawing timing signal DISP output from the CRT controller 11.
/ DRAW, (c) is the display / drawing address ADDRESS output from the CRT controller 11, (d)-
(G) is the reading output from the CRT controller 11.
The write control signals RAS, CAS, WE, OE, (h) are C
Drawing data output from the RT controller 11,
(I) is the clock SCLK output from the read / write control circuit 15, and (j) is the read / write control circuit 15.
Active / inactive selection signal CS output from (k)
Is a display / drawing address output from the address latch circuit 13, and (l) to (n) are read / write control circuits 15.
Read / write control signals SRAS, SCA output from
S, SWE, (o) are read data and drawing data from the synchronous DRAM 12, and (p) are display data from the shift register 16.

First, upon receiving a display command from the CPU 20, the CRT controller 11 causes the synchronous DRAM to operate.
The display data read operation is started from 12. That is, the CRT controller 11 displays the display address to be read and the DR required to read in the display period.
Read control signals RAS, CAS, WE, and OE for AM are output, respectively. Of these, the display address is held by the address latch circuit 13, and the synchronous DRAM 12
Is output according to the required timing. Further, the read control signals RAS, CAS, WE, and OE are transferred to the C for the synchronous DRAM 12 by the read / write control circuit 15.
Create S, SRAS, SCAS, SWE, SCLK,
It is output to the synchronous DRAM 12. At this time, in the display period of one time from the synchronous DRAM 12, m times of data reading from the conventional DRAM are continuously read at high speed, and the shift register 16
Output to. The shift register 16 holds the read data for m times and uses the reference clock CLK of the display timing.
The display data is sequentially output according to For example,
When m = 4, the display data for four times, that is, four times as large as the read data for the conventional DRAM is read from the synchronous DRAM 12 in one display period. For example, assuming that one read data in the conventional DRAM is 8 bits, one read data in this embodiment is 8 × 4 =
It will be 32 bits.

On the other hand, when receiving a drawing command from the CPU 20, the CRT controller 11 causes the synchronous DRAM to operate.
The writing operation of the drawing data for 12 is started. That is, the CRT controller 11 sequentially outputs the drawing address for writing n times, the drawing data, and the write control signals RAS, CAS, WE, and OE for DRAM necessary for writing in one drawing period.
Of these, the drawing address is held by the address latch circuit 13, and the drawing data is output to the synchronous DRAM 12 through the data buffer circuit 14 at a required timing. In addition, write control signals RAS, CAS,
WE and OE are controlled by the read / write control circuit 15.
Write control signals CS and SR for the synchronous DRAM 12
AS, SCAS, SWE, and SCLK are generated and output to the synchronous DRAM 12. As a result, the drawing data is written in the synchronous DRAM 12.
For example, if n = 7, as shown in FIG. 3, the write operation in the case of using the conventional DRAM is performed seven times in one drawing period, so that the time for writing to the synchronous DRAM 12 for drawing is increased. Will be expanded, and the speed of the screen rewriting process will be improved.

As described above, the synchronous DRA
By using M12, it is possible to perform continuous reading at a speed several times faster than the case of using the conventional DRAM in the display period per time, and to extend the drawing period per time according to the degree of this reading. Therefore, the ratio of the display period as the display / drawing timing and the drawing period is changed from 1: 1 in the conventional example using the DRAM to
It becomes possible to change to 1: n (n is 2 or more).

[0029]

According to the present invention, continuous read is performed at a speed several times higher than that in the case of using the conventional DRAM in one display period, and according to the degree of this read, 1
Since the drawing period per time is expanded, the speed of the screen rewriting process can be improved.

A synchronous DRAM which is considerably cheaper than a dual port memory is used as the image memory, and the first control means having the same function as that of the conventional CRT controller using the DRAM is used.
Since these peripheral circuits (second control means, latch means, data holding means) are used, an inexpensive circuit configuration can be achieved. If the conventional CRT controller (first control means) is used, the software required for controlling the graphics circuit can be used without changing the conventional software, which also contributes to the price reduction. To do.

As described above, according to the present invention, it is possible to provide an excellent graphics circuit capable of drawing at a relatively high speed while having an inexpensive circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a graphics circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a read / write control circuit of FIG.

FIG. 3 is a timing chart for comparing display / drawing timing signals of the example and the conventional example.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional graphics circuit.

FIG. 6 is a timing chart for explaining the operation in the conventional example.

[Explanation of symbols]

 10 Graphics Circuit 11 CRT Controller 12 Synchronous DRAM 13 Address Latch Circuit 14 Data Buffer Circuit 15 Read / Write Control Circuit 16 Shift Register

Claims (1)

[Claims] 1. Drawing in which image data is stored in an image memory in response to a drawing command, and image data stored in the image memory is read out and output in response to a display command and displayed on a display unit. A graphics circuit for controlling the display, a synchronous DRAM as an image memory, and a display / drawing timing signal in which the ratio of the display period and the drawing period is set to 1: n (n is 2 or more), A first control means for outputting a display / drawing address, drawing data, a read / write control signal for DRAM and a reference clock for display timing, and a read / write control signal for DRAM output from the first control means. On the basis of the display / drawing timing signal, m times (m is 2
In order to generate and output the read control signal for performing the high-speed continuous reading described above), the display / drawing timing signal is written n = m + (m-1) times in one drawing period. The second control means for generating and outputting the write control signal and the second display / drawing address outputted from the first control means
Latch means for latching in response to a read / write control signal output from the control means, and m continuously read from the synchronous DRAM.
A graphics circuit, comprising: a data holding unit that holds display data for a batch and sequentially outputs it to the display side.