JPH08286201A - Flip chip type liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

(57) [Abstract] [Purpose] In a flip-chip liquid crystal display device,
In the steps from the formation of the wiring on the substrate on which the switching elements are formed to the mounting of the driving IC, countermeasures against static electricity are taken to improve productivity and reduce manufacturing cost. [Structure] Transparent insulating substrate SU where drive IC is mounted
A short circuit wiring SHc made of a transparent conductive film is provided on the B1 surface, the drain terminal DTM and a plurality of input wirings Td to the driving IC are connected to the short circuit wiring SHc, and then,
Before mounting the driving IC on the surface of the substrate SUB1, the short-circuit wiring SHc is cut by a laser or the like at the cutting lines C1, C2, C3, C4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type liquid crystal display device in which a driving IC is directly mounted on one of two transparent insulating substrates which are stacked together, and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, in order to mount a driving IC on one transparent insulating substrate which constitutes a liquid crystal display element (that is, a liquid crystal display panel), outer leads of a tape carrier package (TCP) mounted with the driving IC. And the wiring pattern formed on the transparent insulating substrate are electrically connected using an anisotropic conductive film. This anisotropic conductive film is a film-shaped thermosetting adhesive in which fine conductive particles are uniformly dispersed, and connects the outer lead and the wiring pattern which face each other by being heated and pressed, and TCP
The component can be fixed to the transparent insulating substrate.

However, in recent years, due to the demand for higher density of the liquid crystal display element and the demand for reducing the outer shape of the liquid crystal display module as much as possible, TCP parts are not used, and bumps (protruding electrodes) of the driving IC and liquid crystal are used. A method of directly connecting a wiring pattern on one transparent insulating substrate of the display element has been considered. Such a mounting method is called a flip-chip method or a chip-on-glass (COG) mounting method because the driving IC is directly mounted on the transparent insulating substrate.

This flip-chip connection method is shown in FIG.
This will be described with reference to FIG. As shown in FIG. 14A, bumps (projection electrodes) BUMP are formed on the lower surface of the driving IC. First, the driving IC is bonded to the bonding head H.
It is held on the pressure surface of the EAD by vacuum suction or the like. on the other hand,
A wiring pattern DTM (in the case of a video signal line, GTM in the case of a scanning signal line) that is joined to the bump BUMP is formed on the transparent insulating substrate SUB1 made of glass, for example. Further, an anisotropic conductive film ACF is attached in advance on the wiring pattern DTM.

Next, an image pickup camera CAM in which an image pickup surface FACE is arranged below the transparent insulating substrate SUB1.
The transparent insulating substrate SUB1 is driven in the XY directions based on the signal from the ERA, and the bump BUMP and the wiring pattern DT are driven.
Align M with.

Next, as shown in FIG. 14 (b), the bonding head HEAD is driven downward, the bump BUMP of the driving IC is brought into contact with the upper surface of the anisotropic conductive film ACF to be temporarily attached, and again. It is confirmed by the imaging camera CAMERA whether or not it is surely positioned, and if the alignment is good, the bonding head HEAD is used to perform thermocompression bonding.

In this way, the conductive particles in the anisotropic conductive film ACF are crushed between the bump BUMP and the wiring pattern DTM, and electrical connection is possible.

Although not shown in FIG. 14, a flexible substrate (FPC) that is electrically connected to the input wiring pattern to the driving IC and sends a signal from the outside is also subjected to the same bonding method as the FPC. The upper wiring pattern (usually a copper pattern is plated with gold) and the wiring pattern on the transparent insulating substrate SUB1 (input wiring T
It is possible to electrically connect d) to the anisotropic conductive film ACF.

[0009]

By the way, the conventional method has been insufficient as a countermeasure against static electricity (electrostatic breakdown) generated during the manufacturing process of the liquid crystal display element. That is, in the rubbing treatment step after applying the alignment film, the rubbing cloth comes into contact with the surface of the substrate, so that static electricity is generated, resulting in defective characteristics of a thin film transistor (TFT), which is a switching element extremely weak against static electricity. This will cause uneven display on the display. Further, if a method involving mechanical contact such as a diamond cutter is used in the substrate cutting step, static electricity is generated by the cutting operation itself, which causes similar defects. Furthermore, static electricity is generated in the sealing material application step, the bonding step of two opposite substrates, the liquid crystal encapsulation step, and the sealing step, and static electricity enters the substrate on the side where the thin film transistor is provided, and similar defects are generated. Cause.

The object of the present invention is to improve the productivity and reduce the manufacturing cost by taking measures against static electricity in the steps from the wiring formation of the substrate on which the switching elements are formed to the mounting of the driving IC. A flip-chip liquid crystal display device and a method of manufacturing the same are provided.

[0011]

In order to solve the above-mentioned problems, the flip-chip type liquid crystal display device of the present invention has the first of the two transparent insulating substrates superposed with a liquid crystal layer interposed therebetween. On the surface of the transparent insulating substrate on the liquid crystal layer side, a plurality of scanning signal lines and a plurality of video signal lines intersecting with the scanning signal lines via an insulating film are arranged in parallel, and the scanning signal lines and the video are provided. A flip-chip type liquid crystal display element in which a switching element is provided near each intersection with a signal line and the driving IC is mounted on the same substrate surface, wherein the driving IC
Has a short-circuit wiring on the surface of the substrate at a position where a substrate is mounted, the scanning signal line or the video signal line, and the driving IC.
Is connected to the short-circuited wiring.

Further, the short circuit wiring is formed of a transparent conductive film.

Further, a resistor element is connected between the scanning signal lines or the video signal lines, which is a wiring portion on the output side of the driving IC.

Further, the input wiring to the driving IC is connected to a common short-circuit line provided outside the cutting line of the first transparent insulating substrate.

Further, the resistor element is configured to include a semiconductor film having photoconductivity, and is formed below the mounted driving IC.

Further, in the method for manufacturing a flip-chip type liquid crystal display element of the present invention, a short circuit wiring is provided on the substrate surface where the driving IC is mounted, and the scanning signal line or the video signal line, It is prepared in advance so that a plurality of input wirings to the driving IC are connected to the short-circuit wiring, and thereafter, before the driving IC is mounted on the substrate surface, the short-circuit wiring is connected to a laser or It is characterized in that it is cut by photoetching or the like.

[0017]

According to the present invention, short-circuit wiring is provided on the substrate surface below the driving IC, and the scanning signal line (or video signal line) and the input wiring to the driving IC are connected to this short-circuit wiring. The scanning signal line (or video signal line) and the input wiring are short-circuited for each driving IC. In addition, the short-circuit wiring is a driving IC
Before being mounted on the substrate surface, it is cut by laser or photo etching. In addition, by connecting a resistor element between the scanning signal lines (or between the video signal lines), which is a wiring portion on the output side of the driving IC, the resistance of the scanning signal line (or the video signal line) is increased for each driving IC. Short circuit with your body. This quickly disperses the invading static electricity without affecting the normal operation of the driving IC, and suppresses the influence of static electricity in the steps from the formation of the wiring on the substrate surface to the mounting of the driving IC. it can. Note that the short-circuit wiring can be prevented from being contaminated by forming it with a transparent conductive film which is less contaminated even by laser cutting. In addition, the resistor element is configured to include a semiconductor film having photoconductivity, and light is irradiated during the manufacturing process to further reduce the resistance between the signal lines and disperse the invading static electricity more quickly. You can

[0018]

EXAMPLES The present invention will be specifically described below with reference to examples.

FIG. 6 is a plan view showing a state in which a driving IC is mounted on a transparent insulating substrate SUB1 made of glass, for example. Further, FIG. 7 shows a sectional view taken along the line AA. The one transparent insulating substrate SUB2 is located above the transparent insulating substrate SUB1 as shown by the chain line, and the liquid crystal LC is enclosed by the seal pattern SL (see FIG. 6) including the effective display portion (effective screen area) AR. are doing. The electrode COM on the transparent insulating substrate SUB1 is a wiring electrically connected to the common electrode pattern on the transparent insulating substrate SUB2 side via conductive beads, silver paste, or the like. The wiring DTM (or GTM) supplies the output signal from the driving IC to the wiring in the effective display area AR. Input wiring Td
Is for supplying an input signal to the driving IC. The anisotropic conductive film ACF has an elongated shape common to a plurality of driving IC portions arranged in a line ACF2 and an elongated shape common to the input wiring pattern portions to the plurality of driving ICs. ACF1 is attached separately.
As shown in FIG. 6, the passivation film (protective film) PSV1 covers the wiring part as much as possible to prevent electrolytic corrosion.
The exposed portion is covered with the anisotropic conductive film ACF1.

Further, the periphery of the side surface of the driving IC is filled with a silicone resin SIL (see FIG. 7), and protection is multiplexed.

FIG. 12 is a completed assembly view of the liquid crystal display module MDL, and is a perspective view of the liquid crystal display element as seen from the front side.

The liquid crystal display module MDL has two kinds of housing / holding members, a shield case SHD and a lower case.

The HLD is four mounting holes provided for mounting the module MDL as a display unit on an information processing device such as a personal computer or a word processor, and is fixed and mounted on the information processing device through screws or the like. The module MDL is provided with a brightness adjusting volume VR, a backlight inverter is arranged in the MI portion, and power is supplied to the backlight via the connector LCT and the lamp cable LPC. Signals and necessary power from the main computer (host) are supplied to the controller section and the power section of the liquid crystal display module MDL via the interface connector CT located on the back surface of the module.

FIG. 13 shows the embodiment T shown in FIG.
FIG. 3 is a block diagram showing a TFT liquid crystal display element of an FT liquid crystal display module (active matrix liquid crystal display module using thin film transistors TFT as switching elements) and circuits arranged on the outer periphery thereof. In this example, the drain drivers IC _{1 to} IC _M and the gate drivers IC _{1 to} IC _N are, as shown in FIG. 7, drain side lead lines DTM and gates formed on one transparent insulating substrate SUB1 of the liquid crystal display element. Chip-on with side lead wire GTM and anisotropic conductive film or UV curable resin
Glass mounted (COG mounted). In this example, XG
It is applied to a liquid crystal display element having effective dots of 1024 × 3 × 768, which is the A specification. Therefore, eight 192 output drain driver ICs are provided on each of the opposing long sides on the transparent insulating substrate of the liquid crystal display element (M = 16).
And 100 output gate driver ICs on the short side (N
= 8) and COG mounting. The drain driver section 103 is arranged on the upper and lower sides of the liquid crystal display element, the gate driver section 104 is arranged on the side surface section, and the controller section 101 and the power supply section 102 are arranged on the other side surface section. The controller unit 101, the power supply unit 102, the drain driver unit 103, and the gate driver unit 104 are connected to each other by electrical connecting means JN1 to JN4.

In this example, the XGA panel is 1024 ×
A TFT liquid crystal display module with a screen size of 3 × 768 dots and 10 inches was designed. Therefore, the size of each dot of red (R), green (G), and blue (B) is 207 μm.
(Gate line pitch) × 69 μm (drain line pitch), and one pixel is a combination of three dots of red (R), green (G), and blue (B), and is 207 μm square. For this reason, the drain line lead-out DTM is provided on one side by 10
If the number is 24 × 3, the lead line pitch will be 69 μm or less, which is less than the connection pitch limit of currently available tape carrier package (TCP) mounting. CO
In the G mounting, although it depends on the material such as the anisotropic conductive film used, the pitch of the bumps BUMP of the driving IC chip is about 70 μm and the crossing area with the underlying wiring is about 50 μm.
It can be said that the μm angle is the minimum value currently available. Therefore, in this example, the drain driver ICs are arranged in a line on the two long sides facing each other of the liquid crystal panel, the drain lines are alternately drawn out on the two long sides, and the pitch of the drain line lead-out DTM is set to 69. × 2 μm Therefore, the bump BUMP (see FIG. 7) of the driving IC chip has a pitch of about 100 μm.
Also, the crossover area with the underlying wiring can be designed to be about 70 μm square, and it has become possible to connect with the underlying wiring with higher reliability. Since the gate line pitch is 207 μm, which is sufficiently large,
Although the gate line lead-out line GTM is drawn out on the short side on one side, if the resolution becomes higher, it is also possible to draw out the gate line lead-out line GTM alternately on the two short side sides facing each other like the drain line. is there.

In the method of alternately drawing out the drain lines or the gate lines, as described above, the connection between the lead-out line DTM or GTM and the output side BUMP of the driving IC becomes easy, but the peripheral circuit board is opposed to the liquid crystal panel PNL. It is necessary to dispose them on the outer peripheral portion of the two long sides, which causes a problem that the outer dimension becomes larger than that in the case of one side drawing. In particular, as the number of display colors increases, the number of data lines of display data also increases, and the outermost shape of the information processing device becomes large.
Therefore, in this example, the conventional problem is solved by using the multilayer flexible substrate. Further, when the screen size of the XGA panel is 10 inches or more, the pitch of the drain line lead-out DTM is as large as about 100 μm or more, and the drain driver IC is COG on one long side.
Can be placed on one side by mounting.

The drive IC used in this example has a roughly external appearance as shown in FIG. 6, but has a very long and narrow shape in order to make the external shape of the module as small as possible. For example, in the drive IC on the gate side, the long side dimension is Is about 10 to 11 mm, the short side dimension is about 1.5 to 2 mm, and in the drain side drive IC, the long side dimension is about 15 to 16 mm and the short side dimension is about 1.5 to 2 mm. Further, in this example, the effective display area A
The output wiring pattern between the R and the output side bump BUMP portion of the driving IC extends from three directions of the long side and the short side of the driving IC.

For example, in this example, in the gate side drive IC, 11 out of 100 outputs are output from the 2 short sides, and about 78 lines are output from the 1 long sides. In the drive IC on the drain side, about 16 of the 192 outputs are
The remaining 160 wires are output-wired from the one long side. The drive IC can be designed to be more elongated, and the output wiring can be provided only in the long side direction. In that case, the present invention can be applied.

<< Method of Manufacturing Transparent Insulating Substrate SUB1 >> Next, the first transparent insulating substrate SUB of the liquid crystal display device described above.
The manufacturing method on the first side will be described with reference to FIGS. 9 to 11. In the figure, the central character is an abbreviation for the process name, the left side shows the pixel portion, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal. Except for steps B and D,
The steps A to G are divided according to each photo (photo) process, and each cross-sectional view of each process shows the stage where the processing after the photo process is completed and the photoresist is removed. In the present description, the photographic (photo) processing means a series of operations from application of photoresist to selective exposure using a mask to development thereof, and repeated description will be omitted. Description will be given below according to the divided steps.

Step A, FIG. 9 After the silicon oxide films SIO are formed on both surfaces of the first transparent insulating substrate SUB1 made of 7059 glass (trade name) by dip processing, baking is performed at 500 ° C. for 60 minutes.
Although this SIO film is formed in order to reduce the surface irregularities of the transparent insulating substrate SUB1, this step can be omitted if the irregularities are small. Al-Ta, A with a film thickness of 2800Å
The first conductive film g1 made of l-Ti-Ta, Al-Pd, or the like.
Are provided by sputtering. After the photo-treatment, the first conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step B, FIG. 9 After directly drawing the resist (after forming the above-mentioned anodic oxidation pattern),
3% tartaric acid PH6.25 ± 0.05 by ammonia
The substrate SUB1 was dipped in an anodizing solution composed of a solution prepared by diluting the solution prepared in step 1 with ethylene glycol solution 1: 9,
The formation current density is adjusted to 0.5 mA / cm ² (constant current formation). Next, anodic oxidation (anodic formation) is performed until the formation voltage 125 V required to obtain a predetermined Al ₂ O ₃ film thickness is reached. After that, it is desirable to hold this state for several tens of minutes (constant voltage formation). This is uniform Al
_This is important in obtaining a ₂ O ₃ film. As a result, the conductive film g1 is anodized, and the scanning signal line (gate line) is formed.
An anodic oxide film AOF having a film thickness of 1800Å is formed on the GL and on the side surface in a self-aligning manner and becomes a part of the gate insulating film of the thin film transistor TFT.

Step C, FIG. 9 A conductive film d1 made of an ITO film having a film thickness of 1400Å is provided by sputtering. After the photo process, the conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution to form the uppermost layer of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.

Step D, FIG. 10 Ammonia gas, silane gas and nitrogen gas are introduced into the plasma CVD apparatus to form a 2000 Å-thickness Si nitride film, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to reduce the film thickness. After the 2000 Å i-type amorphous Si film is formed, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N ⁺ -type amorphous Si film having a film thickness of 300 Å. This film formation is continuously performed by changing the reaction chamber in the same CVD apparatus.

Step E, FIG. 10 After photo processing, SF ₆ and CC are used as dry etching gas.
Using N ₄ , the N ⁺ type amorphous Si film and the i type amorphous Si film are etched. Subsequently, etching the nitride Si film using SF _6. Of course, the N ⁺ -type amorphous Si film, the i-type amorphous Si film and the Si nitride film may be continuously etched with SF ₆ gas.

The characteristic feature of the manufacturing process of this embodiment is that the three-layered CVD film is thus continuously etched with a gas containing SF ₆ as a main component. That is, the etching rate for SF ₆ gas is N ⁺ type amorphous Si film, i type amorphous S film.
The i film and the Si nitride film are larger in this order. Therefore, when the N ⁺ -type amorphous Si film is completely etched and the i-type amorphous Si film starts to be etched, the upper N ⁺ -type amorphous Si film is side-etched, resulting in the i-type amorphous Si film. The film is processed into a taper of about 70 degrees. Further, when the etching of the i-type amorphous Si film is completed and the etching of the Si nitride film is started, the upper side of the N ⁺ -type amorphous Si film and the i-type amorphous Si film are side-etched in this order. I-type amorphous Si film is about 50 degrees,
The silicon nitride film is tapered at 20 degrees. The above
Due to the pear shape, the probability of disconnection is significantly reduced even when the source electrode SD1 is formed on the source electrode SD1. The taper angle of the N ⁺ type amorphous Si film is close to 90 degrees, but the thickness is 300 Å
Since it is thin, the probability of disconnection at this step is very small. Therefore, N ⁺ type amorphous Si film, i type amorphous Si film
Strictly speaking, the plane patterns of the film and the Si nitride film are not the same pattern, and the cross section has a forward tapered shape. Therefore, the N ⁺ type amorphous Si film, the i type amorphous Si film, and the nitride film are nitrided. The pattern becomes larger in the order of the Si film.

Step F, FIG. 11: A second conductive film d2 made of Cr having a film thickness of 600 Å is provided by sputtering, and further, an Al- film having a film thickness of 4000 Å is formed.
A third conductive film d3 made of Pd, Al-Si, Al-Ta, Al-Ti-Ta or the like is provided by sputtering.
After the photo-treatment, the third conductive film d3 is etched with the same liquid as in step A, the second conductive film d2 is etched with a second cerium ammonium nitrate solution, and the video signal line DL, the source electrode SD1, and the drain electrode SD2 are etched. To form.

Here, in this embodiment, as shown in step E, an N ⁺ type amorphous Si film, an i type amorphous Si film, and a Si nitride film are formed.
Since the film is a normal taper, it is possible to form only the second conductive film d2 in a liquid crystal display device in which the tolerance of the resistance of the video signal line DL is large.

Next, SF ₆ and
By introducing CCl ₄ and etching the N ⁺ type amorphous Si film, the N ⁺ type semiconductor layer d between the source and the drain is formed.
0 is selectively removed.

Step G, FIG. 11 Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a Si nitride film having a thickness of 1 μm. After the photo-treatment, the protective film PSV1 is formed by etching using SF ₆ as a dry etching gas. As the protective film, not only an SiN film formed by CVD but also an organic material can be used.

<< Countermeasures against static electricity by short-circuit wiring SHc under the driving IC >> FIG. 1 is a plan view of the periphery of the mounting portion of the driving IC on the transparent insulating substrate SUB1 and a main part near the cutting line CT1 of the substrate. FIG. 9 is an overall plan view of the transparent insulating substrate SUB1 in the process of surface processing before cutting at the line CT1.

In FIG. 5, one lower transparent insulating substrate SUB1 constituting the liquid crystal display element has a larger area than the upper transparent insulating substrate SUB2 shown in FIG. 7, and is shown by a dotted line in the drawing by a later cutting process. It is cut at the cutting line CT1 and its outer portion is abandoned.

First, on the surface of the transparent insulating substrate SUB1,
A gate line group including gate lines (scanning signal lines) GL that extend in the x direction and are arranged in parallel in the y direction, and a gate line group that extends in the y direction and are arranged in parallel in the x direction in the central portion excluding its periphery. And a drain line group including the drain line (video signal line) DL. Each of the gate lines GL of the gate line group and each of the drain lines DL of the drain line group are formed to extend beyond a cutting line CT1 which is a cutting portion shown by a dotted line in the drawing. Although not shown, the gate line group and the drain line group are insulated from each other via an interlayer insulating film (GI) or the like.

Further, the display region is constituted by the region where the gate line group and the drain line group intersect, and the region surrounded by the two gate lines GL and the two drain lines DL which are adjacent to each other, A pixel area is formed. That is, a thin film transistor (TFT) as a switching element and a pixel electrode are formed in each pixel region, and a scanning signal is supplied to the gate line GL,
The thin film transistor is turned on, and the video signal from the drain line DL is supplied to the pixel electrode via the turned on thin film transistor.

Every other drain line DL extends in alternate directions beyond the cutting line CT1 and will be described in detail later on a drain short-circuit line (common drain line) SHd extending in the x direction in the drawing. Are connected via a short-circuit wiring SHc and an input wiring Td (to the drain line driving IC). After completion of the liquid crystal display element, the drain short-circuit wiring SH
d is formed on the surface of the transparent insulating substrate SUB1 outside the cutting line CT1 which is cut and discarded in each subsequent process. A drain line driving IC is mounted between the drain short-circuit wiring SHd connected to the drain line DL and the drain line DL (see FIGS. 1, 5, and 6), and this mounting region (indicated by IC in FIG. 1). (Indicated by an alternate long and short dash line) is shown in FIG.
As shown in FIG. 1, the short-circuit wiring SHc is provided in an island shape. Then, the drain line DL and the drain line driving I
A plurality of input wirings Td to C are connected to the short-circuit wiring SHc and short-circuited for each driving IC. In this way, the static electricity generated in each drain line DL and the input wiring Td is distributed through the short-circuit wiring SHc and the drain short-circuit wiring SHd.

On the other hand, in FIG. 5, of the formation region of each gate line GL, in the region inside the cutting line CT1 and in the vicinity of the cutting line CT1 on the upper side in the drawing, the mounting region of the gate line driving IC (FIG. In 5, the dotted line with the reference symbol IC
I will illustrate one. 1) is provided. Each of the gate lines GL is a gate short-circuit line (common line for anodization) AO whose extending portion beyond the cutting line CT1 extends in the y direction in the drawing on the side opposite to the mounting region in the extending direction. Connected through. After completion of the liquid crystal display element, the gate short-circuit wiring S
Hg and AO are formed on the surface of the transparent insulating substrate SUB1 outside the cutting line CT1 which is cut and discarded in the subsequent steps. In this example, unlike the drain line DL side, the island-shaped short-circuit wiring SHc is not provided on the gate line GL side. This is because the gate line driving ICs are arranged on only one side, and the gate lines GL can be short-circuited to each other by the anodizing common line AO on the opposite side (the side on which the gate line driving ICs are not arranged). Because you can. However, when the gate line driving ICs are arranged on both sides or when the gate short circuit wiring AO is not arranged, it is necessary to connect the gate line GL to the gate short circuit wiring SHg through the short circuit wiring SHc.

Further, the drain short-circuit wiring SHd and the gate short-circuit wiring SHg, AO are connected to each other via a capacitor ESD on the surface of the transparent insulating substrate SUB1 which is also cut and discarded later, via a capacitor ESD. It is joined. This capacitor ESD is intended to prevent the thin film transistor formed in each pixel region from being destroyed (a defect in which the characteristics change) due to static electricity, and therefore its capacitance value is formed smaller than that of the thin film transistor. .

Further, two anodic oxidation (anodic formation) pads PAD are formed adjacent to both ends of the gate short-circuit wiring SHg located on the upper side of FIG. This anodizing pad PAD is an insulating film (anodic oxide film AO) obtained by anodizing the surface of the gate line GL, as described in << Method of manufacturing transparent insulating substrate SUB1 >> above.
It is an electrode for supplying a current when forming F).

Further, although not shown, the transparent insulating substrate SUB1 has an inspection terminal so that it can be inspected whether or not the formed gate line GL (or drain line DL) is disconnected. It is formed at the end portion on the display area side in the vicinity of the mounting area of the driving IC. As a result, the gate short-circuit wiring AO (or the drain short-circuit wiring S
Hd) is brought into contact with one inspection probe (inspection needle), and the other probe is sequentially brought into contact with each inspection terminal of each gate line GL (or drain line DL), so that the presence or absence of disconnection can be inspected. it can.

As described above, as shown in FIGS. 1 and 5, the drain terminal DTM connected to the drain line DL.
And the input wiring Td to the driving IC are connected to the short-circuit wiring SHc provided on the surface of the transparent insulating substrate SUB1 below the driving IC and short-circuited for each driving IC. Furthermore, these are drain short-circuit wiring SHd. And all wiring is shorted. As a result, the load can be increased, the invading static electricity can be quickly dispersed, and the transparent insulating substrate SUB1
The influence of static electricity can be suppressed in the steps from the formation of the wiring on the surface to the mounting of the driving IC.

The short-circuit wiring SHc and the drain terminal DT
M and the input wiring Td to the driving IC are the driving IC
Of the cutting lines C1, C2, C shown in FIG. 1 (inside the bump connection portion BP of FIGS. 2 and 3) before mounting the substrate on the surface of the substrate SUB1.
It is cut by laser or photo-etching at points C3 and C4. Therefore, due to this cutting, as shown in FIG. 1, the passivation film PAS1 (that is, the protective film PSV1) is not formed in the region near the cutting lines C1 to C4.

Since the short-circuit wiring SHc is formed of the transparent conductive film ITO, which is less contaminated during laser cutting, contamination can be suppressed. The short circuit wiring SHc may be cut by photoetching.

When removing by photo etching or the like, the short circuit wiring SHc may be entirely removed. That is,
In FIG. 5, the short-circuit wiring (SH
c) shows the removed state.

<< Countermeasures against static electricity by the resistor element ED between the gate terminals GTM or between the drain terminals DTM >> FIG. 2 is an enlarged detailed view of the D portion of FIG. 1, FIG. 3 is an enlarged detailed view of the E portion of FIG. 1, and FIG. FIG. 3 is a sectional view taken along the line FF of FIG.

Between the gate terminals GTM (or the drain terminal DTM) which is a wiring portion on the output side of the driving IC shown in FIG.
2), 3), and 4), the insulating film G
I, amorphous semiconductor film AS, semiconductor film d0, conductive film d2,
The resistor element ED composed of d3 is connected. Also,
It is covered with a protective film PSV1. Note that the insulating film GI of the resistor element ED is simultaneously formed in the same layer as a part of the insulating film GI of the gate insulating film of the thin film transistor TFT (see the drawing on the left side of FIG. 11G). Similarly, the semiconductor film AS is the i-type amorphous Si film for forming the channel of the thin film transistor TFT, and the semiconductor film d0 is the N ⁺ -type amorphous Si film d0.
And the conductive films d2 and d3 are source and drain electrodes SD1,
The conductive films d2 and d3 for forming SD2 are formed simultaneously in the same layer. 2 and 3, reference numeral BP indicates the bump of the driving IC (reference numeral BUM in FIGS. 7 and 14) at the gate terminal GTM, the drain terminal DTM, and the input wiring Td.
P) is a bump connection portion to be bonded.

As a result, the gate terminal GTM connected to the gate line GL (or the drain line DL) is provided for each driving IC on the substrate SUB1, that is, when the resistor element ED is irradiated with light. (Or the drain terminal DTM) are connected by a resistor element ED. Therefore, the load of the resistor can be made smaller than the resistance between the gate and drain of the thin film transistor formed as a switching element, and the invading static electricity can be quickly dispersed without destroying the thin film transistor, and the static electricity on the surface of the substrate SUB1 can be reduced. The influence of static electricity can be suppressed in the steps from the formation of the wiring to the mounting of the driving IC. Further, when the resistor element ED is configured to include the semiconductor film AS having photoconductivity and is formed below the driving IC, when it is desired to short-circuit to prevent electrostatic breakdown, the resistor element ED is used. When it is desired to release the resistance by irradiating the ED with light to reduce the resistance, and to release the resistance reduction during inspection after mounting the driving IC or after completing the liquid crystal display element, the resistance element ED is mounted by mounting the driving IC. Since it is covered with the driving IC and is not irradiated with light, the decrease in resistance is canceled and the normal operation of the liquid crystal display element can be restored.

<< Manufacturing Flow Until Manufacturing of TFT Substrate and Mounting of Driving IC >> Next, referring to FIG. 8, a substrate on which a thin film transistor is formed (hereinafter abbreviated as a TFT substrate) S
The manufacturing flow of the UB1 will be described.

First, the TFT substrate SUB1 is manufactured (protective film PSV1) as described in << Method of manufacturing transparent insulating substrate SUB1 >> with reference to FIGS.
Until).

Next, a protective film (reference numeral P in FIG. 11G) is used.
After printing the alignment film on SV1), the alignment film is rubbed.

Next, the transparent insulating substrates SUB1 and SUB
After printing a sealing material around the edge of one of the two substrate surfaces, and spraying a large number of spacers, such as small spherical beads, that define the distance between the two substrates, on one of the substrate surfaces. Two substrates SUB1 and SUB2 are superposed and assembled. After that, the peripheral portion of the substrate SUB1 is cut along the cutting line CT1 in FIG.

Next, after the liquid crystal is sealed from the liquid crystal sealing port in which the sealing material is not provided between the substrates SUB1 and SUB2 in the area surrounded by the sealing material, the sealing port is made of a resin or the like. Seal with.

Next, referring to FIG. 1, the transparent conductive film IT
The short-circuit wiring SHc made of O, the drain terminal DTM, and the plurality of input wirings Td to the respective driving ICs are connected to, for example, cutting lines C1 and C inside the bump connecting portion BP shown in FIGS.
Cut at 2, C3, C4 with laser,
Release the short circuit.

Next, a lighting inspection is performed using an inspection probe, and a defective one such as a disconnection or a short circuit is repaired.

As a result of the lighting inspection, an anisotropic conductive film (see reference numeral ACF2 in FIG. 7) is attached to the one determined to be good.

Finally, after the driving IC is temporarily attached on the transparent insulating substrate SUB1 via the anisotropic conductive film, it is thermocompression bonded and mounted (see FIGS. 6, 7, and 14).

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. is there.

[0066]

As described above, according to the present invention,
A flip-chip liquid crystal display element capable of taking measures against static electricity, improving productivity, and reducing manufacturing cost in steps from wiring formation on a substrate on which a switching element is formed to before mounting a driving IC. A manufacturing method can be provided.

[Brief description of drawings]

FIG. 1 is a transparent insulating substrate SUB1 showing an embodiment of the present invention.
FIG. 3 is a plan view of the main part around the mounting portion of the driving IC and the vicinity of the cutting line CT1 of the substrate.

FIG. 2 is an enlarged detailed view of a portion D of FIG.

FIG. 3 is an enlarged detailed view of a portion E in FIG.

FIG. 4 is a cross-sectional view taken along the line FF of FIG.

FIG. 5 is a transparent insulating substrate S in the process of surface processing before cutting along the cutting line CT1 showing the above-mentioned embodiment of the present invention.
It is a whole top view of UB1.

FIG. 6 is a plan view showing a state in which a driving IC is mounted on a transparent insulating substrate SUB1 of a liquid crystal display element.

7 is a cross-sectional view taken along the line AA of FIG.

FIG. 8 is a diagram showing a manufacturing flow of the TFT substrate SUB1.

FIG. 9 is a flow chart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of steps A to C on the substrate SUB1 side.

FIG. 10 is a flow chart of a cross-sectional view of the pixel portion and the gate terminal portion showing the manufacturing steps of steps D to E on the side of the substrate SUB1.

FIG. 11 is a flow chart of a cross-sectional view of the pixel portion and the gate terminal portion showing the manufacturing steps of steps F to G on the side of the substrate SUB1.

FIG. 12 is a perspective view of the liquid crystal display module as seen from the front surface side after completion of assembly.

FIG. 13 is a block diagram showing a liquid crystal display panel of a liquid crystal display module and circuits arranged around the liquid crystal display panel.

FIG. 14 is a diagram showing a part of the manufacturing process for mounting the driving IC on the transparent insulating substrate SUB1.

[Explanation of symbols]

SUB1, SUB2 ... Transparent insulating substrate, SHc ... Short-circuit wiring, GL ... Gate line, DL ... Drain line, GTM ... Gate terminal, DTM ... Drain terminal, IC ... Driving IC, T
d ... Input wiring, C1, C2, C3, C4 ... Short-circuit wiring cutting line, SHg ... Gate short-circuit wiring, SHd ... Drain short-circuit wiring, CT1 ... Substrate cutting line, PAS1 (PSV1) ...
Protective film, ED ... Resistor element, d1, d2, d3 ... Conductive film, GI ... Insulating film, AS, d0 ... Amorphous semiconductor film, BP
... bump connection.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shiro Ueda 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Device Division

Claims (7)

[Claims] 1. A plurality of scanning signal lines on a surface of the first transparent insulating substrate on the liquid crystal layer side of two transparent insulating substrates stacked with a liquid crystal layer interposed therebetween, and a plurality of scanning signal lines insulated from the scanning signal lines. A plurality of video signal lines intersecting each other through a film are arranged in parallel, a switching element is provided near each intersection of the scanning signal line and the video signal line, and a driving IC is provided on the same substrate surface. In the mounted flip-chip type liquid crystal display element, a short circuit wiring is provided on the substrate surface at a location where the driving IC is mounted, and the scanning signal line or the video signal line and a plurality of driving circuit ICs are connected to the driving IC. A liquid crystal display element, wherein a book input line is connected to the short-circuit line. 2. The liquid crystal display element according to claim 1, wherein the short circuit wiring is formed of a transparent conductive film. 3. A plurality of scanning signal lines and a plurality of scanning signal lines on the surface of the first transparent insulating substrate on the side of the liquid crystal layer of the two transparent insulating substrates stacked with a liquid crystal layer interposed therebetween. A plurality of video signal lines intersecting each other through a film are arranged in parallel, a switching element is provided near each intersection of the scanning signal line and the video signal line, and a driving IC is provided on the same substrate surface. In the mounted flip-chip type liquid crystal display element, a resistor element is connected between the scanning signal lines or the video signal lines, which is a wiring portion on the output side of the driving IC. element. 4. The input wiring to the driving IC is the first wiring.
The liquid crystal display element according to claim 1 or 3, wherein the liquid crystal display element is connected to a common short-circuit line provided outside the cutting line of the transparent insulating substrate. 5. The driving IC, wherein the resistor element is configured to include a semiconductor film having photoconductivity and is mounted.
The liquid crystal display element according to claim 3, wherein the liquid crystal display element is formed under the. 6. A plurality of scanning signal lines on a surface of the first transparent insulating substrate on the liquid crystal layer side of the two transparent insulating substrates stacked with a liquid crystal layer in between, and a plurality of scanning signal lines insulated from the scanning signal lines. A plurality of video signal lines intersecting each other through a film are arranged in parallel, a switching element is provided near each intersection of the scanning signal line and the video signal line, and a driving IC is provided on the same substrate surface. In the method of manufacturing the mounted flip-chip type liquid crystal display element, a short circuit wiring is provided on the substrate surface at a portion where the driving IC is mounted, and the scanning signal line or the video signal line and the driving IC are connected to each other. A liquid crystal which is prepared in advance so that a plurality of input wirings are connected to the short-circuit wiring, and then the short-circuit wiring is cut before mounting the driving IC on the substrate surface. Display element manufacturing method. 7. The method of manufacturing a liquid crystal display device according to claim 6, wherein the cutting is performed by laser or photo etching.