JPH08280025A - Image signal encoder and image signal decoder - Google Patents

Abstract

PURPOSE: To improve efficiency for using a data bus by fixing the burst length of a storage means, storing plural kinds of image signals on the same row address while making column addresses different, and providing a memory control means for outputting a read command and successively designating the switching of plural column addresses. CONSTITUTION: Plural kinds of image information are stored on the same row address while fixing the burst length of the storage means composed of a synchronous DRAM. Then, after the row address is designated by an active command, the read command is outputted plural times, the plural column addresses are successively switched and designated, and the image signals on the different column addresses are read out. Namely, the image signal for each frame is sent to frame memories 3 and 4 composed of SDRAM to be controlled by a memory control circuit 5. Then, the column address to read the frame memories 3 and 4 is switched for every two clocks and the data of a macro block to be read are sent to motion compensation circuits 7 and 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a synchronous DRAM (Sync
The present invention relates to an image signal coding device and an image signal decoding device using a hronous DRAM) as a frame memory.

[0002]

2. Description of the Related Art Conventionally, an image signal coding apparatus and an image signal decoding apparatus have a frame memory for storing an image signal for each frame.

When a dynamic RAM (hereinafter referred to as DRAM), which is a large-capacity and low-cost volatile read / write memory, is used as the semiconductor memory used for the frame memory, the operation speed is not high, which causes a problem. There is. Further, the non-volatile static RAM has a problem that the storage capacity is small although the operation speed is high.

Therefore, a synchronous DRAM capable of continuous access at high speed, a so-called synchronous DRAM
(Synchronous DRAM: hereinafter referred to as SDRAM) is considered.

This SDRAM is a JEDEC (Joint El
ectron Device Engineering Council) compliant DRAM that performs high-speed burst transfer in synchronization with the rising edge of the input clock signal. The burst transfer is a method of continuously reading / writing data at the same row address in units of blocks of a plurality of words of 2, 4, or 8. The number of read / write words is called a burst length or burst length.

Since this SDRAM also has two banks, the access time while changing the row address is the same as the access time of a normal DRAM due to the necessity of precharging, but the bank is By alternately accessing, it is possible to write or read data in the other bank while precharging one bank.

However, in order to continuously write or read data while switching row addresses, it is necessary to set the number of clocks for writing or reading after giving a column address to 8 or more.

Here, the operation of the SDRAM will be described with reference to FIG. 5, which shows a timing chart at the time of random row read.

The burst length is set to 8, and two banks A and B are switched.

First, the read command CBa is output after the active command RBa for the bank B is output. As a result, after a certain period of time after the output of the read command CBa, specifically, three clocks later, the data reading QBa _{1 to} QBa ₈ of the bank B is sequentially performed.

Further, while the data of the bank B is being read, the active command RA of the bank A is
After a is output, the read command CAa is output. As a result, the data read QB of the bank B is
Read data from bank A QAa _{1 to} QA subsequent to a ₈
a ₈ is sequentially performed.

As described above, the burst length of 8 in the SDRAM means that data for eight consecutive addresses is written or read. When writing or reading data at consecutive addresses. In particular, the usage efficiency of the SDRAM data bus is high.

In order to access the SDRAM at high speed, it is necessary to set the number of clocks from the read command to the output of data to 3. This is a value in which the delay time from the input of a column address strobe (hereinafter referred to as CAS) to the data output is represented by the number of clocks, and is called CAS latency.

FIG. 6 shows the timing of CAS latency and command. Here, the burst length is 4.

For example, the operating clock is 25 to 50 MHz
, The CAS latency is set to 1, the CAS latency is set to 2 when the operation clock is 50 to 66 MHz, and the CAS latency is set to 3 when the operation clock is 66 MHz or more. When the CAS latency is 1, as shown in A of FIG. 6, the write command WA is output by the clock T _1, when the read command RB clock T ₂ is continuously output to the data DA ₁ is Data is read QB ₁ , QB ₂ , QB ₃ , and QB ₄ after one clock interval after writing. Also, CA
When the S latency is 2, as shown in B of FIG.
After the data DA ₁ has been written and two clock intervals have elapsed, data read QB ₁ , QB ₂ , QB ₃ and QB ₄ are performed. When the CAS latency is 3, C in FIG.
As shown in, the data read QB ₁ , QB ₂ , Q after the data DA ₁ has been written and three clock intervals have elapsed.
B _3, QB ₄ is performed.

[0016]

By the way, this SDR
AM is used for the frame memory of the image signal encoding device and the image signal decoding device, and the burst length of this SDRAM is 8
If the user wants to read a part of the data of consecutive addresses, the unnecessary addresses will be read because the addresses are consecutive.

For example, in compression coding of a moving image,
When performing discrete cosine transform (hereinafter referred to as DCT) processing, 8 × 8 pixel sub-blocks are used. Specifically, as shown in FIG. 7, four luminance signal DCT blocks Y ₁ , Y ₂ , Y ₃ , Y ₄ and two color difference signal DCT blocks C are provided.
r ₁ , Cr ₂ , and two color difference signal DCT blocks C
Eight DCTs consisting of b ₁ and Cb _{2 with} a total of 512 bytes
Use blocks. A block of 16 × 16 pixels in which a plurality of these DCT blocks are collected is called a macro block.
The size on the screen is the luminance signal Y and the color difference signals Cr and Cb.
Since and overlap, it becomes 16 × 16.

Therefore, as shown in FIG. 8, data of macroblocks at the same row address are read into banks 0 and 1 of the SDRAM, respectively. When the data of the same macroblock is recorded in the same row address, the control of the row address is less and the signal processing becomes easier.

In this way, when motion compensation is performed after the data of the macroblock is recorded and the motion vector is an integral multiple of the macroblock size, the data of the selected macroblock can be read from the frame memory as it is. good.

However, when the motion vector does not take a value that is an integral multiple of the macroblock size, it is necessary to read the data that spans a plurality of macroblocks.

Here, when the burst length in the SDRAM is set to 8, data can always be read only in units of 8 × 8 DCT blocks, so that much unnecessary data is read. For example, when the motion vector is an integer and the motion vector is (X, Y) = (2, 2), as shown in FIG. 9, when reading a macro block of the luminance signal Y,
(24 × 24) / (16 × 16) = 9/4 times the burst transfer of data is required. This is the color difference signals Cr, C
The same applies to the macroblock of b.

On the other hand, when the burst length is switched to 8 or less, several clocks are required to send the command,
Data cannot be transferred while the command is being sent.

Therefore, in view of the above situation, the present invention provides a method for accessing the SDRAM in small units of 8 or less,
It is an object of the present invention to provide an image signal encoding device and an image signal decoding device capable of accessing only necessary data without reducing the use efficiency of a data bus.

[0024]

An image signal coding apparatus according to the present invention has a burst length of a storage means fixed, and a plurality of types of image signals are stored on the same row address with different column addresses, and active. The above problem is solved by having a memory control means for outputting a plurality of read commands and sequentially switching a plurality of column addresses in a state where the row address is designated by a command.

Further, in the image signal decoding apparatus according to the present invention, the burst length of the storage means is fixed, a plurality of types of image signals are stored on the same row address with different column addresses, and the row command is sent by an active command. The above-mentioned problem is solved by having a memory control means for outputting a plurality of read commands and sequentially switching and designating a plurality of column addresses in a state where an address is designated.

[0026]

According to the present invention, the burst length of the storage means composed of the synchronous DRAM is fixed, a plurality of types of image signals are stored on the same row address, and the row address is designated by the active command. Times,
A read command is output and a plurality of column addresses are sequentially switched and designated, and image signals of different column addresses are read.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of an image signal coding apparatus according to the present invention, and FIG. 2 shows a schematic configuration of an image signal decoding apparatus according to the present invention.

The image signal coding apparatus shown in the embodiment of FIG. 1 performs image compression coding processing using correlation in the time direction, and records the compressed image data on a tape as a recording medium. In the image signal decoding apparatus shown in the embodiment of FIG. 2, the recorded image data is read out, subjected to image decompression decoding processing, and output as an image signal.

An MPEG (Moving Picture Exp) is used as a high-efficiency coding method utilizing the correlation of image signals in the time direction.
erts group) system, and in this MPEG system, an image of each frame is an I picture (Intra Picture:
Intra-picture coded or intra-coded picture), P picture (Predictive Picture: forward predictive coded picture), and B
A method of performing compression encoding by using any one of the three types of pictures of a picture (Bidirectionally predictive Picture) and combining the frame images of these three types of pictures is used. .

In the image signal coding apparatus shown in FIG. 1 and the image signal decoding apparatus shown in FIG. 2, it is assumed that the processing for switching between B picture and I picture is performed.

First, in the image signal coding apparatus of FIG. 1 on the recording side, a digital image signal for each frame is input from the signal input terminal 1. Here, the frame memories 3 and 4 composed of SDRAM are controlled by the memory control circuit 5, and for example, the image signal of the (N + 1) th frame image two frames before the (N-1) th frame image is Written in the frame memory 4, (N-
The image signal of the Nth frame image, which is one frame before the 1) th frame image, is written in the frame memory 3.

After that, the image signals of the (N-1) th frame image are input from the signal input terminal 1, and the image signals of the three frame images are sent to the motion vector detection circuit 6.

In the motion vector detection circuit 6, the motion vector between the (N + 1) th frame image in the frame memory 4 and the Nth frame image in the frame memory 3 and the motion vector in the frame memory 3 are detected. A motion vector between the Nth frame image and the (N-1) th frame image is detected.

When the image data to be output is B picture image data, the image signal of the (N + 1) th frame image written in the frame memory 4 is read out and sent to the motion compensation circuit 7. And (N-1)
The th frame image is sent to the motion compensation circuit 8.

Generally, the size of the DCT block used for the DCT processing described later is 8 × 8. If one pixel, that is, one pixel is 8 bits (= 1 byte), 1DC
The data amount of T block is 64 bytes. Four 8-bit wide SDRAM or 16-bit wide SDRA
If two Ms are used and the bit width of the SDRAM is 32 bits, 64/4 =
It requires 16 clocks. At this time, set the burst length to 8
Set to 32 in both bank 0 and bank 1
Recording each byte makes it easier to design the system.

The data is a luminance signal Y and a color difference signal C.
The macro block is composed of r and Cb, and exists in the same row address as shown in FIG. Therefore, when reading the data of the macroblock from the SDRAM, the column address to be read is switched every two clocks to generate the luminance signal Y and the color difference signals Cr and Cb at the same time by one burst transfer. Reduce burst transfer of unnecessary data.

Specifically, as shown in FIG.
When an active command for bank 0 is output at the 34th clock as shown in B of FIG. 2 when the clock signal of MHz is output, the column address of the macroblock data is switched every 2 clocks. ,
That is, read commands RD ₁ , RD ₂ , RD ₃ , and RD ₄ are output at the 37th, 39th, 41st, and 43rd clocks, respectively.
Specifically, for example, when reading the data of the macro block shown in FIG. 8, read commands RD ₁ , RD ₂ ,
Column addresses 0, _2, and ₃ are assigned to RD ₃ and RD _4.
The values of 2 and 48 are respectively substituted. As a result, FIG.
As indicated by C, the data of the macroblock of bank 0 whose column address is switched is sequentially read from the 40th clock to the 47th clock.

Similarly, when the active command of bank 1 is output at the 42nd clock, 45, 4
Read command R at clocks 7, 49 and 51
D ₁ , RD ₂ , RD ₃ and RD ₄ are output. This allows
Following the data of bank 0, the data of bank 1 whose column address has been switched is sequentially read from the 48th clock to the 55th clock.

The amount of data read in this way is
When reading the data of 16 × 16 bytes of the thick line shown in FIG. 3, it is sufficient to read only the data of 20 bytes in the horizontal direction and 24 bytes in the vertical direction, and 4 × 24 = 96 indicated by the hatched portion.
There is no need to transfer bytes of data. That is,
(20 × 24) / (16 × 16) = 15/8 times the data transfer amount will suffice. The reduction rate at this time is 17%
Is.

As a result, the occupied period of the data bus at the time of data transfer to the motion compensation circuits 7 and 8 is shortened, and the data transfer for other data processing can be allocated accordingly.

The motion vectors detected by the motion vector detecting circuit 6 are sent to the motion compensating circuits 7 and 8, and the motion compensating circuits 7 and 8 perform motion compensation using the motion vectors. The outputs from the motion compensation circuits 7 and 8 are added and averaged by an adder 9 to obtain a predicted value N _E. Further, the predicted value N _E is sent to the subtractor 10, and the difference between the predicted value N _E and the N-th frame image read out from the frame memory 3 is obtained, and the difference N _B is output to the terminal a of the signal switcher 11.

Here, the signal switch 11 is switched by the B / I select signal inputted from the signal input terminal 2, and switches the output of the image signal of the B picture or the I picture.

When the B / I select signal indicates the output of the B picture image signal, the signal switch 11 is switched to the terminal a, and the image compression is performed based on the difference N _B obtained through the terminal a. Be seen.

When the B / I select signal indicates the output of the image signal of the I picture, the image signal of the Nth frame image is output to the terminal b of the signal switcher 11. The signal switcher 11 is switched to the terminal b, and image compression is performed using the signal output via this terminal b.

The method of motion detection is not limited, but as a method of motion detection, a difference between pixels is calculated between corresponding blocks, and the difference is integrated in the block.
A method of using the block having the smallest integrated value for prediction is often used.

The image signal switched and output from the signal switch 11 is subjected to DCT processing by the DCT circuit 12 and the DCT coefficient is quantized by the quantization circuit 13,
The variable-length coding circuit 14 performs variable-length coding, and the image data is sent to the recording-coding circuit 15.

In the recording / coding circuit 15, the sent image data is added with the error correction code and the synchronization identification information together with the motion vector information and the B / I select signal from the motion vector detecting circuit 6, Recording coding such as channel coding for recording is performed.

The recording-coded signal is recorded on a tape (not shown) as a recording signal by the recording unit 16 including a recording amplifier and a head.

Next, in the image signal decoding apparatus of FIG. 4 on the reproducing side, a recording signal is read from a tape (not shown) by the reproducing unit 21 including a reproducing head and an amplifier. The read signal is used for the recording / decoding circuit 22.
At, the channel coding is restored and the error correction code and the motion vector information B / I select signal are separated.

Thereafter, the decoded image data is variable-length decoded by the variable-length decoding circuit 23, inverse-quantized by the inverse quantization circuit 24, and then inverse discrete cosine transform (hereinafter referred to as IDCT). The circuit 25 performs IDCT processing and outputs an image signal.

Here, when the image signal of the decoded frame image is an image signal processed as an I picture on the recording side, the frame image signal of this I picture is stored in the frame memory 26 composed of SDRAM. It is output to the terminal b of the signal switch 33 via the. The signal switch 33 is switched to the terminal b side by the B / I select signal separated by the recording / decoding circuit 22, and the image signal of the frame image of the I picture is output via the terminal b to the signal output terminal 3.
It is output from 4.

When the image signal of the decoded frame image is an image signal processed as a B picture on the recording side, this image signal is written in the frame memories 26 and 27 composed of SDRAM. In particular,
If the currently decoded frame image is the (N-1) th frame image, the image signal of the (N + 1) th frame image two frames before the (N-1) th frame image is the frame signal. The image signal of the Nth frame image which is written in the memory 27 and is one frame before is written in the frame memory 26. These frame memories 2
6, 27 are controlled by the memory control circuit 28.

In this way, the delayed image signal written in the frame memory 27 is read out by the same operation as the reading of data in the above-mentioned image signal encoding device and sent to the motion compensation circuit 29. , (N-
The image signal of the 1) th frame image is the motion compensation circuit 3
Sent to 0. The motion vectors separated by the recording / decoding circuit 22 are input to these motion compensation circuits 29 and 30, and motion compensation is performed using these motion vectors. The outputs from the motion compensation circuits 29 and 30 are added by the adder 3
An image signal which is arithmetically averaged by 1 and further calculated by the adder 32 with the image signal of the Nth frame image read from the frame memory 26 is output to the terminal a of the signal switch 33. . The signal switch 33 is switched to the terminal a side by the B / I select signal from the recording / decoding circuit 22, and is output from the signal output terminal 34 via the terminal a.

Although the burst length is set to 8 in the above embodiment, the burst length is not limited to 8.

The number of column address switching clocks is not limited to 2, and may be 4, for example.

[0056]

As is apparent from the above description, the image signal coding apparatus according to the present invention fixes the burst length of the storage means and allows a plurality of types of image signals to have different column addresses on the same row address. When the data for motion compensation is read out by having a memory control means for outputting a plurality of read commands and sequentially switching a plurality of column addresses in a state in which the row address is specified by the active command. Therefore, it becomes possible to carry out with a smaller burst transfer amount, and the use efficiency of the data bus can be improved.

Further, in the image signal decoding apparatus according to the present invention, the burst length of the storage means is fixed, a plurality of types of image signals are stored on the same row address with different column addresses, and the row command is sent by an active command. Having a memory control means for outputting a plurality of read commands and sequentially switching and designating a plurality of column addresses in a state where an address is designated, so that the data for motion compensation is read with a smaller burst transfer amount. It is possible to improve the use efficiency of the data bus.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an image signal encoding device according to the present invention.

FIG. 2 is a diagram showing a data read timing.

FIG. 3 is a diagram showing a read amount of data of a macro block.

FIG. 4 is a schematic configuration diagram of an image signal decoding device according to the present invention.

FIG. 5 is a diagram showing timing at the time of random row read of the SDRAM.

FIG. 6 is a diagram for explaining CAS latency.

FIG. 7 is a diagram showing a macro block.

FIG. 8 is a diagram showing data on the same row address.

FIG. 9 is a diagram showing a conventional macro block data read amount.

[Explanation of symbols]

 3, 4 frame memory 5 memory control circuit 6 motion vector detection circuit 7, 8 motion compensation circuit 9 adder 10 subtractor 11 signal switcher 12 DCT circuit 13 quantization circuit 14 variable length coding circuit 15 recording coding circuit 16 recording Unit 21 Playback unit 22 Recording decoding circuit 23 Variable length decoding circuit 24 Inverse quantization circuit 25 IDCT circuit 26, 27 Frame memory 28 Memory control circuit 29, 30 Motion compensation circuit 31, 32 Adder 33 Signal switcher

Claims (4)

[Claims] 1. An image signal coding apparatus for writing an image signal into a storage means comprising a synchronous DRAM and reading the written image signal for compression coding, wherein the burst length of the storage means is fixed and the same. Memory control means for storing a plurality of types of image signals on the row address at different column addresses and outputting a plurality of read commands to sequentially switch a plurality of column addresses while the row address is specified by an active command. An image signal encoding apparatus having: 2. The image signal coding apparatus according to claim 1, wherein the storage means is a frame memory used when performing signal processing for motion vector detection and motion compensation. 3. An image signal decoding apparatus for writing decompressed and decoded image data in a storage means composed of a synchronous DRAM and outputting the same, wherein a burst length of the storage means is fixed and a plurality of types of data are stored on the same row address. An image signal is stored with different column addresses, and a memory control means for outputting a plurality of read commands and sequentially switching a plurality of column addresses in a state where the row address is designated by an active command is provided. Image signal decoding device. 4. The image signal decoding apparatus according to claim 3, wherein the storage means is a frame memory used when performing signal processing for motion vector detection and motion compensation.