JPH08279739A - Control circuit for electronic circuit operation command - Google Patents

Abstract

(57) [Abstract] [Purpose] The operation command En to be given to the electronic circuit 20 is controlled so that the electronic circuit 20 does not malfunction even when the power supply voltage Vd changes unexpectedly. [Structure] A power supply voltage monitor circuit 30 monitors a power supply voltage Vd supplied to an electronic circuit 20, and when the value exceeds a predetermined set value, a control signal Sc is generated with a logic value of, for example, a high logic value. Is received by the continuation state confirmation circuit 40, and when it is confirmed that it has maintained a high logic value within a fixed time period, a permission signal Sd is generated, and for example, as the command control means 25 according to this permission signal Sd, AND By transmitting the operation command En to the electronic circuit 20 by putting the gate in the enabled state, the transient voltage distribution on the power supply line that receives it due to the fluctuation of the power supply voltage Vd becomes unstable and the electronic circuit 20 malfunctions. Try not to wake it up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for controlling operation commands to be given to operate various electronic circuits when necessary.

[0002]

2. Description of the Related Art In various electronic circuits or their circuit parts, it is sometimes desired to operate them only when necessary. In this case, it is customary to give an operation command to specify the operation timing. Further, there is a case where it is desired to give the operation command to the electronic circuit only when a predetermined condition is satisfied, such as immediately after the power is turned on. For this purpose, the control circuit for the operation command, which is the object of the present invention, is used. FIG. 4 shows an example thereof.

FIG. 4 shows a plurality of thermoelements 1 shown in the upper part of the drawing incorporated in the print head of a thermal printer.
1 shows an outline of a configuration of an integrated circuit device 10 for driving the.
Data PD to be printed by the thermoelement 1 is sequentially read and stored in synchronization with the clock pulse CP in the shift register constituted by the D-type flip-flop 11 shown in the lower part of the figure. Reference numeral 12 is a data PD or clock pulse
It is an amplifier for CP. The output circuit 20 in the integrated circuit device 10 incorporates a plurality of output transistors 21 and an AND gate 22 corresponding to the thermoelement 1, and the AND gate 22 stores print data PD at one input. It receives the stage output of the shift register from the corresponding flip-flop 11 and controls the gate of the output transistor 21 accordingly, and the output transistor 21 receives the power supply voltage V on the load side by the on / off operation according to the contents of the print data PD. It is adapted to drive the element 1.

However, the print data PD is the clock pulse CP.
Since the shift register is moved one stage at a time, it is necessary to store the print data PD in all the flip-flops 11 and then operate the output circuit 20. For this reason, the operation command En is set to the other of the AND gates 22. The operation timing is specified by giving it to the input and enabling it. However, when the circuit operation does not sufficiently rise immediately after the power supply to the integrated circuit device 10 is turned on or when the power supply voltage Vd is abnormally lowered due to an unexpected cause, the operation command En malfunctions. Printing occurs.

Therefore, in the conventional operation command control circuit,
As shown in the figure, an AND gate 25 that receives the control command Se at one input is provided in association with the output circuit 20, and the integrated circuit device
A power supply voltage monitoring circuit 30 is incorporated in 10 and a control signal Sc that becomes high only when the power supply voltage Vd is normal is applied to the other input of the AND gate 25. When the control signal Sc is high, the AND gate 25 is enabled, and the operation command En is simultaneously applied to the other inputs of the AND gate 22 of the output circuit 20 to enable it.

[0006]

As described above, in FIG. 4, malfunction should be prevented by controlling the operation command Se to be given to the electronic circuit which is the output circuit 20 by the control signal Sc from the power supply voltage monitoring circuit 30. However, it has been found that there is a rare problem that a malfunction occurs when noise enters the power supply voltage Vd or a so-called instantaneous blackout occurs.

This malfunction tends to occur as the degree of integration of the integrated circuit device 10 increases, and tends to occur as the number of thermoelements 1 to be driven by the output circuit 20 increases in the example of FIG. When the cause of the problem is investigated by using this tendency as a hint, a large number of circuit parts are connected to the power supply line in the integrated circuit device 10 which receives the power supply voltage Vd. It was found that there is a case where the normal power supply voltage is not received depending on the circuit part even if the power supply is normal.

That is, after noise intrusion or a momentary power failure, a non-uniform voltage distribution transiently occurs along the power line, which is a kind of distributed constant circuit, and some circuit parts have insufficient voltage. It is easy to cause malfunctions when power is not supplied. In the integrated circuit device 10 having a high degree of integration, the power supply line tends to be thin, and in the integrated circuit device 10 that drives a large number of loads such as the thermoelements 1, the number of circuit parts to be fed from the power supply line is large. The voltage along the line is non-uniform and therefore malfunctions are more likely to occur. The thicker the power supply line is, the lower its resistance value is, but the transient voltage distribution along the power supply line is also affected by other distribution constants such as capacitance, so that the nonuniformity of the voltage is not necessarily improved.

An object of the present invention is to solve the above problems of the prior art and provide an operation command control circuit which can more completely prevent a malfunction of an electronic circuit in the event of an unexpected fluctuation of a power supply voltage. .

[0010]

In a first control circuit for an operation command according to the present invention, a control signal which monitors a power supply voltage supplied to an electronic circuit and takes a predetermined logical value when the value exceeds a set value. A power supply voltage monitoring circuit that outputs a control signal, a sustain state confirmation circuit that outputs a permission signal when it receives a control signal and maintains a predetermined logic value within a fixed time period, and an operation command is transmitted to an electronic circuit according to the permission signal. To achieve the purpose.

In the above-described continuous state confirmation circuit, the shift register for sequentially transmitting the control signal received at the first stage to the next stage according to the clock, and the output from the shift register are aligned to a predetermined logical value. At this time, it is preferable to use a logic gate that opens a gate and issues a permission signal. Furthermore, a flip-flop that is set only when this logic gate is opened and is reset otherwise is provided, and its set output is used as a permission signal. As a result, the control operation can be ensured.

In the second control circuit according to the present invention, the power supply voltage monitoring circuit having the same structure as described above, and immediately after the operation command or the control signal is received, the circuit opens immediately in response to the change in the logical value, and then the predetermined time elapses. By using a timed switch circuit to be closed later and command control means for receiving a control signal from the power supply voltage monitoring circuit via this timed switch circuit and transmitting an operation command to an electronic circuit when it has a predetermined logical value To achieve.

The timed switch circuit in the above-mentioned configuration includes switch means for control signals such as analog switches, a delay circuit for receiving either an operation command or a control signal, a delay signal resulting therefrom and an original signal. Therefore, it is preferable to use a logic gate that closes the switch means only when the logic values of the two coincide with each other. Further, the logic value of the control signal is held within a short time between the switch means and the input side of the command control means. By providing the temporary holding circuit, the control operation can be made more reliable.

In a third control circuit according to the present invention, a similar power supply voltage monitoring circuit, a delay means for receiving a control signal from the power supply voltage monitoring circuit and delaying a change in its logical value for a predetermined time period, and a control signal via the delay means. And a command control means for transmitting an operation command to the electronic circuit when it has a predetermined logical value, the fourth control circuit according to the present invention further receives a power supply voltage for supplying power to the electronic circuit and outputs the detected value. A delay means for delaying the change for a predetermined time period, a power supply voltage monitoring circuit for issuing a control signal which compares the detected value of the power supply voltage with a set value and takes a predetermined logical value when the former exceeds the latter, and the control signal. And the command control means for transmitting the operation command to the electronic circuit when it has a predetermined logical value. The delay means for these third to fourth control circuits is the simplest to use as capacitors.
Further, in any of the first to fourth control circuits, an appropriate logic gate may be used as the command control means.

[0015]

According to the present invention, the cause of the conventional problem is that, after noise intrusion into the power source of the electronic circuit or its instantaneous interruption, a non-uniform voltage distribution occurs along the power source line for the power source voltage in the integrated circuit device as described above. Paying attention to the fact that there is a transient occurrence point, after confirming that the transient phenomenon has settled sufficiently after the occurrence of such an abnormality, or after setting a sufficient time period for allowing the transient phenomenon to settle Is given to an electronic circuit to operate it, thereby preventing the electronic circuit from malfunctioning due to a transient phenomenon.

That is, as described in the configuration in the preceding paragraph, in the first control circuit according to the present invention, the continuous state confirmation circuit which receives the control signal from the power supply voltage monitoring circuit has maintained a predetermined logical value within a fixed time period. After confirming that the control signal is given to the command control means, the second control circuit opens the control signal immediately when the logical value of the operation command changes and closes it after a predetermined time period. Is given to the command control means, the delay means delays the change of the logical value of the control signal within a predetermined time period in the third and fourth control circuits. In either case, a transient voltage distribution along the power supply line is generated. By giving the operation command to the electronic circuit after the change of the above is sufficiently settled, the malfunction can be almost completely prevented.

[0017]

Embodiments of the present invention will be described with reference to the drawings.
1 is a configuration example of a first control circuit in response to an operation command in the present invention, FIG. 2 is a configuration example of a second control circuit, and FIG.
5 and 6 are circuit diagrams respectively showing configuration examples of the fourth control circuit, and the same reference numerals are given to the portions corresponding to FIG. 4 in these drawings. In any of the embodiments, the electronic circuit to which the operation command is given is, for example, the output circuit 20 in the integrated circuit device 10 of FIG. 4, and the electronic circuit 20 is shown as a block in the figure for simplification.

In the embodiment shown in FIG. 1, the first control circuit for the operation command En for the electronic circuit 20 is a power supply voltage monitoring circuit 30 surrounded by an alternate long and short dash line, and a continuous state shown below the power supply voltage monitoring circuit 30. The confirmation circuit 40 and the command control means 25, which is an AND gate provided in association with the electronic circuit 20, are the same as those in FIG. The power supply voltage monitoring circuit 30 receives and monitors the same power supply voltage Vd for supplying power to the electronic circuit 20 as shown in the figure, but the power supply voltage Vd in the wiring of the power supply line in the integrated circuit device 10 of FIG. It is advisable to have this monitor the voltage at a location as close as possible to the power supply terminal receiving it.

In the illustrated example, the power supply voltage monitoring circuit 30 includes a current mirror circuit on the power supply side composed of transistors 31a and 31b,
A series resistor 31c of the reference transistor 31a of the power supply side current mirror circuit, which includes a ground side current mirror circuit including transistors 32a and 32b and a pair of comparison transistors 33 and 34.
The current set by the above is supplied from the driven transistor 31b to the pair of transistors 33 and 34, and the same current is made to flow in both by the ground side current mirror circuit which also serves as the load resistance of these transistors.

The pair of transistors 33 and 34 compares a voltage proportional to the power supply voltage Vd received by the latter gate with a reference voltage Vr received by the former gate. The reference voltage Vr is 2 in the illustrated example. It is made up of resistance-connected transistors 35 and series resistors 35a thereof, and the proportional voltage is made by dividing the power supply voltage Vd by the resistors 36a, 36b. The comparison result of these voltages is detected by the on / off state of the transistor 37,
The potential at the connection point with the series resistor 37a is derived as the control signal Sc via the inverter 37a. In the circuit configuration shown in the figure, the control signal Sc takes a high logic value when the power supply voltage Vd exceeds a predetermined set value by the reference voltage Vr. Note that the voltage dividing resistor
The series resistance 36c for 36a and 36b and the transistor 36a connected in parallel to the series resistance 36c are the power supply voltage by the power supply voltage monitoring circuit 30.
This is to add a history to the monitoring characteristic of Vd, and a series resistor 36c is added to the voltage dividing circuit when the control signal Sc is high by controlling the gate of the transistor 36a with a complementary signal from the inverter 37c of the control signal Sc. It is like this.

The sustaining state confirmation circuit 40 receives the control signal Sc and confirms that it has maintained a predetermined logical value, for example, a high state within a fixed time period, and then generates the permission signal Sd. In the illustrated example, a shift register 41 composed of two D-type flip-flops 41a and 41b, an AND gate 42, and an oscillator circuit 43 for generating a clock C for the shift register 41 are used. Control signal Sc is a shift register
It is given to the first stage of 41 and its two stage outputs are AND gates.
Given to 42. In the circuit example shown in the figure, the oscillator circuit 43 includes a resistor 43a and a capacitor 43b that form a time constant circuit, two inverters 43c that amplifies the potential at the connection point between them and outputs as a clock C, and a clock C as a time constant circuit. The negative feedback inverter 43d. Although the cycle of the clock C is appropriately set according to the application, it is usually 1 to several mS.

When the power supply voltage Vd exceeds a predetermined set value after the power is turned on or after a momentary power failure, the control signal Sc that the continuous state confirmation circuit 40 receives from the power supply voltage monitoring circuit 30 becomes high,
If this state lasts only for the time period set by the cycle of the clock C generated in the oscillation circuit 43, both of the two stage outputs of the shift register 41 in this example become high, so that the AND gate 42 receives these stage outputs. Is opened and its output becomes high, which confirms that the normal state of the power supply voltage Vd has been maintained for the predetermined time period.
The high output of the above may be used as it is as the permission signal Sd.

However, in the illustrated embodiment, in order to make this confirmation operation more accurate, a NAND gate 44a for receiving two outputs of the flip-flop 44 and the shift register 41 is provided.
Is provided so that the flip-flop 44 is set only when the AND gate 42 is opened, and is reset by the NAND gate 44a in all other cases, and the Q output or set output is used as the enable signal Sd. I will take it out. The command control means 25 that receives this permission signal Sd controls the transmission of the operation command En to the electronic circuit 20 according to its logical value, and in the example of the figure, a single logical gate that is an AND gate is used for this. That's fine. The AND gate as the command control means 25 of this embodiment is enabled only when the permission signal Sd is high, and the operation command En is sent to the electronic circuit 20.
Make it work by communicating against.

A second control circuit according to the present invention shown in FIG. 2 is a power supply voltage monitoring circuit 30 having the same configuration as that of FIG. 1, a time switch circuit 50 for receiving an operation command En in the example of the figure, and a time switch circuit 50 therethrough. Command control means 25 which receives the control signal Sc from the power supply voltage monitoring circuit 30 and when the logical value of the control signal Sc is high in this example with the timed switch circuit 50 closed, the command control means 25 issues an operation command. En is transmitted to the electronic circuit 20.
The command control means 25 is also a single AND gate in the circuit example of FIG.

The time limit switch means 50 performs an operation of immediately opening once according to a change in the logical value of the operation command En and then performing a closing operation after a predetermined time period elapses. Therefore, in the example of the figure, the switch means 51 which is an analog switch is used. A delay circuit that receives the operation command En and delays the change of its logical value for a predetermined time period.
A logic gate 53 which is an exclusive NOR gate is used in the figure in which 52 and the switch signal 51 are closed when the logic values of the delay signal and the operation command En are coincident with each other. In the illustrated example, the delay circuit 52 is composed of a resistor 52a and a capacitor 52b for a time limit, and two inverters 52c for amplifying the potential at the connection point between them and giving it to the logic gate 53.

In principle, the control signal Sc may be given to the AND gate of the command control means 25 via the switch means 51, but the logical value of the control signal Sc is set so that one of its inputs does not float when the switch means 51 is off. It is desirable to provide a holding circuit 54 for holding. In the illustrated example, the holding circuit 54 is composed of an inverter 54a, and a series circuit of an inverter 54b and a resistor 54c connected in anti-parallel to the inverter 54a.

In the circuit example of the second control circuit shown in FIG. 2, each time the logical value of the operation command En changes, the timed switch circuit 50 immediately turns off and turns on after the time period set by the delay circuit 52. , The control signal Sc only during the time when the power supply voltage Vd is easily affected by the change in the logic value of the operation command En
Can be disabled to prevent malfunction. As can be easily understood, if the control signal Sc is applied to the time switch circuit 50 of FIG. 2 instead of the operation command En, the operation substantially equivalent to that of the first control circuit using the continuous state confirmation circuit 40 of FIG. Can be done.

FIG. 3 relating to the third and fourth control circuits according to the present invention has a power supply voltage monitoring circuit 30 having substantially the same configuration as that of FIG.
Are surrounded by the one-dot chain line, and the corresponding parts are given the same reference numerals. This power supply voltage monitoring circuit 30 compares the value of the power supply voltage Vd with the value set by the reference voltage Vr, and sets the logical value of the control signal Sc to high when the former exceeds the latter, which is the same as the first control circuit. However, in the third control circuit according to the present invention, by connecting a capacitor as the delay means 60 between the gate and the drain of the transistor 37 which detects the comparison result, in the example of the figure, the change in the logical value of the control signal Sc is changed. The difference is that it is delayed by a predetermined time period. In the third control circuit, the control signal Sc is directly applied from the power supply voltage monitoring circuit 30 to the AND gate as the command control means 25.

When the power supply voltage Vd is lower than the predetermined set value, the transistor 37 is in the off state and the logic value of the control signal Sc is low.
When 37 turns on, the on operation is delayed by the time required to discharge the capacitor of the delay means 60, and therefore the timing at which the logical value of the control signal Sc changes to high is delayed. The time delay, which is the delay time, is set by the capacitance of the capacitor, and in order to have an appropriate time, it is usually set in the range of 10 to 100 pF.

In the fourth control circuit according to the present invention, a pair of comparison transistors 33 and 34 in the power supply voltage monitoring circuit 30 are used to delay the change in the detected value of the power supply voltage Vd to be compared with the reference voltage Vr. Therefore, in the example shown in the figure, a capacitor is connected between the gate of the transistor 34, which is the voltage dividing point of the voltage dividing circuit including the resistors 36a and 36b receiving the power supply voltage Vd, and the ground point as the delay means 70. In order to allow the delay means 70 to give an appropriate time limit to the change in the logical value of the control signal Sc, the resistors 36a and 36b are made to have a high resistance of about several MΩ, and the capacitor for the delay means 70 has a capacitance of about several tens pF. It is better to

This fourth control circuit is similar to the third control circuit only in that the connection point of the delay means 70 is different, and the operation of delaying the change in the logical value of the control signal Sc when the power supply voltage Vd changes is similar. Further, the control signal Sc is directly applied from the power supply voltage monitoring circuit 30 to the AND gate for the command control means 25. Therefore, the fourth control circuit can also achieve the same effect as the third control circuit. .

When the above-mentioned first and second control circuits according to the present invention are applied to the integrated circuit device 10 for driving the plurality of thermoelements 1 shown in FIG. Was given. The integrated circuit device 10 is a small chip of a few mm ² integrated according to the rule of 2 μm, and the output circuit 20 incorporates hundreds to 256 output transistors 21 having a current capacity of 10 mA and turns them on and off. The designated print data PD was loaded in the flip-flop 21 of the shift register with a clock pulse CP of several MHz.

[0033]

As described above, in the present invention, the cause of the conventional problem is that the voltage distribution on the power supply line which receives the power supply voltage in the integrated circuit device after noise intrusion into the power supply of the electronic circuit or its instantaneous blackout occurs. Paying attention to the fact that it becomes unstable, the first control circuit causes the persistence state confirmation circuit to confirm that the control signal has maintained the predetermined logical value within the predetermined time period, and the second control circuit issues the operation command. In response to a change in the logic value of the control circuit, the timed switch circuit is made to open once and then closed after a predetermined time period. In the third control circuit, the delay means delays the change in the logic value of the control signal for a predetermined time period. In the control circuit of No. 4, the power supply voltage monitoring circuit delays the change of the detected value of the power supply voltage to be compared with the set value by the delay means for a predetermined time period so that the voltage distribution of the power supply line is completely unstable in any case. Finished An operation instruction from the instruction control unit by a control signal and enable signal since so as to impart to the electronic circuit after it is possible to almost completely prevent malfunction of the electronic circuit due to instability of the voltage distribution of the power supply line.

The first embodiment of the continuous state confirmation circuit for the control circuit is composed of a shift register for receiving the control signal at the first stage and a logic gate for receiving the output of the stage, so that the confirmation of the continuous state of the logical value of the control signal is accurate. In addition, the mode of adding the flip-flop that is set when the logic gate is opened and is otherwise reset has the effect that the enable signal can be issued after confirming the sustain state more accurately.

The timed switch circuit for the second control circuit is a switch means, a delay circuit for receiving an operation command and the like, and a delay signal resulting therefrom and an original signal are received, and the switch means is closed when the logical values of both match. And a logic gate which has the effect of ensuring the timed operation with a simple circuit configuration, and further holds the logic value of the control signal within a short time between the timed switch circuit and the command control means. The mode in which the holding circuit is provided has the effect of ensuring the operation of the command control means.

The mode in which the capacitors are used as the delay means for the third and fourth control circuits has an effect that an accurate delay operation can be obtained only by adding simple circuit elements to the power supply voltage monitoring circuit. The mode in which the logic gate is used as the command control means for the fourth control circuit has the effect of simplifying the configuration of these control circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a specific configuration example of a first control circuit for an operation command according to the present invention together with an electronic circuit.

FIG. 2 is a circuit diagram showing a specific configuration example of a second control circuit according to the present invention.

FIG. 3 is a circuit diagram showing a specific configuration example of third and fourth control circuits according to the present invention.

FIG. 4 is a circuit diagram showing an operation command control circuit according to a conventional technique.

[Explanation of symbols]

20 Electronic circuit 25 AND gate as command control means 30 Power supply voltage monitoring circuit 33, 34 Transistor for voltage comparison 40 Continuous state confirmation circuit 41 Shift register 42 AND gate as logic gate 44 Flip-flop 50 Timed switch circuit 51 As switch means Analog switch 52 Delay circuit 53 Exclusive NOR gate as logic gate 54 Holding circuit for control signal 60 Capacitor as delay means 70 Capacitor as delay means En Operation command Sc Control signal by power supply voltage monitoring circuit Sd Sustained state confirmation circuit Enable signal Vd Power supply voltage Vr Reference voltage for setting comparison operation of power supply voltage monitoring circuit

Claims (10)

[Claims] 1. A circuit for controlling an operation command to be given to an electronic circuit, which monitors a power supply voltage supplied to the electronic circuit and issues a control signal having a predetermined logical value when the value exceeds a set value. A power supply voltage monitoring circuit, a sustaining state confirmation circuit that receives a control signal and issues a permission signal when it maintains a predetermined logical value within a fixed time period, and command control means that transmits an operation command to an electronic circuit according to the permission signal. An electronic circuit operation command control circuit, comprising: 2. The circuit according to claim 1, wherein a shift state register is provided with a shift register for receiving a control signal at a first stage and sequentially transmitting it to a next stage in response to a clock, as a continuous state confirming circuit, and receiving a predetermined output from the shift register. A control circuit for an operation command for an electronic circuit, comprising: a logic gate which opens a gate only when the logic values are aligned, and an enabling signal is issued when the logic gate is opened. 3. The circuit according to claim 2, further comprising a flip-flop which is set only when the logic gate is opened and is reset otherwise, so that the output of the flip-flop is taken out as a permission signal. A control circuit for an operation command for an electronic circuit, characterized in that 4. A circuit for controlling an operation command to be given to an electronic circuit, which monitors a power supply voltage supplied to the electronic circuit and issues a control signal having a predetermined logical value when the value exceeds a set value. A power supply voltage monitoring circuit, and a timed switch circuit which receives any one of an operation command and a control signal and immediately opens in response to a change in its logical value and then closes after a lapse of a predetermined time period,
Command control means for receiving a control signal from the power supply voltage monitoring circuit via the timed switch circuit and transmitting the operation command to the electronic circuit when the control signal has a predetermined logical value. Control circuit. 5. The circuit according to claim 4, wherein the timed switch circuit is a switch circuit, a delay circuit for receiving one of an operation command and a control signal, and a logic for both the delay signal and the original signal. A control circuit for an operation command for an electronic circuit, comprising: a logic gate that closes the switch means when the values match. 6. The operation command for an electronic circuit according to claim 4, wherein a temporary holding circuit for holding the logical value of the control signal within a short time is provided on the input side of the command control means. Control circuit. 7. A circuit for controlling an operation command to be given to an electronic circuit, wherein the value of a power supply voltage to be supplied to the electronic circuit is compared with a set value and a predetermined logical value is obtained when the former exceeds the latter. A power supply voltage monitoring circuit that emits a signal, a delay unit that receives a control signal from the delay unit to delay a change in its logical value for a predetermined time period, and a control signal that is received via the delay unit and operates when it has a predetermined logical value An electronic circuit operation command control circuit, comprising: a command control means for transmitting a command to an electronic circuit. 8. A circuit for controlling an operation command to be given to an electronic circuit, comprising delay means for receiving a power supply voltage for supplying power to the electronic circuit and delaying a change in a detection value thereof by a predetermined time period, and a delay means for this power supply voltage. A power supply voltage monitor circuit that compares the detected value with a set value and issues a control signal that takes a predetermined logical value when the former exceeds the latter, and an operation command when the control signal is received and has a predetermined logical value. And a command control means for transmitting the command to an electronic circuit operation command control circuit. 9. The circuit according to claim 7, wherein:
A control circuit for an operation command for an electronic circuit, which uses a capacitor as a delay means. 10. A circuit according to any one of claims 1, 4, 7 or 8, wherein the command control means is a logic gate.