JPH0827741B2 - Single-chip microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a single-chip microcomputer, the present invention outputs an access detection signal obtained by decoding an address in a test mode from an external terminal to generate a test time and a test pattern file. Save time.

[Industrial applications]

The present invention relates to a single-chip microcomputer, and more particularly to a single-chip microcomputer in which a CPU, an internal memory and peripheral circuits are incorporated on a single semiconductor chip.

Single-chip microcomputer is R in addition to CPU
It has internal memory such as OM and RAM, and peripheral circuits such as I / O port, timer, and A / D converter.

The above-mentioned single-chip microcomputer is connected to an external memory at the time of developing a program used by an individual user, and the program / debugging or the like using this external memory is performed.

Therefore, at the time of testing after connecting the tester after manufacturing the single-chip microcomputer, it is necessary to check whether the internal internal memory and peripheral circuits are properly accessed and the external memory is accessed.

[Conventional technology]

The conventional single-chip microcomputer does not output a signal for instructing access to the internal memory and peripheral circuits or access to the external memory to the outside.

Conventionally, the peripheral circuits are initialized, such as writing a predetermined value to the internal memory in advance before the test, and it is determined whether the value of the data output to the outside from the data bus during the test is the predetermined value. It is determined whether it is an access, an internal memory and a peripheral circuit, or an external memory.

Since the external memory is not connected during the test, the data on the data bus is all 1 when accessing the external memory.

[Problems to be solved by the invention]

The conventional single-chip microcomputer requires initialization of the internal memory and peripheral circuits before the test, and it is necessary to determine whether the data on the data bus has a predetermined value. In addition, there is a problem that it takes time to create a test pattern file which is a test data file in the tester.

The present invention has been made in view of the above points, and an object of the present invention is to provide a single-chip microcomputer in which a test time and a test pattern file creation time are short.

[Means for solving problems]

The single-chip microcomputer of the present invention is
CPU (11), internal memory (12,13), peripheral circuits (14-16)
The address of the address bus (18) that connects the Generate address decoder (1
7) and a signal for instructing the test mode. In the test mode, the access detection signal from the address decoder (17) is transferred from the external terminal (21 _n ) to the chip instead of the signal input or output in the normal mode. And a switch (22) for outputting to outside.

[Action]

In the present invention, the internal memory (1
2,13) and peripheral circuits (14-16) access and external (20)
An access detection signal is generated to distinguish the access from. The switch (22) switches and outputs the access detection signal from the external terminal (21n) in the test mode.

As a result, it is not necessary to initialize the internal memory and peripheral circuits before the test, and the test time can be shortened. Also, it is not necessary to determine whether the data on the data bus has a predetermined value, so the test pattern file can be created. It is easy and can shorten the creation time.

〔Example〕

FIG. 1 shows a block system diagram of an embodiment of a single-chip microcomputer of the present invention.

In the figure, the single-chip microcomputer 10 is
CPU11, internal RAM12 and internal ROM13 as internal memory,
I / O interface 14 as a peripheral circuit, timer 15, A
The / D converter 16 and the address decoder 17 are included. The CPU 11 and the internal memory and peripheral circuits are connected by an address bus 18 and a data bus 19, and the address decoder 17 is connected to the address bus 18.

An external memory 20 is connected to the address bus 18 and the data bus 19 when a program is developed by a user or the like.

The I / O interface 14 inputs / outputs n (integer) bit signals to / from the outside of the single-chip microcomputer 10. Only the I / O interface circuit 14 has n.
Of the bit terminals, the (n-1) bit terminal is directly connected to the external terminals 21 _{1 to} 21 _n-1 , and the remaining 1-bit terminal is connected to the external terminal 21 _n via the terminals a and c of the switch 22. It is connected to the.

When the CPU 11 accesses the internal RAM 12 or the internal ROM 13, the enable signal RAMEN,
Supply to ROMEN. Further, the CPU 11 generates the H-level control signal TDIR and supplies it to the control terminal of the switch 22 in the test direct mode in which the tester directly tests the internal memory and the peripheral circuits. In modes other than the test direct mode, the control signal TDIR is at L level.

The address decoder 17 decodes the address coming from the address bus 19 and supplies the enable signals IOEN, TEN, and ADEN to the peripheral circuits such as the I / O interface 14, the timer 15 and the A / D converter 16 respectively. The CPU 11 can access the peripheral circuits separately.

The address decoder 17 has an internal RAM 12 and an internal ROM 1 in the single-chip microcomputer 10.
3, I / O interface 14, timer 15, A / D converter 1
6 Generates an access detection signal ADS of L level when it is a value for accessing each of them and H level when the address is a value of accessing the external memory 20,
Supply to.

The switch 22 connects the terminals bc in the test direct mode in which the control signal TDIR is at the H level, and connects the terminals ac in the normal operation when the control signal TDIR is at the L level.

During the test, the tester is connected to the external terminals 21 _{1 to} 21 _n .

When the power of the single-chip microcomputer 10 is turned on, the reset sequence causes the I / O
The test data is taken into the CPU 11 via the O interface 14 and the data bus 18, and the test direct mode is set. As a result, the CPU 11 goes into the test direct mode from time t ₁ as shown in FIG.
After that, the switch 22 connects the terminals bc to each other, and the access detection signal ADS is output from the external terminal 21 _n as shown in FIG. 2 (B).

This access detection signal ADS is for time t ₁ t ₂ , t ₃ t ₄ , t ₅ t
The access to the internal memory and the peripheral circuit is instructed during the interval ₆ and the access to the external memory 20 is instructed during the times t ₂ t ₃ and t ₄ t ₅ .

When the test direct mode ends at time t ₆ , the switch 22 connects the terminals ac, and the output of the access detection signal from the external terminal 21 _n ends.

In this way, the address decoder 17 generates the access detection signal, and the access detection signal is output from the external terminal 21 _n via the switch 22 only in the test direct mode. Test time can be shortened without the need for initial setting. Further, since the access detection signal indicates the access to the internal memory and the peripheral circuit or the access to the external memory at the level, it is not necessary for the tester to check the value of the data on the data bus as in the conventional case. The creation time of test data, that is, the test pattern file is shortened.

Further, since the switch 22 switches the external terminal 21 _n to the output of the access detection signal ADS only in the test direct mode, the number of external terminals does not increase.

〔The invention's effect〕

As described above, according to the single-chip microcomputer of the present invention, the test time and the test pattern file creation time are shortened, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block system diagram of an embodiment of a single chip microcomputer of the present invention, and FIG. 2 is a signal waveform diagram of each part of the microcomputer shown in FIG. In FIG. 1, 10 is a single-chip microcomputer and 11 is a CP.
U, 12 is internal RAM, 13 is internal ROM, 14 is I / O interface, 15 is timer, 16 is A / D converter, 17 is address decoder, 18 is data bus, 19 is address bus, 20 is external memory, 21 _{1 to} 21 _n are external terminals, and 22 is a switch.

Claims (1)

[Claims] 1. A single chip which has an internal memory (12, 13) and peripheral circuits (14-16) in addition to a CPU (11) on a single chip and which can be connected to an external memory (20). -In a microcomputer, the CPU (11), internal memory (12, 13), peripheral circuits (14 to 1)
The address of the address bus (18) connecting 6) is decoded and the internal memory (12, 13) and peripheral circuits (14-1) are decoded.
6) The address decoder (17) that generates an access detection signal that distinguishes the internal access from the external access of the external memory (20) and the signal that instructs the test mode. Or a switch (22) for outputting an access detection signal from the address decoder (17) to the outside of the chip from an external terminal (21 _n ) instead of the output signal. Microcomputer.