JPH082756Y2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an image processing apparatus used for remote sensing image processing, medical image processing, and the like.

(Prior Art) Generally, an image processing apparatus includes a system control device 11, a processor (arithmetic device) 12, a memory (storage device) 13, an interface (input / output device), as shown in FIG.
Composed of 14. The system control device 11 decodes a command from a host computer (not shown) and controls each part of the device. First, when data input is instructed, image data is input to the memory 13 from the data bus (not shown) through the interface 14 and sequentially written in a predetermined memory area according to the write address from the processor 12. Next, when signal processing is instructed, corresponding image data is read from the memory 13 according to the read address from the processor 12 and input to the processor 12, where image processing is performed. This image processing data is rewritten in the memory 13 according to the write address of the processor 12, and is sent to the data bus through the interface 14 by the data output of the system control device 11.

As described above, in the conventional image processing apparatus, data is read from the memory 13 and image processing is performed by the control of the processor 12 based on a command from the system control apparatus 11. Here, the processor 12 and the memory 13 are connected by an address line A and a data line B, the write / read address generated in the processor 12 is sent to the memory 13 through the address line A, and the memory 13 is sent through the data line B. The data read by the processor is sent to the processor 12.

However, in the conventional image processing apparatus as described above, the address line A connecting the processor 12 and the memory is connected.
Depends on the performance of the processor, and when the memory is further added in parallel to expand the memory capacity of the memory (memory expansion), the number of bits of the address line A must be increased accordingly. I have to. To do this, the number of address lines is fixed on the processor 12 side, so change to the corresponding processor (or replace).
There is a need to. However, changing the processor requires redesigning the entire circuit, which is not easy.

(Problems to be Solved by the Invention) As described above, in the conventional image processing apparatus, it is indispensable to change the processor in accordance with the increase in the memory, so that it is not possible to easily request the expansion of the memory.

The present invention has been made to solve the above problems, and an object thereof is to provide an image processing apparatus that can easily cope with memory expansion without changing the processor.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, an image processing apparatus according to the present invention has a memory for storing image data and a read operation for the memory in response to a read / write command. / Function of generating write address, function of performing image processing on the image data read from the memory according to an image processing command and writing to the memory, output of read / write pulse used for generation of the read / write address And a read / write command for an extension area other than the area of the memory that can be designated by the processor, and an initial address for designating the extension area and change mode information for designating the address change. , According to the read / write command, according to the change mode from the initial address An auxiliary address generator that generates a read / write address for the extended area of the memory by counting the read / write pulses output from the processor, and a read / write command and an image for the processor according to an external control signal. A system control device having a function of giving a processing command, a command of reading / writing image data to an extension area of the memory, a function of giving an initial address and change mode information to the auxiliary address generator.

(Operation) The image processing apparatus having the above-described configuration is provided with an auxiliary address generator, and when the system control apparatus gives the auxiliary address generator a read / write command for the memory expansion area, an initial address for specifying the expansion area, Information of a change mode for designating an address change is given, and the auxiliary address generator counts the read / write pulse from the initial address according to the change mode, thereby reading / writing the extended area of the memory.
Since the write address is generated, even if the amount of image data increases and the memory storage capacity is expanded later, it can be expanded arbitrarily without depending on the number of addresses generated by the processor. The storage capacity can be secured.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows the configuration when the present invention is applied to the image processing apparatus shown in FIG. In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals.

In FIG. 1, reference numeral 15 is an auxiliary address generator. This auxiliary address generator 15 is a system control unit 11
And the processor 12 according to the control signal from the processor 12.
In association with the operation of the write / read address of the processor 12, an extended write / read address of the memory 13 is generated and the memory 13 is supplied through the address line A ′.
It is designed to be sent to.

Specifically, the system control device 11
Informs the processor 12 of the contents of processing, necessary coefficients, processing start instruction, and the like. Further, it notifies the auxiliary address generator 15 of an initial address value, an address change mode, etc., which differs depending on the contents of processing. Further interface
A command to start data transfer is sent to 14. Based on a command from the control device 11, the processor 12 stores the memory 13
Data is input from and image processing is performed.

The auxiliary address generator 15 is composed of an address control circuit 151 and an address generation circuit 152, as shown in FIG. The address control circuit 151 is the system control device 1
While storing the initial address and change mode from 1,
The write / read pulse from the processor 12 is input and counted, and the address generation of the address generation circuit 152 is controlled while comparing with the change mode. The address generation circuit 152 generates an address according to an instruction from the address control circuit 151, and outputs the generated address to the memory 13 at a predetermined level. That is, the control device 11 inputs an initial address and a change mode according to the processing content, and further, a write / read pulse is input from the processor 12, and an auxiliary address is output to the memory 13 in synchronization with this. The address is changed according to the setting of the change mode while internally counting the write / read pulse.

FIG. 3 shows an example of each address content of the processor 12 and the auxiliary address generator 15. In this example, m bits on the LSB (Least Significant Bit) side from the processor 12,
From the auxiliary address generator 15, the MSB (Most Significant Bi
It outputs (n−m) bits on the t) side.

Therefore, since the image processing apparatus having the above-mentioned configuration is provided with the auxiliary address generator for compensating for the insufficient address of the processor, even if the number of bits of the address line increases due to the memory expansion, the address can be easily addressed without changing the processor. The number of lines can be added. In other words, if the number of address output bits of the auxiliary address generator is set in accordance with the memory expansion, it is possible to easily cope with the memory expansion.

[Advantages of the Invention] As described above, according to the present invention, it is possible to provide an image processing apparatus that can easily cope with memory expansion without changing the processor.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an image processing apparatus according to the present invention, FIG. 2 is a block circuit diagram showing a concrete configuration of an auxiliary address generator of the embodiment, and FIG. FIG. 4 is a block circuit diagram showing a state where the number of bits of an address line for memory expansion is increased by the auxiliary address generator of the example, and FIG. 4 is a block circuit diagram showing a configuration of a conventional image processing apparatus. 11 …… System control device, 12 …… Processor,
13 ... Memory, 14 ... Interface, 15 ... Auxiliary address generator, 151 ... Address control circuit, 152 ... Address generation circuit.

Claims (1)

[Scope of utility model registration request] 1. A memory for storing image data, a function for generating a read / write address for the memory in response to a read / write command, and image processing for image data read from the memory in response to an image processing command. And a processor having a function of writing to the memory and outputting a read / write pulse used for generating the read / write address, and a read / write instruction to an extension area of the memory other than an area that can be designated by the processor. At the same time, an initial address designating the extension area and change mode information designating the address change are given, and read / output from the processor according to the change mode from the initial address according to the read / write command. Expansion of the memory by counting write pulses Area for generating a read / write address for an area, a function for giving a read / write instruction and an image processing instruction to the processor according to an external control signal, and image data for an extended area of the memory for the auxiliary address generator And a system control device having a function of giving a read / write command, an initial address, and change mode information.