JPH08273399A - Memory - Google Patents

Abstract

PURPOSE: To provide a read/write memory constituted such that a test can be carried out with small number of steps. CONSTITUTION: A column select circuit 40A switches a first mode for selecting any one block (e.g. block 11A) among a plurality of block 11A, 11B, 11C, 11D and a second mode for selecting memory cells (e.g. memory cells a00 , b00 , c00 , d00 ) arranged at corresponding positions in a plurality of blocks based on a test mode switching signal TEST-IN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory for storing data in a writable manner, and in particular, it stores a plurality of stored data in a readable and writable manner, inputs search data, and stores stored data corresponding to the input search data. The present invention relates to a memory suitable for being applied to an associative memory having a function of searching for.

[0002]

2. Description of the Related Art Conventionally, memories such as SRAMs for storing data in a readable and writable manner have been widely known. One of such memories is an associative memory (Associative Memo) having a search function as described above.
ry, content addressable memory; Content Add
Responsible Memory) has been proposed.

FIG. 17 is a circuit block diagram showing an example of an associative memory. The associative memory 10 has, for example, a large number of word memories 11_, each of which has 32 bits as one word and which is composed of 32 memory cells arranged in the lateral direction of the drawing.
1, 11_2, ..., 11_n are provided. The associative memory 10 also includes a search data register 12 into which search data of one word is input and latched, and a mask data register 13 in which mask data for masking the search data for each bit is stored.
Of the search data latched in the mask data register 13, all or a predetermined part of the bit pattern not masked by the mask data and the storage stored in each of the word memories 11_1, 11_2, ..., 11_n Matching mismatch between the bit pattern of the data and the bit pattern of the corresponding portion is compared, and matching lines 14_1, 14_2, ..., 1 provided corresponding to the word memories 11_1, 11_2, ..., 11_n, respectively.
A match signal of logic "1" is output to the match line for the word memory having the matched bit pattern of 4_n. Other match lines remain at logic '0'.

These matching lines 14_1, 14_2, ...,
The signal output to 14_n corresponds to each match flag register 1
5_1, 15_2, ..., 15_n. Here, as an example, as shown in the figure, the match flag registers 15_1, 15_2, ...
It is assumed that "1", "1", "0", ..., "0", "0" are stored. These match flag registers 15_
The signals stored in 1, 15_2, ..., 15_n are input to the address encoder 16, and from the address encoder 16, a match flag register (here, the match flag register 15_2 and the match flag are stored, in which a signal of logic “1” is stored. The address signal corresponding to the match flag register having the highest priority among the two (registers 2 </ b> _ 3 </ b> _ 3) is output. Here, it is assumed that the smaller the subscript, the higher the priority. Therefore, the memory address corresponding to the match flag register 15_2 is output here. The address signal AD output from the address encoder 16 is input to the decoder 17 as needed. In the decoder 17, the input address signal AD is decoded and word lines 18_1, 18_2, ..., And provided for the word memories 11_1, 11_2, ..., 11_n, respectively.
One of the word lines 18_n corresponding to the input address signal AD (here, word line 18_n
The access signal is output to 2). As a result, the data stored in the word memory 11_2 corresponding to the word line 18_2 to which the access signal is output is output to the output register 19
Read out.

FIG. 18 shows 1 in the associative memory shown in FIG.
It is a detailed circuit diagram showing one word memory. This word memory 11 has 32 memory cells 11 of the same configuration.
, 11_2, ..., 11_32.
Each memory cell 11_1, 11_2, ..., 11_32 is provided with first inverters 20_1, 20_2, ..., 20_32 and second inverters 21_1, 21_2, ..., 21_32 whose outputs are connected to their inputs. And these inverters 20_1, 21_1; 20_
, 21_32 stores 1-bit information of logic "1" or logic "0" in each memory cell 11_1, 11_2, ..., 11_32.

Further, each memory cell 11_1, 11_2,
..., 11_32, the first inverter 20_1,
The outputs of 20_2, ..., 20_32 are transistors 22_.
Bits 23_ via 1, 22_2, ..., 22_32
, 23_32, and the gates of the transistors 22_1, 22_2, ..., 22_32 are connected to the word line 24. The outputs of the second inverters 21_1, 21_2, ..., 21_32 are connected to the bit bar lines 26_1, 26_2, ..., 26_32 via the transistors 25_1, 25_2, ..., 25_32, and the transistors 25_1, 25_
The gates of 2, ..., 25_32 are also connected to the word line 24. Further, each memory cell 11_1, 11_2, ...
11_32, bit lines 23_1, 23_2,
..., 23_32 and bit bar lines 26_1, 26_2,
..., two transistors 27_1, 28_1; 2 connected in series with each other so as to connect between 26_32 and
7_2, 28_2; ...; 27_32, 28_32 are arranged, and these two transistors 27_1, 28 are provided.
_1; 27_2, 28_2; ...; 27_32, 28_3
One of the two transistors 27_1, 27_2,
The gate of 27_32 is the first inverter 20_1,
, 20_32, and the gates of the other transistors 28_1, 28_2, ..., 28_32 are connected to the outputs of the second inverters 21_1, 21_2 ,.

Further, the match line 140 is provided with each memory cell 11
, _1, 11_2, ..., 11_32, one by one, transistors 290_1, 290_2, ..., 290_32
Are provided, and those transistors 290_1,
290_2, ..., 290_2 are connected in series with each other, and their transistors 290_1, 290_2,
..., each gate of 290_32 has two transistors 27_1, 28_1; 27_2, 28_2;
It is connected to the midpoint of 32, 28_32.

Further, another transistor 290_0 is connected in series to the match line 140, and the left end of the match line 140 in FIG. 5 is the transistor 290_.
It is grounded through 0. This transistor 290_
The 0 gate is connected to the control line 300. Further, an inverter 310 is provided on the right side of this match line in FIG. 5, and the match line 140 also extends to the output side of this inverter 310, and each match flag register 15_1, 15_2 ,.
, 15_n (see FIG. 17). Two P-type transistors 320 and 330 are provided between the input of the inverter 310 and the power supply V _DD, and the gate of one of the P-type transistors 320 is connected to the control line 300 and the other is connected. The gate of the P-type transistor 330 is connected to the output of the inverter 310.

In order to write data to the associative memory having the word memory and the peripheral circuit having such a structure, the bit lines 23_1 and 23_ are to be written in the same manner as the normal SRAM.
2, ..., 23_32, the data to be written to, bit bar lines 26_1, 26_2, ..., 26_32 are loaded with data in which the logic of each bit of the data is inverted, and the word line 24 is raised to logic "1". , 11_32 are written into the memory cells 11_1, 11_2, ..., 11_32 bit by bit. At the time of reading, similarly to the normal SRAM, by raising the word line 24 to logic “1”, the memory cells 11_1, 11_2,
, 11_32 are read out via the bit lines 23_1, 23_2, ..., 23_32 and the bit bar lines 26_1, 26_2 ,.

Further, in the associative memory having the above structure, the matching search is performed as follows. First, the control line 300 becomes logic "0" and the P-type transistor 320
Becomes conductive and the match line 140 is precharged. At this time, the transistor 290_0 is turned off and the match line 140 is reliably separated from the ground line.
This ensures the precharge. In this way, the match line 140 is first precharged and then searched.

Here, it is assumed that information of logic "1" is stored in the memory cell 11_1. That is, in this case, the output side of the first inverter 20_1 is in the state of logic "1" and the output side of the second inverter 21_1 is in the state of logic "0". It is assumed that a search for logic "1" is performed on this memory cell 11_1. That is, the bit line 23_1 is set to logic "1" and the bit bar line 26_1 is set to logic "0". The word line 24 is held in the state of logic "0". Further, the control line 300 becomes logic “1”, and the transistor 290_0 is turned on. In this case, a logic "1" voltage is applied to the gate of the transistor 27_1 and a logic "1" signal of the bit line 23_1 is applied to the gate of the transistor 290_1, whereby the transistor 290_1 is turned on. That is, the memory cell 11
If the bit information stored in _1 matches the bit information in the search data input via the bit line 23_1 and the bit bar line 26_1, the corresponding transistor 2
90_1 becomes conductive.

The memory cell 11_2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20_2 is in the logic "0" state and the output side of the second inverter 21_2 is in the logic "1" state. It is assumed that a search for logic "1" is also performed on this memory cell 11_2. That is, the bit line 23_2 is set to logic "1", the bit bar line 26_2 is set to logic "0", and the control line 300 is set to logic "1". In this case, the signal on the bit bar line 26_2 in the logic '0' state is applied to the gate of the transistor 290_2 via the transistor 28_2, and thus this transistor 290_2
Will remain non-conducting. That is, in the case of a mismatch, the charges precharged on the match line 14 are not discharged.

Regarding the masked bits,
As shown in the memory cell 11_32, the bit line 23_3
2 and both of the bit bar lines 26_32 are set to logic "1". In this case, the memory cell 11_32 has a logic "1".
Either the transistor 27_32 or the transistor 28_32 is turned on depending on whether the information of 1 is stored or the information of logic '0' is stored, and in either case, the transistor 290_32 is turned on.

As described above, in the word memory shown in FIG. 18, the bit pattern stored in the word memory and the bit lines 23_1, 23_2, ..., 23_32 and the bit bar lines 26_1, 26_2 ,. If the bit pattern of the search data matches (the masked bits are considered to match as described above), the charges precharged on the match line 140 are the transistors 290_32 ,. 29
It flows out via 0_2, 290_1, 290_0,
As a result, the match line 140 is discharged, and the part of the match line 140 on the left side of the inverter 310 in FIG. 51 is in the logic “0” state. This logic “0” is inverted by the inverter 310, and a match signal of logic “1” is output from this inverter 310 and input to each match flag register 15_1, 15_2, ..., 15_32 (see FIG. 17).

Also, the bit patterns stored in the word memory and the bit lines 23_1, 23_2, ..., 23_32,
When the bit pattern of the search data input via the bit bar lines 26_1, 26_2, ..., 26_32 does not match, the match line 140 remains in the logic “1” state due to the precharge, and this logic “1”. 'Is inverted by the inverter 310 and a mismatch signal of logic' 0 'is output.

As described above, in the word memory shown in FIG. 18, the match line 140 has the P-type transistor 3 prior to the search.
Precharge via 20 and only if the search results in a match, the transistors 290_0, 290_1, 29
Since it is configured to be discharged via 0_2, ..., 290_32, most of the match lines are discharged in each search in most cases. Remains in a precharged state, so that the number of match lines that need to be precharged before the next search is small, and the power consumption associated with the search is suppressed.

The circuit configuration shown in FIG. 18 is merely an example.
, Various structures are known or considered
It FIG. 19 is a circuit of an associative memory having a plurality of blocks.
It is a block diagram. Here are four blocks as an example
11A, 11B, 11C, 11D are provided, each
The blocks 11A, 11B, 11C and 11D are respectively
64 (256 in total) word memories 11a₀ , 11
a₁ , ..., 11a₆₃; 11b₀ , 11b₁ , ..., 11b
₆₃; 11C₀ , 11C₁ , ..., 11C₆₃; 11d₀ , 1
1d ₁ , ..., 11d₆₃It is composed of Also each word
Memory 11a₀ , 11a₁, ..., 11a₆₃; 11b
₀ , 11b₁ , ..., 11b₆₃; 11C₀ , 11C₁ ,
…, 11C₆₃; 11d₀ , 11d₁ , ..., 11d₆₃Is
Here, for the sake of simplicity, each memory cell is composed of four memory cells.
It has been done. That is, in the example shown here, 4
One word is made up of bits. Here, for example
Word memory 11a ₀ The four memory cells that make up the
A from the most significant bit side₀₀, A₀₁, A₀₂, A₀₃Table like
Note that each memory cell a₀₀, A₀₁, A₀₂, A₀₃Stored in
Each bit data to be represented may be represented by the same symbol.
It The same applies to other word memories.

It should be noted that the functions relating to data retrieval in the associative memory are not shown in FIG. 19, and in the following, the function of reading and writing data, that is, the function of the SRAM in the associative memory will be described. . Further, this associative memory is provided with an address decoder 17, and this address decoder 17 has address data A ₂ , A ₃ , ..., A excluding the lower 2 bits of the address data AD consisting of 8 bits. ₇ is input, and the address decoder 17 outputs the address data A ₂ , A ₃ ,
,, 64 word lines 18 ₀ , 1 in response to input of A ₇
The address data A ₂ , out of 8 ₁ , ..., 18 ₆₃
Start up one line represented by A ₁ , ..., A ₇ . Each word line 18 ₀ , 18 ₁ , ..., 18 ₆₃ has four blocks 1
It extends over 1A, 11B, 11C and 11D.

The associative memory also includes a column selection circuit.
40 and a sense amplifier write driver 50 are provided
There is. The column selection circuit 40 stores the address data AD.
Lower 2 bits A₀ , A₁ Is entered and the column selection
The path 40 is the address data A₀ , A₁ Received the input of
Address data A of the four blocks
₀ , A₁ Bits extending from one block represented by
Connect the line and bit bar line to the column selection circuit 40 and the sense amplifier.
Bit line bit0 extending between the write driver 50 and
~ Bit3, connect to bit bar line bit0 'to bit3'
To continue. For example, address data A₀ , A₁ Together with
In the case of logic '0', the bit line bi extending to the block 11A
t_a0 to bit_a3 and bit bar line bit_a
0'-bit_a3 'and bit lines bit0-bit3
And bit bar lines bit0 'to bit3'.
It

When the input data DI is input from the outside,
The input data passes through the write driver in the sense amplifier / write driver 50, and the bit line bit between the sense amplifier / write driver 50 and the column selection circuit 40.
0～Bit3, are input into the block 11A via the bit bar line bit0'~bit3 ', word memory 11a ₀ located at the intersection between the selected word line (here, for example, a word line 18 ₀₎ Written in.
The same applies when reading data, for example, the word memory 1
When reading the data stored in 1a ₀ , when the word line 18 ₀ is activated in the same manner as above, the word memory 1
The data stored in 1a ₀ is the bit lines bit_a0
bit_a3, bit bar lines bit_a0 'to bit_
via a3 ', and further bit lines bit0 to bit3,
The data is input to the sense amplifier / write driver 50 via the bit bar lines bit0 ′ to bit3 ′, the sense amplifier detects the data, and the data is output to the outside as output data D0.

By the way, in the associative memory, one match line 140 (see FIG. 18) is required for each word memory for data retrieval, and the memory cells forming one word memory are separated from each other. Since it is extremely difficult to draw the coincidence line when arranging the memory cells in the memory cells, the memory cells forming one word memory are as shown in FIG.
They are sequentially arranged in adjacent positions.

After manufacturing this associative memory, it is necessary to test whether or not the associative memory operates normally.
During the test, it is necessary to check whether or not there is a short circuit between adjacent memory cells. Here, a case where a so-called march test, which is a method of performing the test, is applied to the associative memory having the configuration shown in FIG. 19 will be described, and the number of test patterns will be estimated together with it. Here, description will be given using the following symbols.

Dbus_w: External data bus width. FIG.
In the case of the associative memory shown in (the following description is omitted) dbus_w = 4 Words: the total number of words in the associative memory. Words = 2
56 bits: The number of bits forming one word. bits = 4 block_num: the number of blocks forming the associative memory. block_num = 4 block_size: The number of words forming one block. block_size = 64 W _x / R: write signal / read signal. Write "0" and read "1".

AD: Address. 00 (H) to FF
(H). 19 corresponds to A7, A6, ..., A2, A1, A0. In addition, (H) of XX (H) indicates that XX is an octal number. DATA: Input / output data. O (H) -F (H). FIG.
Corresponding to the input data DI and the output data DO. When writing (when W _x / R = 0), DATA is input data DI
Means that when reading (when W _x / R = 1), DAT
A means output data D0.

When the march test is applied to the associative memory shown in FIG. 19, the following procedure is taken. (1-1) First, as shown in Table 1, while sequentially incrementing the address AD, the addresses 00 (H) to FF are incremented.
Write 0 (H) to all word memories of (H).

[0026]

[Table 1]

As a result, "0" is written in all the memory cells forming all the word memories. The number of patterns required for this writing is: Words × bits / dbus_w = 256 × 4/4
= 256 is required. (1_2) Next, as shown in Table 2 and FIGS. 20 to 31, “0” is read and “1” is written so that the column of “1” advances on the bit plane.

[0028]

[Table 2]

20 to 31 show all the memory cells constituting each of the blocks 11A, 11B, 11C and 11D of the associative memory shown in FIG. 19, and "0" and "1" in each memory cell are shown. 'Indicates the bit data stored in each memory cell in that step, and the hatched portion represents the memory cell read in that step.

Table 2 represents the following steps. First, data is read from the address AD = 00 (H). The read data should be 0 (H) (see FIG. 20). Next, address AD = 00 (H)
The data DATA = 1 (H) is written in the. Next, the data is read from the address AD = 00 (H). The read data should be 1 (H) (see FIG. 21).

Next, the data DATA = 3 (H) is written in the address AD = 00 (H). Next, address AD =
Data is read from 00 (H). The read data should be 3 (H) (see FIG. 22). Thereafter, in the same manner, reading and writing are repeated so that "1" advances on the bit plane. When that is completed for one word memory, the operation moves to the next word memory, and reading and writing are repeated in the same manner (see FIGS. 20 to 31).

The number of patterns shown in Table 2 is bits × Wx / R × Words × bits / dbus.
_W = 4 × 2 × 256 × 4/4 = 2048. (1-3) Next, as shown in Table 3, "1" is read,
Write "0" so that the sequence of "0" advances on the bit plane. Illustration and detailed description are omitted.

[0033]

[Table 3]

The number of patterns shown in Table 3 is the same as that of Table 2, bits × Wx / R × Words × bits / dbus.
_W = 4 × 2 × 256 × 4/4 = 2048. (1-4) As shown in Table 4, 1 (H) is written in all the word memories of addresses 00 (H) to FF (H) while sequentially incrementing the address AD. Above (1-
This corresponds to the case where the write data 0 (H) in 1) is changed to F (H).

[0035]

[Table 4]

The number of patterns required for this writing is (1
-1), Words × bits / dbus_w = 256 × 4/4
= 256. (1-5) Read data is "1", write data is "1"
As 0 ',' 1 'is read and' 0 'is written so that the column of' 0 'advances on the bit plane (Table 5).
It corresponds to the bit data "1" and "0" of (1-2) described above reversed. The number of patterns is 2048, as in (1-2) above.

[0037]

[Table 5]

(1-6) Read data is "0", write data is "1", "0" is read, and "1" is written so that a column of "1" advances on the bit plane. (Table 6). The bit data "1", "(1-3)"
It corresponds to the opposite of 0 '. The number of patterns is 2048 as in (1-3) above.

[0039]

[Table 6]

The march test is performed on the associative memory shown in FIG. 19 by the above (1-1) to (1-6). The total number of steps between (1-1) to (1-6) is 8704.

[0041]

In recent years, the memory capacity of associative memories has been increasing, and the number of test patterns (the number of steps) for detecting a failure due to the influence between adjacent memory cells has been increased. There is a problem in that the test time increases and the test time becomes extremely long.

In view of the above circumstances, it is an object of the present invention to provide a readable / writable memory having a structure capable of performing a test with a small number of steps.

[0043]

Means for Solving the Problems A memory of the present invention which achieves the above object is provided with a plurality of word memories for storing word data consisting of an array of a plurality of bit data in a readable and writable manner, and is stored in each word memory. In a memory in which a plurality of memory cells each storing a plurality of bit data forming word data are sequentially arranged in adjacent positions, a first mode in which each of the word memories is read and written and input data is 1 bit Of the plurality of bit data decomposed into each of the plurality of word memories, simultaneously writing to each of the memory cells arranged in corresponding bit array positions forming each of the plurality of word memories, and of the bit data stored in each of these memory cells Equipped with a mode switching circuit for switching between the second mode for simultaneous reading It is characterized in.

Here, in the memory of the present invention, the plurality of word memories have an array structure which is decomposed into a plurality of blocks, and the plurality of word memories are used for writing data to or reading data from the word memory. Of the plurality of blocks, the block selection circuit includes a block selection circuit that selects a block including a word memory to which data is to be written or read, and the block selection circuit receives a predetermined access mode switching signal. The mode switching circuit is included by switching between a first mode for selecting any one of the blocks and a second mode for selecting memory cells arranged in corresponding bit arrangement positions of a plurality of blocks. It may be one that does.

The present invention is not applied only to an associative memory, but can be applied to, for example, a normal SRAM as long as the memory cells forming one word memory are arranged at positions adjacent to each other. Is. However, in an ordinary SRAM, the number of test steps can be reduced by arranging the memory cells forming one word memory at positions distant from each other. However, in the case of an associative memory, as described above, the match line Since the memory cells forming one word memory are inevitably arranged at positions adjacent to each other due to the routing, the present invention is suitable for an associative memory.

[0046]

Since the memory of the present invention is provided with the mode switching circuit described above, by switching to the second mode at the time of testing, one bit is simultaneously written into a plurality of word memories and one bit from a plurality of word memories. It is possible to read simultaneously, and it is possible to detect the presence or absence of a failure due to the influence between adjacent memory cells with a small number of steps. Therefore, according to the present invention, the problem that the test time is long, which has occurred as the associative memory has been increased in scale in recent years, can be solved at a considerably high level.

Although it is conceivable that the present invention slightly increases the circuit scale, for example, it takes a little extra time to write and read data, but in the case of an associative memory, data retrieval is usually performed. This is not a problem because access becomes a bottleneck and the cycle time of access is determined. When the present invention is applied to a normal SRAM,
It is possible that there will be some trade-off between fast access and reduced test time.

[0048]

Embodiments of the present invention will be described below. FIG. 1 is a circuit block diagram showing an example of an associative memory to which the present invention is applied. The same elements as those of the conventional associative memory shown in FIG. 19 are designated by the same reference numerals as those shown in FIG. 19, and only different points will be described.

The column selection circuit 40A of the associative memory shown in FIG. 1 receives the test mode switching signal TEST-IN in addition to the input / output line connected to the column selection circuit 40 of the associative memory shown in FIG. The control line of is added. FIG. 2 is an internal circuit diagram of the column selection circuit shown as a block in FIG. Test mode switching signal TEST-
If IN is set to logic '0', bit line bi extending to each block 11A, 11B, 11C, 11D shown in FIG.
t_a0 to bit_a3, bit_b0 to bit_b
3, bit_c0 to bit_c3, bit_d0 to bi
t_d3 and bit bar lines bit_a0 'to bit_
a3 ', bit_b0' to bit_b3 ', bit_c
0'-bit_c3 ', bit_d0'-bit_d
3 ', and bit lines bit0 to bit3 and bit bar line bit extending to the sense amplifier / write driver 50
0'to bit3 'are connected as follows according to the logic of the address data A1, A0.

[0050]

[Table 7]

On the other hand, the test mode switching signal TEST-I
When N is a logic '1', the connection state is as follows.

[0052]

[Table 8]

In this embodiment, the test mode switching signal TE
By performing the test with ST-IN set to logic '1', the presence or absence of a failure due to the influence between adjacent memory cells can be detected with a small number of steps, as will be described later. 3 and 4 are diagrams showing a partial circuit (A) and an improved circuit (B) in the column selection circuit shown in FIG.

A buffer depicted in column A of FIG. 2, a partial circuit composed of N-channel transistors connected to the buffer (FIG. 3A), and an AND gate depicted in column A of FIG. Partial circuit consisting of N-channel transistor connected to the AND gate (FIG. 3 (B))
Respectively as shown in FIG. 3 (B) and FIG. 4 (B),
It is preferable to change the N-channel transistor to a transfer gate and to change the circuit to which an inverter is added. With such a change, the signal is transmitted more smoothly through the bit line and the bit bar line.

When the march test is applied to the associative memory shown in FIG. 1, that is, the associative memory having the column selection circuit shown in FIG. 2, the following procedure is taken. At this time,
The test mode selection signal TEST-IN is set to "1". (2-1) First, as shown in Table 9, while incrementing the address AD sequentially, "0" is set to all memory cells.
Write.

[0056]

[Table 9]

The number of patterns required for this writing is: Words × bits / dbus_w = 256 × 4/4
= 256. The step (2-1) is the same as the step (1-1) of the above-mentioned conventional example (see FIG. 19). (2-2) Next, similarly to the step (1-2) described above, "0" is read out and "1" is written so that the column of "1" advances on the bit plane. However, the steps shown in Table 10 are taken here.

[0058]

[Table 10]

Table 10 represents the following steps. First, data is read from the address AD = 00 (H). As shown in FIG. 5, the data read at this time is a set of four bit data a ₀₀ , b ₀₀ , c ₀₀ , d ₀₀ , one for each of the four word memories, and O (H) is It should be read.

Next, the data D is stored at the address AD = 00 (H).
Write ATA = F (H). Thus, one each for each of the four-word memory, a total of four memory cells a _00, b _00, the c _00, d ₀₀ '1' is written. Next, the data is read from the address AD = 01 (H). At this time, as shown in FIG. 6, the data to be read is four bit data a that spans four word memories.
It is a set of ₀₁ , b ₀₁ , c ₀₁ , and d ₀₁ , and O (H) should be read.

Next, the data D is stored at the address AD = 01 (H).
Write ATA = F (H). This makes four notes
Recell a₀₁, B₀₁, C₀₁, D₀₁'1' is written in
It Next, the data is read from the address AD = 02 (H).
You The data read at this time is, as shown in FIG.
4 bit data a that spans 4 word memories ₀₂,
b₀₂, C₀₂, D₀₂, And O (H) is read out.
Should be.

Thereafter, in the same manner, on the bit plane, so that "1" advances simultaneously for the four word memories,
Repeat reading and writing. When it is finished for 4 word memories, move to the next 4 word memories,
Similarly, reading and writing are repeated (see FIGS. 5 to 16).
reference). The number of patterns shown in Table 10 is Wx / R × block_size × bits × block
k_num / dbus_w = 2 × 64 × 4 × 4/4 = 512. (2-3) Next, as shown in Table 11, the word memory 4
Read "1" at the same time and write "0" on the bit plane.
Write "0" so that the column of will progress. Illustration and description are omitted.

[0063]

[Table 11]

The number of patterns shown in Table 11 is Wx / R × block_size × bits × block as in Table 10.
k_num / dbus_w = 2 × 64 × 4 × 4/4 = 512. (2-4) As shown in Table 12, "1" is written in all the memory cells while sequentially incrementing the address AD.

[0065]

[Table 12]

The number of patterns required for this writing is
Similar to (2-1), Words × bits / dbus_w = 256 × 4/4
= 256. (2-5) Read data is "1", write data is "1"
As 0 ', 4 word memories are simultaneously' 1 '
Is read and "0" is written so that the column of "0" advances on the bit plane (Table 13). Above (2-2)
The bit data of "1" and "0" are reversed. The number of patterns is 512 as in (2-2) above.

[0067]

[Table 13]

(2-6) The read data is set to "0" and the write data is set to "1", and "0" is read out simultaneously for the four word memories, so that the column of "1" advances on the bit plane. Write in '(Table 14). It corresponds to the bit data "1" and "0" of (2-3) which are reversed. The number of patterns is the same as in (2-3) above.
512.

[0069]

[Table 14]

From the above (2-1) to (2-6), FIG.
A march test is performed on the associative memory shown in FIG. The total number of steps between (2-1) to (2-6) is 2560. As described above, the total number of steps when the march test is applied to the conventional associative memory shown in FIG. 19 is 8704, and in the case of the embodiments shown in FIGS. 1 and 3, the number of steps is 2560/8704 = about 30%.

The above comparison result is a comparison result for a march test included in a so-called N system (a test method that requires a number of test patterns proportional to the number N of memories), but a more accurate test. Is the 1.5th power of N,
Alternatively, when the N squared system test is performed, it is considered that the difference in test time becomes more remarkable.

[0072]

As described above, according to the present invention,
The test time can be significantly shortened.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an example of an associative memory to which the present invention is applied.

FIG. 2 is an internal circuit diagram of a column selection circuit shown in FIG.

FIG. 3 is a diagram showing a partial circuit and an improved circuit in the column selection circuit shown in FIG.

FIG. 4 is a diagram showing a partial circuit and an improved circuit in the column selection circuit shown in FIG.

5 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10. FIG.

FIG. 6 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 7 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 8 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 9 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 10 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 11 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 12 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10;

FIG. 13 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 14 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10;

FIG. 15 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 16 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 10.

FIG. 17 is a circuit block diagram showing an example of an associative memory.

18 is a detailed circuit diagram showing one word memory in the associative memory shown in FIG.

FIG. 19 is a circuit block diagram of an associative memory having a plurality of blocks.

FIG. 20 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 21 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 22 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 23 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 24 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 25 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 26 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 27 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 28 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 29 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 30 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

FIG. 31 is a diagram showing bit data stored in all memory cells in a step corresponding to Table 2;

[Explanation of symbols]

11A, 11B, 11C, 11D block 11a ₀ , 11a ₁ , ..., 11d ₆₃ word memory a ₀₀ , a ₀₁ , ..., d ₆₃ memory cell 17 address decoder 18 ₀ , 18 ₁ , ..., 18 ₆₃ word line 40A column selection Circuit 50 Sense Amplifier / Write Driver

Claims (2)

[Claims] 1. A memory cell comprising a plurality of word memories for readable and writable storage of word data composed of an array of a plurality of bit data, each storing a plurality of bit data constituting the word data stored in each word memory. In a memory in which a plurality of memory cells are sequentially arranged adjacent to each other, a first mode of reading and writing in units of the word memories and a plurality of word memories of a plurality of bit data obtained by decomposing input data bit by bit A mode switching circuit for switching between a second mode for simultaneously writing to memory cells arranged at mutually corresponding bit array positions and for simultaneously reading bit data stored in each of these memory cells. A memory characterized by having. 2. The plurality of word memories have an array structure that is decomposed into a plurality of blocks, and when writing data to the word memory or reading data from the word memory, data among the plurality of blocks is written. A block selection circuit that selects a block including a word memory that is a target for writing or reading data, the block selection circuit receiving a predetermined access mode switching signal, and any one of the plurality of blocks. By switching between a first mode for selecting a memory cell and a second mode for selecting memory cells arranged in corresponding bit arrangement positions of a plurality of blocks. The memory of claim 1, wherein the memory is a memory.