JPH08263374A - Cache control method and multiprocessor system using the same - Google Patents

Abstract

(57) [Summary] [Purpose] Cache match control is performed using a directory with a small capacity. A bit compression directory device 13 of each processor element (PE) divides a main memory 20 into a plurality of unit areas having a size larger than a line size of a cache device 11, and a bit compression directory in which the unit areas are used as a unit. Are held in correspondence with other PEs, and in each PE, when data is written in the main memory 20, cache coincidence control is executed using this bit compression directory device. The compression directory device 12 holds, for each unit area, a compression directory indicating the number of blocks cached in the cache device 11 of this PE and whether or not any of these blocks has been updated. According to the change of information, the other PE is instructed to update the bitmap directory of this PE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system including a plurality of processors which share a memory device with each other and each have a cache.

[0002]

2. Description of the Related Art In recent years, a tightly coupled multiprocessor system sharing a main memory has been put into practical use as one means for realizing a faster computer. Even in a tightly coupled multiprocessor system, each processor often has a cache in order to improve performance, as in the conventional single processor system.

In a system in which a plurality of processors each have a cache, there is a need for data consistency control (coherence control) between the caches. For example, if each processor rewrites the data of the same address in each cache, the value of the same address should originally be the same among the processors at the same time, but it may actually take different values. Occurs. In order to avoid such a situation, cache coherence control is performed. For example, when a processor rewrites data in the main memory, another processor that already has the data in the cache invalidates the data in its own cache.

A snoop cache method is one of the coherence control methods. In the snoop cache system, a plurality of processor elements are connected to a main memory shared by them through a common bus. When each processor element rewrites the data in the main memory, each processor element does not request the invalidation of the data in the cache to another specific processor element which holds the data in the cache. Instead, all other processors decide whether to invalidate the data in their cache. That is, each processor element is monitoring a data write request to the main memory issued from another processor element on this bus, and when such a write request is detected, each processor element recognizes itself. It is determined whether or not the data specified by this write request exists in the cache of, and if there is, that data is invalidated.

In this method, the processor element that has issued the write request does not determine which of the other processor elements holds the data of the address specified by the write request. It does not require a circuit for making a distinction. For this reason, this method is often used in systems that do not require relatively high performance.

Each time a processor element outputs a data write request to the main memory, each processor element hits whether or not the data at the address designated by the write request is held in its own cache. Need to check. For this hit check, the cache tag holding the address of the data held in the cache is accessed. It is also necessary to access this address tag in order to fulfill the main memory access request issued by the processor in this processor element, so that these two access requests conflict with respect to the use of the address tag. Become. As a result, the execution of the main memory access request issued by the processor is delayed. In many cases, the data specified by the main memory write request issued by another processor is not in my cache, and in such a case, many useless hit checks are preventing access to my processor. It will be.

As a method of avoiding this collision, in order to perform a plurality of hit checks for the same cache in parallel, an address used in the hit check of a write request issued from another processor element in each processor element. It is also known to provide tags separately from those used for hit checking for access requests issued by their processor. See, for example, Japanese Examined Patent Publication No. 40-40182 or U.S. Pat. No. 4,056,844 corresponding thereto.

Another typical method for performing coherence control is the directory method, which is often used in relatively large systems. For example, D Chaiken, GF
ields, K Kurihara and A Agarwal, ”Directroy-Based
Cache Coherence in Large-Scale Multiprocessors, ”I
See EEE Computer, June 1990, pp 49-58. In principle,
In the directory system, the main memory is divided into unit areas of the size of the cache block, and a directory containing information indicating in which cache the data of the area is registered, corresponding to each unit area, It is provided commonly to a plurality of processor elements.

For example, when one of the processors issues a data write request to the main memory, it is determined in which processor element the data of the address designated by the write request is held in the directory control circuit. Use this directory to determine,
When such a processor element is detected, the directory control circuit instructs the processor element to invalidate the data.

In this method, the directory control circuit is
Since invalidation requests are issued only to other processor elements that require invalidation of data, other processor elements other than such processor elements hit the cache with respect to write requests issued from other processor elements. No need to check. As a result, this directory method is less likely to interfere with the hit check for the main memory access by the processor in each processor element than the snoopy method.

Further, Japanese Patent Laid-Open No. 2-77858 discloses a system having a vector processor and a scalar processor sharing a main memory, the scalar processor having a cache memory and the vector processor not having the cache memory.
A block valid memory that divides the main memory into a plurality of unit areas that are equal in size to the blocks held in the cache in the scalar processor and has a block valid bit that indicates whether or not the blocks belonging to each unit area are held in the scalar processor. It holds a table called main memory. Furthermore, a block group valid table indicating whether or not at least one of the groups is held in the cache of the scalar processor for each block group in which the plurality of unit areas of the main memory are collected Have in main memory.

When writing from the vector processor to the main memory, the block group valid table held in the main memory is first referenced to determine whether the block to be written is held in the cache memory in the scalar processor. Is roughly checked, and after it is determined that the block is held by this check, the block valid memory is referenced to determine whether the block to be written is actually held in the scalar processor. Only when it is determined that the block is held, the scalar processor is notified of processing for cache coherence, for example, invalidation of the block. This prevents the scalar processor from performing an unnecessary cache hit check on the block designated by the write request when the vector processor writes to the main memory.

Further, in order to avoid a memory reference collision that occurs when referring to this block valid memory due to a large number of write requests, the block group valid table performs a rough sieving, whereby unnecessary writing is performed. It prevents the block valid memory from being referenced by a request.

[0014]

In the above directory system, the total number of directory entries is the value obtained by dividing the main memory capacity by the cache block size. For example, in a system having a main memory of 4 gigabytes (GB) and a cache block size of 4 bytes (B), the number of directory entries is 4 GB / 4B = 1 billion entries. For each entry, which processor element
Information on which processor element the block corresponding to the entry is held is held. Therefore, the size of each entry increases as the total number of processor elements increases. As a result, the total capacity of the directory increases as the main memory increases and the number of processor elements increases, and the cost of the memory for holding the directory increases. Further, the ratio of the memory for the directory to the area of the processor or the area of the system control LSI is not necessarily negligible. Therefore, it is desirable to reduce the capacity of the directory.

When the number of processor elements increases,
A method of reducing the capacity of the directory is also introduced in the above-mentioned document, for example.

By the way, in applications such as scientific and technological calculations in which the data sharing rate of each processor is low, the cache contents change less frequently due to cache coherence control. In other words, data in the address range accessed by one processor is rarely accessed by other processors, so even if cache coherence control occurs due to a cache miss in that processor, the contents of the cache of another processor will actually be affected. Changes less frequently. In applications where the data sharing rate of each processor is low,
The directory provided only for cache coherence is not effectively used as a resource. For such applications, further reduction of directory capacity is desirable.

Further, since the conventional directory is provided in the main memory or in the vicinity thereof in common to a plurality of processor elements, the directory is checked for a data write request generated in each processor element, and The result is notified to other processor elements. It is generally longer than the signal transmission time between the main memory and each processor element. Therefore, since it takes time to notify the concerned processor element of the result of the directory check, even if some data is updated in one of the processor elements, the cache in the other processor element that holds the same data as the data is updated. There is a problem that can not be immediately disabled.

An object of the present invention is to provide a cache control method capable of performing cache coherence control by using a directory having a smaller capacity than before, and a multiprocessor system using the cache control method.

Another object of the present invention is to provide a cache control method capable of executing a directory check in each processor element, and a multiprocessor system using the cache control method.

[0020]

In order to achieve the above object, according to the first invention of the present application, a storage device shared by a plurality of processor elements as a directory for a plurality of processor elements is set to a size larger than a first size of a cache block. A plurality of unit areas having a large second size are divided into a plurality of unit areas having at least one block that is cached by any of the processor elements, and the other unit areas corresponding to the plurality of unit areas. A first directory containing information for at least identifying the processor element is stored, and the first processor element is responsive to an access request issued by any one of the first processor elements to the storage device. In the first directory provided inside Then, it is detected whether or not there is a second processor element having another second cache that holds any block in the specific unit area to which the data of the address specified by the access request belongs, When the second processor element is detected, a request for executing a specific process for maintaining inter-cache coherence is selectively transmitted to the detected second processor element, and the second processor In the element, the second element in the processor element
It is checked whether or not a specific block having the address specified by the above access request actually exists in the cache of the second cache, and as a result of the hit check, the second block
If it is found that the particular block is actually present in the second cache, then the requested particular processing is performed for this second cache.

According to the first invention of the present application, since the information held by the directory has a size larger than the size of the block of the cache, the capacity of the directory can be reduced more than before. Furthermore, when an access request to the storage device is generated in any of the processor elements, when detecting whether the data specified by the access request is cached in another processor element,
Since the information held by the directory is larger than the size of the block of the cache, it is only necessary to detect whether or not there is a possibility that another processor element is caching. Therefore, in the other processor element determined to be caching, it is determined whether or not the data is actually cached, and then the cache matching control related to the access request is performed in the other processor element. It decides whether or not to execute.

Such a determination in the other processor element interferes with cache access by the processors in that processor element, but when the data shared between the processor elements is small, the adverse effect of such interference is practical. Can be reduced. Further, as a result of making such a determination, the data may not be cached by the other processor element. In such a case, this determination is not desirable processing for the other processor elements, but when the amount of data shared between the processor elements is small, such determination is not necessary frequently. Conceivable.

In order to achieve the above other objects, the second aspect of the present invention
In the invention, the directory related to each processor element is redundantly held in the processor elements other than the processor element, and when each processor element accesses any data, whether or not the data is cached in the other processor element is checked. When it is determined by the processor element and any other processor element is caching the data in the unit area to which the data belongs, the other processor element detected from the processor element executing the access Requests execution of processing for cache match control.

As a result, in each processor element,
It is possible to determine whether or not there is caching in the other processor element regarding the data to be accessed, and it is possible to request the other processor element to execute the process for cache match control according to the result of the determination.
Therefore, the directory search and subsequent processing become faster than the conventional directory method.

In this case, it is desirable that the ratio between the size of the unit area obtained by dividing the main memory and the size of the cache block is at least twice the total number of processor elements. In this case, even if the directories are arranged in a distributed manner in each processor element, the total capacity of the directories is still smaller than the conventional one.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The data processing device according to the present invention will be described in more detail below with reference to some embodiments shown in the drawings. In the following, the same reference numbers represent the same or similar items. Example 2
In the following description, only the points different from the first embodiment will be described.

<Embodiment 1> FIG. 1 is a schematic configuration diagram of an embodiment of a multiprocessor system according to the present invention. In the figure, 2 a to 2 d are processor elements, which share the main memory 20 connected to the bus 1. In the processor element 2a, an instruction processor (IP) 3 and a cache device 11 for holding a copy of the data in the main memory 20 are provided. These cache devices 11 are accessed by the instruction processor 3. The processor element further includes a bit compression directory device 13 that holds directory information for a compressed area regarding data held in a cache device of another processor element, and this cache device 1.
The compressed directory device 12 holds compressed directory information regarding the data held in 1.
Although not shown, the inside of the processors 2b to 2d has the same configuration as that of the processor 2a.

In this embodiment, the area of the main memory 20 is divided into unit areas each having a size larger than the size of the block held in the cache device 11 of each processor element.
For each of these unit areas, directory information indicating whether or not each processor element holds data belonging to the unit area is used. Therefore, the number of entries is smaller than when the size of the unit area is equal to the size of the block held in the cache.
In that sense, the compressed directory information is used in this embodiment.

More specifically, the bit compression directory device 13 holds compressed directory information regarding each of a plurality of other processor elements, as will be described later. This bit compression directory device 13
When the instruction processor 3 issues a request to write data to the main memory 20, it determines whether or not there is another processor element holding the data, and if any of the other processor elements receives the same data. When the data is held, the data in the other processor element is used for the control of so-called cache coherence so that the data held in the cache device 11 in the processor element 2a does not become inconsistent. It For example, the address of the data is specified, and the invalidation of the data is instructed at that address. In the other processor elements, in response to this invalid indication,
It is determined whether the data of the address specified by the invalidation instruction is held in the cache device 11, and if the block including the data is held in the cache device, the block is invalidated.

The bit compression directory device 13
Has directory information about a unit area larger than the size of the block held in the cache device 11, the result of the directory check by the bit compression directory device 13 indicates that the cache device in any of the other processor elements requests the write request. It is possible that the data specified by is not actually stored. This results in a wasteful cache check, resulting in a wasteful competition with respect to the cache check with the access by the instruction processor 3 in the other processor element. However, this useless contention is much less than in the conventional Snoopy scheme.
Further, when the data shared between the processor elements is limited to some extent, this useless competition is further reduced.

The compression directory device 12 holds the directory information regarding the processor element 2a including this device. This compressed directory device 12 notifies the other processor elements when the compressed directory information relating to this processor element has changed as a result of the data write request issued by the instruction processor 3 in this processor element. And is used to rewrite the contents of the bit compression directory unit 13 in those processor elements. Therefore, the compressed directory device 12 has different directory information from the bit compressed directory device 13.

As described above, in this embodiment, by using the compressed directory information, the total capacity of the directory information is reduced and the directory information regarding each processor element is distributed to other processor elements. Since they are arranged, the access to the directory information and the subsequent processing of the coherence control based on the directory information can be speeded up as compared with the method of centrally arranging the directory information regarding a plurality of processor elements in the main memory or in the vicinity thereof. There is. In this embodiment, the directory information regarding one processor element is duplicated and held in each of the other plurality of processor elements. Therefore, main memory 2
There is a possibility that the total capacity of the directory information will increase as compared with the case where the directory information related to all the processor elements is centrally arranged in or near 0, but in the present embodiment, the compression rate of the directory information is set to a high value to some extent. By doing so, the total capacity of the directory information is reduced as compared with the case where the directory information is concentrated in the main memory.

In FIG. 1, the processor element 2
Of the inside of a, only the part related to cache coherence control is shown, and the part related to normal instruction execution is not shown, but these are processed in the same way as a conventional processor. Further, in the following description, all the description without adding the processor name indicates the one in the processor 2a. For example, when described as "cache device 11", this indicates the cache device 11 in the processor 2a. When describing the cache device 11 of another processor, it is described as "cache device 11 in the processor 2b". It is of course possible that an expression such as "the cache device 11 in the processor 2a" is made without using the above abbreviations.

FIG. 2 is a diagram showing the internal construction of the cache device 11. In the figure, 30 is a cache memory, and 15 to 18 are fields included in each of a plurality of entries included in the cache memory 30, and 18 is a data section for holding one block, 1
5 is an address part for holding the address of the block, 1
6 is a valid bit (VB) indicating whether or not the data in the data portion of the entry is valid, and 17 is the case where the data is valid, after the data is loaded from the main memory 20 into the cache device 11, It is a store bit (DB) indicating whether or not it has been rewritten by the instruction processor 3. Caches having such fields are known per se. In this embodiment, the cache device 11 uses a store type cache.

FIG. 4 shows the bit compression directory device 13
It is the figure which showed the internal structure. In the figure, 54 to 56 are bit compression directories.

FIG. 6 shows bit compression directories 54 to 5
It is a figure which shows the structure of 6. Bit compression directory 54
Reference numerals 56 to 56 are tables in which the main memory is divided in address units, for example, 1 MB units, and each entry includes another valid bit 23 and another store bit 24. The bit compression directories 54 to 56 are provided corresponding to each of the other processors and indicate the cache states of the other processors. The other valid bit 23 is a bit indicating whether or not the data of the address in the address management unit is registered in the cache of the corresponding other processor, and the other store bit 24 is one of the data registered in this cache. , Store bit 17 is a bit indicating whether or not there is a value of DB = 1. Other effective bit 2
The values of 3 and the other store bit 24 are simultaneously updated when the original compression directory 40 is updated. In the present embodiment, the address management unit is set to 1 MB for convenience of description, but it goes without saying that the bit compression directories 54 to 56 and the compression directory 40 may have the same address division method.

FIG. 10 is a correspondence table showing which bit compression directories 54 to 56 in the processors 2a to 2d correspond to the compression directories 40 of the processors 2a to 2d. The bit compression directory reflects the contents of the compression directory in another processor. Each processor has a bit compression directory that corresponds to the compression directories of the other processors. Specifically, 54 in FIG. 4 is the processor 2b.
Is a bit compression directory corresponding to a compression directory in the processor 2c, 55 is a bit compression directory corresponding to a compression directory in the processor 2c (not shown), and 56 is a compression directory in the processor 2d. It is a bit compression directory corresponding to (not shown). Similarly, the processor 2b has a bit compression directory (not shown) corresponding to the compression directory 12 in the processor 2a, a bit compression directory (not shown) corresponding to a compression directory (not shown) in the processor 2c, and It has a bit compression directory (not shown) corresponding to the compression directory (not shown) in the processor 2d. The same applies to other processors.

In the present embodiment, the case where the number of processors is four is shown, but the number of processors may be other than this. In that case, the bit compression directories 54 to 56 are increased / decreased according to the number of processors,
The number may be one less than the number of processors.

FIG. 3 is a diagram showing an internal configuration of the compression directory device 12. In the figure, 40 is a compression directory.

FIG. 5 is a diagram showing the structure of the compression directory 40. The compression directory 40 is a table in which the main memory is divided by the same address unit as that used in the bit compression directory, for example, 1 MB, and each entry has 21 effective blocks and 22 strike blocks. The compression directory 40 is a device having information of the address section 15, the valid bit 16 and the store bit 17 of the entry of the cache memory 30 of the self processor. The number of valid blocks 21 records the result of counting how many VB = 1 entries exist in the cache memory 30 for each address in the address management unit (1 MB) of the compressed directory 40. Similarly,
The number of storage blocks 22 records the result of counting how many DB = 1 entries exist in the cache memory 30 for each address in the address management unit (1 MB) of the compressed directory 40. In this embodiment, the size of the main memory is 4 GB and the address is divided into 1 MB units, but it goes without saying that other values may be used.

(Outline of Operation) In the normal directory system, cache coherence control is performed by two kinds of operations. That is, updating of the contents of the cache of another processor (specifically, writing back of data to the main memory, or purging of data) that occurs due to directory reference being performed at the same time when each processor accesses its own cache, The contents of the directory are updated when the cache state changes due to the cache access of each processor. The cache coherence control of this embodiment is also performed by two similar operations. In the following, the term cache coherence control is also used when the cache is accessed by each processor.
It may be used to mean a request to update the cache contents of another processor and an update of the cache state of its own processor. This control is performed when the processor element, for example, 2a accesses the cache memory 30, and the result of the cache access and
Whether or not the data of the address accessed by the cache exists in the cache memory of the other processors 2b to 2d, or if it exists, the content of the data is stored in the main memory 20.
It takes different actions depending on whether it matches the contents of.

In the following, the cache access by the processor element 2a is taken as an example, and the case where the access result is 1) read hit, 2) read miss, 3) write hit, and 4) write miss will be described in order. The read hit indicates a state in which the cache is accessed for reading and the cache is hit. The same applies hereinafter. Whether the data of the address accessed by the cache in the processor 2a exists in the cache memory 30 of the other processors 2b to 2d, and if it exists, whether the content of the data matches the content of the main memory 20. Is determined by the bit compression directory device 13, and details of the determination will be described later. Here, the processing after the determination is performed will be described.

1) Read hit In this case, the processor 2a uses the cache memory 30.
Read data from the other processors 2b to 2d
The operation is ended without performing any special operation on the cache memory 30 of FIG. Further, the values of the valid bit 16 and the store bit 17 of the read entry remain unchanged (VB = 1 and DB remains unchanged).

2) Read Miss In this case, the operation changes depending on whether or not the data at the read-missed address exists in the cache memory 30 of the other processors 2b to 2d.

2a) When the data to be read does not exist in the cache memory 30 of another processor: The cache memory 30 of the processor 2a reads the data from the main memory 20 and stores the data in the data section 18
To be stored. The operation ends without performing any special operation on the cache memories 30 of the other processors 2b to 2d.

2b) When the data to be read exists in the cache memory 30 of another processor and the content of the data matches the content of the main memory 20, the same as in 2a) above, the cache memory 30 is The data is read from the memory 20, and the operation ends without performing any special operation on the cache memory 30 of the other processors 2b to 2d.

2c) When the data to be read exists in the cache memory 30 of another processor and the content of the data does not match the content of the main memory 20. A request for cache coherence control is issued by the processor 2a to the other processor 2b. From the cache memory 30 of the other processors 2b to 2d to the main memory 20 by the bit compression directory device 13, which is a device issuing to the other processors 2b to 2d, from the other processors 2b to 2d. Issue a request to do a return. When the write-back is completed, the value of the store bit 17 of the entry of the cache memory 30 of the other processors 2b to 2d that performed the write-back is DB = 1 to DB = 0.
Changes to (VB remains at 1). The completion of the write-back is notified to the cache memory 30 of the processor 2a, and the cache memory 30 of the processor 2a stores the data in the main memory 2
Read from 0.

In the case of a read miss, the cache coherence control is performed as described above, and the processor 2a
An entry for the newly read data is generated in the cache memory 30 of the above, and the value of the valid bit 16 is V
B = 1 and the value of the store bit 17 becomes DB = 0.

3) Write Hit In this case as well, as in the case of a read miss, the operation changes depending on whether or not the data at the address where the write hit exists in the cache memory 30 of the other processors 2b to 2d.

3a) When the data to be written does not exist in the cache memory 30 of the other processors 2b to 2d The processor 2a writes the data to the cache memory 30, but it is special for the cache memory 30 of the other processors 2b to 2d. The operation ends without performing any operation.

3b) When the data to be written exists in the cache memory 30 of the other processors 2b to 2d and the content of the data matches the content of the main memory 20. The processor 2a writes the data in the cache memory 30. At the same time, the bit compression directory device 13 issues a request to the other processors 2b to 2d to purge the data of the address from the cache memory 30. Other processors 2b to 2d that have accepted the purge
The value of the valid bit 16 of the cache memory 30 entry changes from VB = 1 to VB = 0. Processor 2
The a writes to the cache memory 30 of the processor 2a without waiting for the purging of the cache memory 30 of the other processors 2b to 2d.

In the case of a write hit, the cache coherence control as described above is performed. Then, the value of the store bit 17 of the entry in which the processor 2a writes the data in the cache memory 30 is set to DB = 1. The value of the valid bit 16 remains unchanged (VB = 1) and does not change.

In the cache coherence control described in the present embodiment, in the case of a write hit, the data which is write hit in the processor 2a exists in the cache memory 30 of the other processors 2b to 2d, and The data in the cache memories 30 of the other processors 2b to 2d will not be inconsistent with the main memory 20. Therefore, it is not necessary to consider the state corresponding to 2c) in the case of a read miss. This is because in the cache coherence control described in the present embodiment, when a read miss occurs, the cache line that matches with another processor is written back,
This is because purging of the cache line that coincides with that of another processor is performed during the write operation. Therefore, when the same data is shared by the cache memories 30 of a plurality of processors (the effective bit 1 of those cache memories is 1
(When 6 becomes VB = 1), the store bit 17 of the cache memory 30 of any processor never becomes DB = 1. Further, when the store bit 17 of the cache memory 30 in one processor is DB = 1, the data does not exist in the cache memory 30 of another processor.

4) Write Miss In this case, basically, the control of writing the data in the cache memory 30 is performed after the control of the read miss. Therefore, as in the case of the read miss, the data of the address where the write miss occurs is transmitted from the other processors 2b to 2d.
The operation changes depending on whether the cache memory 30 exists.

4a) When the data to be written does not exist in the cache memory 30 of the other processors 2b to 2d The cache memory 30 of the processor 2a reads the data from the main memory 20 and stores the data in the data section 18
To be stored. After storing, the instruction processor (IP) 3
Writes data to the cache memory 30. The operation ends without performing any special operation on the cache memories 30 of the other processors 2b to 2d.

4b) When the data to be written exists in the cache memory 30 of the other processors 2b to 2d and the content of the data matches the content of the main memory 20. The bit compression directory device 13 of the processor 2a
A request is issued to the other processors 2b to 2d to purge the data of the write-missed address from the cache memory 30 of the other processors 2b to 2d. As a result of the purge request, the value of the valid bit 16 of the entry of the cache memory 30 of the other processors 2b to 2d changes from VB = 1 to VB = 0 (DB remains 0). In parallel with the purge request, the cache memory 30 of the processor 2a reads data from the main memory 20 and stores the data in the data unit 18. After storing, the instruction processor (IP) 3 writes the data in the cache memory 30.

4c) When the data to be written exists in the cache memory 30 of the other processors 2b to 2d and the content of the data does not match the content of the main memory 20. The bit compression directory device 13 of the processor 2a
Two requests are issued to the other processors 2b to 2d for writing back the data of the write miss address from the cache memory 30 of the other processors 2b to 2d to the main memory 20, and for purging after the writing back. Issue. When the write-back and the purge are completed, the values of the valid bit 16 and the store bit 17 of the entries of the cache memories 30 of the other processors 2b to 2d that have performed the write-back become 0. The completion of the write-back is notified to the cache memory 30 of the processor 2a, the cache memory 30 of the processor 2a reads the data from the main memory 20,
The data is stored in the data section 18. After storing, the instruction processor (IP) 3 writes the data in the cache memory 30.

In the case of a write miss, the cache coherence control as described above is performed. Then, an entry for the newly read data is generated in the cache memory 30 of the processor 2a, the value of the valid bit 16 becomes VB = 1, and the value of the store bit 17 becomes DB = 1.
Becomes

In the case of a read miss and a write miss, the control for replacing another entry in order to newly create an entry is the same as that of the single processor, and the cache memory 30 of another processor is accompanied by the replacement. It does not change the state of.

(Details of Operation) In the following, at the time of accessing the cache memory 30 of a certain processor, whether the accessed data exists in the cache of the other processor, and if it exists, the content of the data is stored in the main memory 2.
How the bit compression directory device 13 determines whether or not it matches the content of 0, and
When this data exists in the cache of another processor, how to request the cache of the other processor to write back or purge its contents will be described in detail together with the configuration of the device. The description will be given by taking as an example the case where the cache memory 30 of the instruction processor (IP) 3 in the processor 2a is accessed, but the same applies to other processors.

First, the instruction processor (IP) 3 in the processor 2a accesses the cache memory 30. At this time, the arbitration circuit 4 causes the instruction processor (I
P) 3 is prioritized, the address indicated by the signal line L12 passes through the selector 10, is transmitted to the signal line L23, and the cache memory 30 is accessed. Then, at the address indicated by the signal line L12, the cache memory 3
At the same time as searching for 0, the bit compression directory 54
Searches from 56 to 56 are also performed. If the other valid bit and the other store bit of any of the entries of the bit compression directories 54 to 56 corresponding to this address are 0, the cache memories of the other processors 2b to 2d corresponding to the bit compression directories 54 to 56. At 30, the address accessed by the instruction processor (IP) 3 of the processor 2a does not exist.
In this case, it is not necessary to perform cache coherence control on the other processors 2b to 2d. Conversely, the bit compression directories 54 to 5 corresponding to this address
If the other valid bit 23 or the other store bit 24 of any of the entries 6 is 1, it indicates that the cache coherence control needs to be performed on the corresponding other processors 2b to 2d. , A cache coherence request is subsequently made by the bit compression directory device 13.

First, according to the information of the three signal lines L10, L13, L26 input to the coherency control request circuit 50, the coherency control request circuit 50 requires cache coherence control for access by the instruction processor (IP) 3. It is confirmed whether or not it is a kind of access, that is, whether the access is issued by the instruction processor (IP) 3 and the access to the cache memory 30 is a read miss, a write hit or a write miss. Then, if this condition is satisfied and L
When the other valid bit 23 or the other store bit 24 of any one of the entries of the bit compression directories 54 to 56 corresponding to the access address transmitted by 23 is 1, the type of access that requires cache coherence control It is determined that

In this case, an instruction is issued to the PE number sending circuit 51, and the other valid bit 23 or the other store bit 2 is sent.
The PE numbers of the bit compression directories 54 to 56 in which 4 is 1 are output to the shared bus 1 via the signal line L34. At the same time, the values of the other effective bit 23 and the other store bit 24 corresponding to the transmitted PE number from the bit compression directories 54 to 56 and the information indicating whether the access to the cache memory 30 is a read miss, a write hit or a write miss are displayed. The coherency type issuing circuit 53 received from the coherency control request circuit 50 outputs the type of cache coherence control to the signal line L35. The type of cache coherence control is the main memory 2 for the cache memory 30 of the processors 2b to 2d.
Request to write back to 0, or request to purge contents,
There are three types of requirements, or both requirements. The requirements are as described above. In addition, the coherency type issuing circuit 53 includes the other processors 2b to 2d.
The number and type of cache coherence control issued to the cache coherence control, that is, how many write-back requests and how many purge requests are generated, are counted, and the end determination circuit 38 in the cache device 11 is provided via the signal line L35. Send to. Further, the signal line L35 instructs the gate 8 to output the address indicated by the signal line L12, that is, the address to be the target of cache coherence control, to the shared bus 1.

In the following, as a specific example in the case where the type of cache coherence control is write back, a read miss occurs when accessing the cache memory 30 of the processor 2a, and at the same time, the signal line L23 indicates in the bit compression directory 54. A case will be described in which the write-back request is issued to the processor 2b because the values of the other valid bit 23 and the other store bit 24 of the entry corresponding to the address are both 1. First, processor 2
A cache coherence request (in this case, from the bit compression directory device 13 of a to the processor 2b)
(Data write-back request) is signal lines L12, L34, L3
5, which is as described above. The fact that the signal line L35 has issued the data write-back request
The main memory access control circuit 3 is input to the end determination circuit 38.
6 is transmitted. As a result, the main memory access control circuit 3
Reference numeral 6 temporarily suspends the access to the read-miss data until the end of the cache coherence request is notified by the signal line L05.

The PE number to be subjected to cache coherence control, which is output from the signal line L34, is input to the PE number comparison circuit 5 of the processor 2b via the signal line L03 of the processor 2b. When the PE number comparison circuit 5 of the processor 2b recognizes that this PE number indicates its own processor 2b, it operates the gates 6 and 7 of the processor 2b to output the information indicating the type of cache coherence control output from the signal line L35. To the signal line L of the processor 2b
04, the address output from the signal line L12, that is, the address to be the target of cache coherence control is transmitted to the signal line L02 of the processor 2b. Processor 2
The signal on the signal line L04 of b is input to the arbitration circuit 4 of the processor 2b, and the arbitration circuit 4 of the processor 2b recognizes this signal as a cache coherence request.

As a result of the arbitration, when the access of the cache memory 30 of the processor 2b for the cache coherence request is prioritized over the access of the instruction processor (IP) 3 of the processor 2b, the selector 10 in the processor 2b outputs the signal of the processor 2b. The signal on the line L02 is passed to the signal line L23. In addition, the signal line L of the processor 2b
The access type is transmitted to the cache memory registration / updating circuit 31 of the processor 2b via 14 that the access type is a cache coherence request, in this case, a write back request to the main memory 20. At this time, the cache memory registration / updating circuit 31 of the processor 2b first sets the processor 2 to the cache memory 30 of the processor 2b.
An instruction is given via the signal lines L40 and L41 of b to search whether or not there is data corresponding to the address indicated by the signal line L23 of the processor 2b.

As a result of the search, the comparator 33 of the processor 2b
Indicates that the addresses match, and when the value of the store bit 17 is 1, the data in the data portion corresponding to this address is controlled by the processor 2b under the control of the main memory access control circuit 36 of the processor 2b. Write back to the main memory 20 via the signal line L21. If, as a result of the search, the comparator 33 of the processor 2b does not indicate the match of the addresses, or if the addresses match but the value of the store bit 17 of the entry is 0, this write-back request is issued. Is an apparent problem that occurs because the address management unit of the compressed directory 40 is larger than the cache entry size. Originally, it is a request that does not require a write-back request. The update process of the cache memory 30 of the processor 2b ends without performing the process.

Main memory 2 for data in processor 2b
Completion of the write back processing to 0 is notified from the cache memory registration / update circuit 31 of the processor 2b to the end notification circuit 37 of the processor 2b. At this time, the processor 2b
The end notification circuit 37 determines whether the write-back is actually performed or the write-back request is apparent and the data is not actually written back, and outputs the signal to the signal line L07 of the processor 2b. To do. This is input to the end determination circuit 38 of the processor 2a via the shared bus 1 and the signal line L05 of the processor 2a. The end determination circuit 38 of the processor 2a notifies the main memory access control circuit 36 of the completion of the process of writing back the data to the main memory 20 in the processor 2b, and the main memory access control circuit 36 temporarily holds the read-missed data. Access again. The main memory access control circuit 36 uses the signal line L
A signal for accessing the main memory 20 is output to 06, and the read data is stored in the cache memory 30 via the signal line L21 and sent to the instruction processor (IP) 3 via the signal line L20. In this way, the cache coherence control is completed.

A specific operation example will be described with reference to FIG. In FIG. 7, it is assumed that the bit compression directory 54 reflects the compression directory 40 of the processor 2b in the processor 2a.
The description will be made assuming that 0 is for the processor 2b (state change of the cache memory 30 of the processor 2a is omitted). In FIG. 7, for the sake of explanation, the cache memory 30 has 6 entries and the data section 18 is omitted. The total address space of the main memory is 16 MB. In FIG. 7, all the entries in the cache memory 30 are registered. The registered address is 0x0002 as shown in the address section 15 in the figure.
00, 0x08F000, 0x0FF000, 0x100000, 0x1A0000, 0x2000
It is 00. The store bit 17 is set when the address is 0x000200, 0x0FF000, 0x1A000.
There are three entries, 0. The bit compression directory 54 reflects the state of the cache memory 30 and has addresses 0x000000 to 0x0FFFFF and 0x100000 to 0x1FFFFF.
The value of the other valid bit 23 and the other store bit 24 is 1, the value of the other valid bit 23 of the address 0x200000 to 0x2FFFFF is 1, and the value of the other store bit 24 is 0. The values of the other valid bit 23 and the other store bit 24 of the other addresses are 0. Since the compressed directory 40 will be described later in the description of updating the bit compressed directory 54, the description thereof will be omitted here.

Here, for example, the processing when the access to the address 0x100000 in the processor 2a becomes a read miss will be described as an example. The bit compression directory 54 is referred to when accessing the address 0x100000.
As a result of the reference, the other valid bit 23 and the other store bit 2 of the bit compression directory 54 corresponding to the address 0x100000
It can be seen that the values of 4 are both 1. That is, the cache memory 30 of the processor 2b has the address unit 15
It can be seen that there may be an entry with a value of 0x100000. In this case, a request for cache coherence control (writeback in this case) is further issued to the cache memory 30 of the processor 2b. When it is found that there is an entry whose value in the address section 15 is 0x100000 in the cache memory 30 of the processor 2b, the data of the entry is written back to the main memory 20. After this is completed, the processor 2a reads the data of the address 0x100000 from the main memory 20, and the series of processing is completed.

The above example is an example of writing back data, but data purging (or both writing back and purging) is processed in the same manner. However, in the case of only purging, the following points are different from the case of writing back. That is, in the case of write-back, the main memory access control circuit 36 accesses the read-missed (or write-hit, write-miss) data until the end determination circuit 38 is notified of the end of the cache coherence request by the signal line L05. Although it has been temporarily held, in the case of purging, the end of the cache coherence request is not notified by the signal line L05, and the main memory access control circuit 36 does not temporarily hold the access of the read miss (or write hit, write miss) data. , Immediately. Although the above example is for a read miss, the write-back process (or purge) for a write hit or write miss is also performed in the same manner.

In the above example, only the processor 2b is the target of the cache coherence request. However, when a plurality of cache coherence requests are generated in the bit compression directories 54 to 56,
As described above, the coherency type issuing circuit 53 counts the type and total number of cache coherence control issued to the other processors 2b to 2d, that is, how many write-back requests and how many purge requests have occurred. hand,
It is sent to the end determination circuit 38. The end determination circuit 38 stores how many of the cache coherence controls issued from the other processors 2b to 2d are write-back requests. If the number of write-back requests is 0,
Since the end of the cache coherence request is not notified by the signal line L05, the main memory access control circuit 36 does not temporarily hold the access of the read-miss (or write-hit, write-miss) data but immediately performs it. When the number of write-back requests is one or more, the main memory access control circuit 36 reads the data (or write hits or misses) until the signal line L05 indicates that the write-back is actually performed. Suspends access to. If all the write-back requests issued to the other processors 2b to 2d are apparent and it is not necessary to actually perform the write-back, the write-back request stored in advance by the end determination circuit 38 When the completion of the number of cache coherence requests is notified by the signal line L05, the temporary suspension of access is released, and the main memory access control circuit 36 restarts the access.

The specific example shown with reference to FIG. 7 is an example in which the write-back processing is actually performed in response to the write-back request. An example in which write-back processing is not performed is shown. For example, the processing when the access to the address 0x110000 in the processor 2a is a read miss will be described as an example. address
The bit compression directory 54 is referred to when accessing 0x110000. As a result of the reference, the other valid bit 2 of the bit compression directory 54 corresponding to the address 0x110000
It can be seen that the values of 3 and the other store bit 24 are both 1. That is, the cache memory 3 of the processor 2b
It can be seen that there is a possibility that an entry in which the value of the address part 15 is 0x110000 exists in 0. In this case, a request for cache coherence control (writeback in this case) is further issued to the cache memory 30 of the processor 2b. Actually, when it is found that there is no entry having the value of 0x110000 in the address section 15 in the cache memory 30 of the processor 2b, the end signal indicating that the write back is not performed is transmitted to the processor 2a. After receiving the end signal, the processor 2a sends the main memory 20
The data at address 0x110000 is read from, and a series of processing is completed.

As yet another example, an example will be shown in which, as a result of referring to the bit compression directory 54, it is found that cache coherence control is unnecessary for the other processor 2b. For example, suppose that a read miss occurs in access to the address 0x300000 in the processor 2a. The bit compression directory 54 is referred to when accessing the address 0x300000. As a result of the reference, the bit compression directory 54 corresponding to the address 0x300000
It can be seen that the values of the other valid bit 23 and the other store bit 24 are both 0. That is, the value of the address part 15 is 0x300000 in the cache memory 30 of the processor 2b.
It can be seen that there is no entry that indicates that there is no need to write back or purge the data in the cache memory 30 of the processor 2b. Therefore, the processor 2a reads the address 0x300000 from the main memory 20, and the series of processing is completed.

Next, the compressed directory device 1 is changed by the change of the cache memory 30 of a certain processor which is the latter of the above-mentioned two types of cache coherence control.
2 is rewritten, and subsequently, the operation of rewriting the bit compression directory device 13 in another processor will be described.

In the following, the case where the access is caused by the instruction processor (IP) 3 in the processor 2a is shown as a specific example, but the same applies to the cases of the processors 2b to 2d. In the initial state, the valid bits and store bits of all the entries of the cache memory 30 in the cache device 11 of all the processors are reset, and the valid count numbers 21 of all the entries of the compression directory 40 of all the processors 21, The value of the store count number 22 is 0, and the values of the other valid bit 23 and the other store bit 24 of all the entries of the bit compression directories 54 to 56 of all the processors are 0. Values in the initial state of the other parts are the same as those in the conventional processor.

The address for data access issued by the instruction processor (IP) 3 is output to the signal line L12. The arbitration circuit 4 accesses the cache device 11 of the instruction processor (IP) 3 and connects the shared bus 1 to the signal line L02.
And access of the cache device 11 for cache coherence brought through L04 (request to write back data of the cache device 11 to the main memory 20 or request to purge entry of the cache device 11), and signal lines L01 and L02. And access to update the contents of the bit-compressed directories 54-56 via As a result of the arbitration, when the instruction processor (IP) 3 is prioritized, the arbitration circuit 4 instructs the selector 10 via the signal line L13 to signal line L.
The 12 signals are passed to the signal line L23. Further, the arbitration circuit 4 gives an instruction to the cache memory registration / update circuit 31 via the signal line L14 to notify that the current cache access is by the instruction processor (IP) 3. The cache memory registration / update circuit 31 is a cache memory 30.
Is controlled, and a search is performed using the address of the signal line L23.

The search result by this address is the signal line L
The address of 23 is compared with the address of the comparator 33, and if they match, a cache hit occurs. If this comparator 3
If the comparison results of 3 do not match, a cache miss occurs. Information on whether the access is hit or miss is signal line L26.
Output by. In the case of a cache hit, the value of the valid bit 16 of the entry remains 1, but in the case of a cache miss, a new entry is generated by the cache memory registration / update circuit 31 and the value of the valid bit 16 becomes 1 is set. Also, replacement due to a cache miss or other processors 2b to 2d
When purging is performed as a result of the cache coherence control of 1, the value of the valid bit 16 of the entry is reset to 0 by the cache memory registration / update circuit 31. Such a change in the value of the effective bit 16 is detected by the comparator 34 and output to the signal line L24.

Further, whether the access type is read or write is input to the store bit update circuit 32 by the signal line L10, and the value of the store bit 17 of the cache memory 30 is updated. In the case of write, the value of the store bit 17 does not depend on the original value of the store bit update circuit 3
Set to 1 by 2. In the case of reading, the value of the store bit 17 does not change. Is the value of the store bit changed from 1 to 0 when the entry is replaced?
This is one of the cases where a write-back request is received from another processor. Such a change in the store bit 17 is detected by the comparator 35 and output to the signal line L25.

When the values of the valid bit 16 and the store bit 17 in the entry of the cache memory 30 change as described above, the changes are transmitted to the compression directory 40 via the signal lines L24 and L25, and the compression directory 40 is compressed. Update 40. The update is performed as follows. One of the signal lines L24 and L25 is a valid bit 16 or a store bit 1 in the entry of the cache memory 30.
7 indicates that the signal line L from the cache memory 30
The values of the effective count number 21 and the storage account number 22 of the entry of the compressed directory 40 corresponding to the address transmitted via 27 are read out, and the adders / subtractors 41 and 4
Sent to 2.

The adders / subtractors 41 and 42 add or subtract 1 to the values of the effective count number 21 and the strike account number 22 based on the change transmitted through the signal lines L24 and L25, and again the compression directory 40. Store it in the original entry of. Whether to add or subtract 1 is determined as follows. If the valid bit 16 of the cache memory 30 is set (changes from 0 to 1), 1 is added to the value of the valid count number 21 and the valid bit 16 is reset. For, the operation of subtracting 1 from the value of the effective count number 21 is performed.
The same applies to the case of the store bit 17.

When the entry of the compression directory 40 is updated, if the value before the update or the value after the update is 0 for either the value of the effective count number 21 or the value of the storage account number 22, , The zero detection circuits 43 and 44 detect this, and the bit compression directory update request circuit 45 sends the signal to the other processor 2 via the signal line L30.
Bit compression directories 54 to 56 corresponding to the compression directories 40 of the processors 2a existing in b to 2d
The update of the contents (not shown) is instructed for each processor.
The update is performed as follows.

When the zero detection circuits 43 and 44 detect that the value before the update of the entry of the compressed directory 40 or the value after the update is 0, the bit compressed directory update request circuit 45 causes the information (which entry The value of the other valid bit 23 or the other store bit 24 is changed from 0 to 0) is output to the shared bus 1 via the signal line L30, and is transmitted to all the other processors 2b to 2d. .. Further, the signal line L30 operates the gate 9 to output the signal of the signal line L27, that is, the information indicating the address of the entry, to the shared bus 1.

An example in which the processor 2b receives the signals on the signal lines L27 and L30 and updates the contents of the bit compression directories 54 to 56 (not shown) is shown below, but the same applies to the other processors 2c to 2d. Processing is performed. Further, in FIG. 1, the components inside the processor 2b are omitted and not shown, but in the following, a notice to those not shown is omitted.

The signal on the signal line L30 is input to the arbitration circuit 4 in the processor 2b and the distribution circuit 52 in the processor 2b via the signal line L01 in the processor 2b. Further, the signal line L01 operates the gate 6 to allow the signal of the signal line L02 to pass. As a result of the arbitration performed by the arbitration circuit 4 in the processor 2b, priority is given to updating the bit compression directory 54 in the processor 2b.
The selector 10 in the processor 2b is instructed via 13 to pass the signal of the signal line L02 in the processor 2b. To the signal line L02 in the processor 2b, the address of the entry of the compressed directory 40 whose value before update or value after update, which was previously output from the signal line L27 in the processor 2a to the shared bus 1, was 0. Is stored and points to the entry of the bit compression directory 54 in the processor 2b to be updated.

The distribution circuit 52 in the processor 2b selects the bit compression directory 54 in the processor 2b to be updated from the bit compression directories 54 to 56 in the connected processor 2b.
When the value of the effective count number 21 of the compressed directory 40 in a changes to 0, the other effective bit 23 is set to 0,
When the value of the valid count number 21 changes from 0 to non-zero, the other valid bit 23 is set to 1. Other store bit 24
With respect to, the same update is performed based on the change in the value of the strike account number 22. The compression directory 40 in the processor 2a and the bit compression directory 54 in the processor 2b are updated as described above.

The compression directory 40 and the bit compression directories 54 to 56 in the other processors.
Is not only caused by the access to the cache memory 30 of the instruction processor (IP) 3, but also because of the access to the cache memory 30 for cache coherence control from another processor, which is described above. Valid bit 1 of cache memory 30 entry
It is also performed when a change occurs in 6 or the store bit 17. Also in this case, the update is performed in the same manner as the procedure for updating the compressed directory 40. Further, the bit compression directories 54 to 56 are updated in the same manner.

As a concrete example, the operation of the cache memory 30, the compression directory 40, and the bit compression directories 54 to 56, which are the main components of this embodiment, will be described in detail with reference to FIGS. 7 to 9. . Regarding the state of the cache memory 30, as described above,
All entries are registered. The registered addresses are 0x000200, 0x08F000, 0x0FF000, 0x100000, 0x1A00 as shown in the address section 15 in the figure.
The numbers are 00 and 0x200000. Of the six entries, the address of the address part 15 falls within the range of 0x000000 to 0x0FFFFF for the three entries 1 to 3, and therefore the addresses 0x000000 to 0x of the compressed directory 40.
The value of the effective count number 21 of the entry corresponding to 0FFFFF is 3. Since only two of the cache entries 1 to 3 have the store bit 17 set, the addresses 0x000000 to 0x0FFF of the compressed directory 40 are stored.
The value of the strike account number 22 of the entry corresponding to FF is 2
Becomes Similarly, among the entries registered in the cache memory 30, those having addresses within the range of 0x100000 to 0x1FFFFF are two entries 4 to 5,
Since only one entry has store bit 17 set, the address of compressed directory 40
The value of the valid count number 21 of the entry corresponding to 0x100000 to 0x1FFFFF is 2, and the value of the store account number 22 is 1.
Becomes Similarly, the address of the compressed directory 40
The value of the effective count number 21 and the value of the strike account number 22 of the entries corresponding to 0x200000 to 0x2FFFFF are 1. The values of the valid count number 21 and the strike account number 22 of other entries are all 0.

The bit compression directory 54 has the same address management unit as that of the compression directory 40, and whether the values of the effective count number 21 and the strike account number 22 of the compression directory 40 are 0 is another effective bit 23, another store bit 24. I remember.

In the case of FIG. 7, the value of the effective count number 21 of the compression directory 40 is non-zero at the address 0x0000.
00 to 0x0FFFFF, 0x100000 to 0x1FFFFF, 0x200000 to 0x2FFF
The entry corresponding to FF and the value of the storage account number 22 is non-zero is the address 0x000000 to 0x0FFFFF, 0x.
Since this is an entry corresponding to 100000 to 0x1FFFFF, these parts take the value 1 and the other parts are 0.

Next, from the state shown in FIG. 7, the cache memory 30
The case where the sixth entry of is deleted will be described with reference to FIG. In FIG. 8, the cache memory 30
Since the sixth entry of No. has disappeared, the valid bit 16 of that entry is 0. Accordingly, the value of the effective count number 21 of the entry corresponding to the addresses 0x200000 to 0x2FFFFF of the compression directory 40 is 1 as compared with the case of FIG.
The value decreases only to 0. Since the value of the store count number 22 was originally 0, no change occurs in this case. The change in the value of the effective count number 21 of the compression directory 40 is reflected in the bit compression directory 54,
The value of the other valid bit 23 of the entry corresponding to the address 0x200000 to 0x2FFFFF changes from 1 to 0.

Further, a case where a new address is registered in the sixth entry of the cache memory 30 from the state of FIG. 8 will be described with reference to FIG. In FIG. 9, a new address 0x0A0000 is registered in the sixth entry of the cache memory 30. At this time, the values of the valid bit 16 and the store bit 17 are both 1. Along with this, addresses 0x000000 to 0x of the compressed directory 40
The values of the effective count number 21 and the storage account number 22 of the entry corresponding to 0FFFFF are increased by 1 from the case of FIG. 8 and are changed to 4 and 3. In this case, the effective count number 21 and the strike account number 22 of the compressed directory 40
Since the value of is neither changed to 0 nor changed from 0, no change occurs in the bit compression directory 54,
It remains the same as before.

The present embodiment is a modification of the method generally called the directory method, and the bit compression directory 5
4 to 56 correspond to directories in the normal directory system. In a general directory system, a system in which a single directory has cache information of all processors is well known, but in the present embodiment, the bit compression directory 5 corresponding to the directory is used.
4 to 56 are provided corresponding to each processor.
A feature of this embodiment is that a directory in a normal directory system has cache coherence information in a cache line size unit, while an address is managed in a unit larger than a line size. As a result, it is possible to significantly reduce the size of the directory (the number of entries) which is a problem in the normal directory method. The update of the bit compression directories 54 to 56 is performed using the compression directory 40 in order to manage the address in a large unit. Further, in this embodiment, a plurality of bit compression directories 54 to 56 provided corresponding to each processor are prepared and arranged in each processor. Therefore, when each processor accesses its own cache, whether or not it is necessary to perform cache coherence control with respect to the cache of another processor,
It can be judged by its own processor. Therefore, the number of inquiries to other processors for cache coherence control can be reduced, and the system performance can be improved.

Usually, in the general directory system, the physical quantity of the directory is large, so that it is not realistic to arrange the directory in each processor. In this embodiment, the bit compression directories 54 to 56 and the compression directory 40, which have a large address management unit, are used.
The problem that the quantity becomes large is solved by using. This will be described using an equation. The size of the main memory is M
(Unit is KB), address management unit is A (unit is K
B), the line size of the cache is L (unit is KB),
If the number of processors is N and the value of F given by the following equation is smaller than 1, the method of the present embodiment can reduce the physical quantity of the directory as compared with the general directory method. The value of F is the bit compression directories 54 to 56 and the compression directory 4 in this embodiment.
The ratio of the physical quantity of 0 to the physical quantity of the directory in the general directory system is shown. The smaller this value is, the smaller the physical quantity in this embodiment is.

[0095]

## EQU00001 ## F = [2N.times. (Log (A / L) + N-1) .times.M / A] / [(1 + N) .times.M / L] (1) (assuming the log base is 2) In the above formula, the denominator is the size of the physical quantity of the directory in the general directory system, and the numerator is the size of the physical quantity of the bit compression directories 54 to 56 and the compression directory 40 in this embodiment (the unit is bit. ). The above equation can be transformed into the following by making an approximation that N is sufficiently larger than 1.

[0096]

## EQU00002 ## F = 2N.times.L / A (2) The conditions for making F smaller than 1 are as follows.

[0097]

## EQU00003 ## A / L> 2N (3) That is, if the address management unit of the bit compression directories 54 to 56 and the compression directory 40 is set to 2N times or more the size of the line size of the cache, the method of this embodiment is The physical quantity can be made smaller than that of a general directory system. For applications with low data sharing rate of each processor, such as scientific computing,
Address management unit is the cache line size (usually 4
B to about 16B), so F
It can be seen that it is easy to make the value of less than 1. For example, when the address management unit is 1 MB and the cache line size is 4 B, the value of F becomes smaller than 1 when the number of processors is about 100,000 or less. If the number of processors is from a dozen to a few dozen,
The value of F is about 1/1000 to 1/10000, and the physical quantity required for the directory of the present embodiment is 1/1000 to that of the general directory system.
It can be seen that the size is about 1/10000.

As described above, in this embodiment, cache coherence control using the bit compression directory is performed. In the case of the normal directory method, when the main storage capacity is 16 MB as described in this embodiment, the number of entries is 16 MB / 4B = 4 million (assuming the cache line size is 4B). However, by setting the address management unit to 1 MB and a value larger than the line size of the cache as in this embodiment, the number of entries in the compressed directory and the bit compressed directory is 16 M.
B / 1MB = 16, which can be much smaller.

<Modification of First Embodiment> (1) In the first embodiment, the update between the compression directory and the bit compression directory is performed via the shared bus, but the update is performed by providing a dedicated communication line. It goes without saying that it can be realized by the method. Further, although the present embodiment has been described assuming that the compression directory for cache coherence and the bit compression directory exist inside the processor, it goes without saying that they may exist outside the processor.

(2) The cache coherence control operation shown in the first embodiment is only an example, and other control methods may exist. For example, in the example shown here, in the case of a write hit, if the data exists in the cache of the other processor, in that case, it is assumed that DB = 0 in the cache of the other processor. DB
There may be controls that allow = 1. In order to perform the cache coherence control by the control method different from the example shown here, the cache states (VB and DB values) of other processors can be known from any processor, and At that time, it suffices if the cache can be written back to the main memory or purged to another processor, and as described above, the condition is satisfied in the first embodiment. The cache coherence control other than the example shown in the example 1 is also applicable to the example 1.

(3) In the first embodiment, for convenience of explanation, the size of the main memory is set to 4 GB and the address is fixedly divided in units of 1 MB, but it goes without saying that other values may be used. The address division unit can be changed according to the address. For example, the address division unit is 4 KB up to the upper 16 MB of the address,
It is also possible to adopt a configuration in which the division unit is 1 MB unit for lower addresses.

<Embodiment 2> This embodiment aims at efficiently performing cache coherence control with a compressed directory having a smaller number of entries. The present embodiment is different from the first embodiment in the configuration of the compression directory device 12 and the configurations of the bit compression directories 54 to 56. Also,
As the cache coherence operation, the update operation of the compression directory device 12 and the bit compression directory device 13 of another processor due to the change of the cache memory 30 is different, but the update operation of the cache memory 30 of another processor by the bit compression directory device 13 is different. Is the same as in the first embodiment.

FIG. 11 is a diagram showing the structure of the compression directory device 12, wherein in FIG. 11, 46 is a compression directory and 47 is a compression directory registration / update circuit. Each entry of the compression directory 46 includes an address part 25, a valid count number 21, and a strike account number 22. In the compressed directory 40 shown in the first embodiment, the address management unit is fixed, whereas the compressed directory 46.
With the address section 25, the address area for counting the effective count number 21 and the storage account number 22 can be freely changed for each entry.

FIG. 12 is a diagram showing the structure of the bit compression directories 54 to 56. Bit compression directory 5
Similar to the compressed directory 47, each of the entries 4 to 56 is newly provided with an address part 26. The other valid bit 23 and the other store bit 24 have the same functions and configurations as the bit compression directories 54 to 56 (FIG. 6) in the first embodiment. The size of the address area covered by one entry of the compression directory 46 and the bit compression directories 54 to 56 is fixed.
Hereinafter, for the sake of explanation, it is assumed that the size is 1 MB.

Next, the operation of the present system configured as described above will be described with reference to FIGS. 1, 2, 4, 11, and 12. Hereinafter, a difference between the first embodiment and this embodiment, that is, how the contents of the compression directory 46 and the bit compression directories 54 to 56 are updated will be described. The description shows a specific example of the process in which the compression directory 46 is updated due to the access of the instruction processor (IP) 3 in the processor 2a. Further, regarding the update of the bit compression directories 54 to 56 that occur following the update of the compression directory 46, the process of updating the bit compression directory 54 of the processor 2b after updating the compression directory 46 in the processor 2a will be described in detail. As an example:

In the initial state, the cache memory 3
The valid bit and the store bit of all the entries of 0 are reset, the values of the valid count number and the storage account number of all the entries of the compression directory 46 are 0, and all the entries of the bit compression directories 54 to 56 are Other valid bits and other store bit values are 0. The address part 25 of the compression directory 46 and the address part 26 of the bit compression directories 54 to 56 may have arbitrary values. Values in the initial state of the other parts are the same as those in the conventional processor.

When the entry of the cache memory 30 is changed due to the access of the instruction processor (IP) 3, specifically, the valid bit 16 in the entry,
When the value of the store bit 17 changes, the change is transmitted to the compression directory registration / update circuit 47 via the signal lines L24 and L25. The address of the changed entry in the cache memory 30 is transmitted to the compression directory 46 via the signal line L27. When the address indicated by the address section 25 in the entry of the compressed directory 46 includes the address indicated by the signal line L27, the values of the valid count number 21 and the strike account number 22 of the entry are updated as in the first embodiment. Subsequently, the other valid bit 23 and the other store bit 24 of the bit compression directory 54 of the processor 2b are updated.

Next, when the address indicated by the signal line L27 does not exist in the address part 25 of any entry in the compression directory 46, the compression directory 46 is updated and the bit compression directory 54 of the processor 2b is updated. Will be described. The compression directory registration / updating circuit 47 searches the entry of the compression directory 46 for an entry having a value of the valid count number 21 of 0. If such an entry exists, the address indicated by the signal line L27 is written in the address section 25 of that entry. Address part 25
When the compression directory 46 is updated after rewriting, the address indicated by the signal line L27 is changed to the compression directory 4
It is performed in the same manner as in the case where it exists in the address part 25 of any entry in 6. At this time, the value of the effective count number 21 changes from 0 to 1, so that the bit compression directory 54 of the processor 2b is also updated subsequently.

First, the compressed directory registration / update circuit 4
7 sends the number of the entry in which the address is newly written in the compression directory 46 to the signal line L30.
The processor 2b transmits this entry number to the bit compression directory 54 of the processor 2b via the signal line L01 of the processor 2b, and the address transmitted via the signal lines L02 and L23 of the processor 2b to the corresponding entry. The value is written in the address part 26 of the bit compression directory 54 of the processor 2b, and the other valid bit and the other store bit are updated.

Next, when the address indicated by the signal line L27 does not exist in the address part 25 of any entry in the compression directory 46, and the effective count number is 0 in the entry of the compression directory 46. Update of the compression directory 46 when there is no such entry and update of the bit compression directory 54 of the processor 2b will be described.

The compressed directory registration / update circuit 47
An appropriate entry is selected from the entries of the compression directory 46, the value of the address section 25 indicated by the entry is read, and the contents of all the cache memories 30 existing in the address area indicated by the address section 25 are flushed or purged. , Sends an instruction to the cache memory registration / update circuit 31 via the signal line L22 to the cache memory 30. After the flushing or purging is completed, by the same method as in the case where there is an entry having an effective count number of 0 in the entry of the compression directory 46, for the selected entry,
The compression directory 46 is updated, and the bit compression directory 54 of the processor 2b is updated.

As a method of selecting an appropriate entry among the entries of the compression directory 46, a method of selecting an entry having the smallest effective count value, or an entry having 0 or the smallest account count value is selected. There is a method or a method of adopting the LRU method to update the most recently updated entry, but any method may be selected depending on the situation, and another method may be adopted. But of course

In this embodiment, the cache coherence control is performed by using the compression directory 46 provided with the address section 25. Therefore, for example, for a program in which the locality of the used address is large, an entry is made more than in the first embodiment. Can be used effectively. Therefore, although the size of the entry of the compression directory 46 is increased by the size of the address part 25, the number of entries can be reduced as compared with the first embodiment, and as a result, the capacity of the compression directory 46 can be further reduced.

In the present embodiment, the size of the address area covered by one entry of the compression directory 60 and the bit compression directories 54 to 56 is fixed regardless of the address. For example, as in the first embodiment, A configuration is possible in which the address management unit is 4 KB for the upper 16 MB of addresses and the management unit is 1 MB for lower addresses.

<Third Embodiment> This embodiment is similar to the second embodiment.
The purpose is to efficiently perform cache coherence control with a compressed directory having a small number of entries. The present embodiment is different from the second embodiment in the configuration of the compression directory device 12 and the configurations of the bit compression directories 54 to 56. Here, only components and operations different from those of the second embodiment will be described.

FIG. 13 is a diagram showing the configuration of the compression directory device 12, in which 60 is a compression directory and 61 is a compression directory registration / update circuit. Each entry of the compressed directory 60 has an address part 26,
The address size instruction unit 27, the effective count number 21, and the strike account number 22. The total number of entries is equal to or more than the number of entries in the address translation buffer (TLB) of the instruction processor (IP) 3.

The compressed directory 46 shown in the second embodiment.
The address management unit is fixed, whereas the compressed directory 60 has an address size instruction section, so that the effective count number is 21 and the storage account number is 2.
The size of the address area to be counted by 2 can be freely changed for each entry.

FIG. 14 is a diagram showing the structure of the bit compression directories 54 to 56. Bit compression directory 5
Similar to the compressed directory 61, each of the entries 4 to 56 is newly provided with an address size instruction unit 28. The address part 26, the other valid bit 23, and the other store bit 24 have the same functions and configurations as the bit compression directories 54 to 56 (FIG. 12) in the second embodiment.

Next, the operation of the present system thus constructed will be described with reference to FIG. 1, FIG. 2, FIG. 4, FIG. 13 and FIG. In this embodiment, the compression directory 60 and the bit compression directory 5 are compared with the second embodiment.
The only difference is the method of updating the address part from 4 to 56. Only the different parts will be described below.

The compression directory 60 is updated as follows. When the content of the address translation buffer (TLB) in the instruction processor (IP) 3 is rewritten due to the access of the instruction processor (IP) 3,
That is, when the entry or the erasure of the entry of the address translation buffer (TLB) occurs, the physical address and the address size information of the translation address pair of the entry of the address translation buffer (TLB) that is created or erased are transmitted via the signal line L15. And sends it to the compressed directory registration / update circuit 61. Compressed directory registration / update circuit 61
Uses the received physical address and address size information to create or delete an entry in the address translation buffer (TLB) according to the compression directory 60.
Create or delete an entry for. As a result, the address part 25 and the address size instructing part 27 of the entry of the compressed directory 60 are
The control is performed so as to have the same information as the physical address and the address size of all the address translation pairs in B).

In this embodiment, it is assumed that the address translation buffer (TLB) can change the address size of the address to be translated for each address translation pair. If the address size is fixed, it is possible to use the compression directory 40 instead of the compression directory 60. Further, in that case, the structure of the bit compression directories 54 to 56 may be the one shown in FIG. 12 instead of the structure shown in FIG.

When the entry of the address translation buffer (TLB) disappears, the entry of the compressed directory 60 having the same address as the physical address of the disappeared entry is deleted, but the effective count number of the deleted entry is 21, the account When the value of the equation 22 is not 0, the compression directory registration / update circuit 61 sends an instruction to the cache memory registration / update circuit 31 via the signal line L22 to delete the address of the entry of the compression directory 60 to be deleted. The cache memory 30 is flushed or purged with all the data in the area range. However, there is a case where the specification is such that the data in the cache memory 30 is automatically flushed or purged when the entry of the address translation buffer (TLB) disappears, but in such a case, The compressed directory registration / update circuit 61 does not need to perform this operation.

The updating of the bit compression directories 54 to 56 associated with the updating of the compression directory 60 is the same as that of the second embodiment except for the update of the address size instruction section. The update of the address size instruction unit is performed by sending the information of the address size instruction unit together with the updated entry number on the signal line L30.

In this way, in this embodiment, the cache coherence control is performed by the address translation buffer (TLB).
Based on the address information of the. Generally, the address range included in the address translation buffer (TLB) is considered to cover almost all entries of the cache memory. Therefore, in the present embodiment, the cache coherence control can be efficiently performed by the compressed directory in which the number of entries is further reduced as compared with the second embodiment.

<Fourth Embodiment> This embodiment is a modification of the third embodiment. In the third embodiment, there is a possibility that the cache contents may need to be flushed or purged when updating the compressed directory 60, and system performance may be degraded. To aim. This embodiment differs from the third embodiment in the configuration of the compression directory device 12 and the configuration of the bit compression directory device 13. Here, only components and operations different from those of the third embodiment will be described.

FIG. 15 is a diagram showing the structure of the compression directory device 12, wherein 62 is an auxiliary compression directory, 63 is an auxiliary compression directory registration / update circuit, and 7
1 and 72 are adder / subtractors, and 73 to 74 are zero detectors. The auxiliary compression directory 62 has the same structure as the compression directory 40 (FIG. 5) of the first embodiment.

FIG. 16 shows the bit compression directory device 13
It is a figure which shows the structure of. In FIG. 16, 80 is a distribution circuit and 8
Reference numerals 1 to 83 are auxiliary bit compression directories. The auxiliary bit compression directories 81 to 83 have the same configuration as the bit compression directories 54 to 56 (FIG. 6) of the first embodiment.

Next, with respect to the operation of the present system configured as described above, FIG. 1, FIG. 2, FIG. 5, FIG. 6, FIG.
4, FIG. 15 and FIG.

The present embodiment is a combination of the first embodiment and the third embodiment. Compared with the third embodiment, the control method at the time of updating the compression directory 60 and the update control of the auxiliary compression directory 62 are improved. They are different in that they are newly added. Less than,
The different points will be described. As an example, the description shows a specific example of the process in which the compression directory 60 and the auxiliary compression directory 62 are updated due to the access of the instruction processor (IP) 3 in the processor 2a.
Further, the update of the bit compression directory and the auxiliary bit compression directory that occur subsequent to the update of the compression directory 60 and the auxiliary compression directory 62 will be described for the processor 2b.

The difference between the present embodiment and the third embodiment in updating the compression directory 60 is that the instruction processor (I
P) When the entry of the address translation buffer (TLB) 3 is deleted, and the entry of the compressed directory 60 having the same address information as that entry is deleted, but the effective count number of the deleted entry is 21, the account count This is the control when the value of 22 is not 0.
In the third embodiment, the cache memory 30 corresponding to the address area of the entry of the compressed directory 60 to be deleted
In the present embodiment, the compressed directory 6 to be deleted is flushed or purged.
The information of the entry of 0 is transferred from the compression directory 60 to the auxiliary compression directory 62.

That is, the compressed directory 6 to be deleted
The information of the entry of 0 is transferred from the compression directory registration / update circuit 61 to the auxiliary compression directory registration / update circuit 63 through the signal line L63, and the auxiliary compression directory 62 is transferred.
Auxiliary compression directory 6
Register to 2. Along with this, the bit compression directories 54 to 56 and the auxiliary bit compression directories 81 to 83 are updated. In this method, the third embodiment and
The method is the same as that described in the first embodiment.

Further, the auxiliary compression directory update circuit 63
Monitors the signal line L15, and checks the contents of the auxiliary compression directory 62 when an entry is generated in the address translation buffer (TLB) in the instruction processor (IP) 3. Then, when the values of the effective count number 21 and the storage account number 22 of the entry of the auxiliary compression directory 62 corresponding to the address area of the entry of the newly generated address translation buffer (TLB) are not 0, the auxiliary compression is performed. The contents of the entries in the directory 62 are transferred to the compressed directory 60. That is, the auxiliary compression directory 62 sends an instruction to the cache memory registration / update circuit 31 via the signal line L22 to search the cache memory 30 for the address range of the newly generated auxiliary compression directory 62 described above. Then, the information of the valid bit 16 and the store bit 17 of the corresponding address part 15 in the entry of the cache memory 30 is read and the compression directory 60 is updated.

The cache coherence control using the bit compression directories 54 to 56 and the auxiliary bit compression directories 81 to 83 is performed by a method combining the third embodiment and the first embodiment. That is, the bit compression directories 54 to 5 are accessed at the addresses that access the cache memory 30.
6 and the auxiliary bit compression directories 81 to 83, and with respect to both, the third embodiment and the first embodiment, respectively.
Performs cache coherence control as described above.

By the control as described above, the compression directory 60 and the auxiliary compression directory 62 are updated. According to the present embodiment, unlike the third embodiment, even if the entry of the address translation buffer (TLB) disappears, it is not necessary to flush or purge the data in the cache, and the performance degradation is suppressed as compared with the third embodiment. Cache coherence control becomes possible.

<Modified Example of Fourth Embodiment> In this embodiment, an example in which the third embodiment and the first embodiment are combined has been described. However, other combinations, for example, a combination of the second embodiment and the first embodiment, and the like. Alternatively, the third embodiment and the second embodiment may be combined.

<Embodiment 5> In Embodiments 1 to 4 and the modifications thereof, the copy of the bit compression directory for each processor element is redundantly arranged in a plurality of processor elements other than the processor element. However, instead of this, it is also possible to arrange the bit compression directory of each processor element inside or in the vicinity of the main memory.

In this case, since the bit compression directories relating to the same processor element do not overlap, the total capacity of the directories is reduced as compared with the above-described first embodiment.

Further, in the first to fourth embodiments and their modifications, the compression directory is arranged in each processor element. However, instead of this, it is also possible to arrange the compression directory inside or in the vicinity of the main memory.

<Embodiment 6> In this embodiment, as in the case of the embodiment 5, the bit compression directory of each processor element is arranged in the main memory or in the vicinity thereof. In this case, the bit-compressed directories for the same processor element do not overlap, so that the total capacity of the directories is reduced compared to the previously described embodiments.

However, the compressed directory is arranged in each processor element as in the first embodiment. As a result, since the compression directory of each processor element can be updated within that processor element, it can be performed faster than in the fifth embodiment.

[0141]

According to the present invention, cache coherence control in a multiprocessor system can be performed using a compressed directory having a small capacity.

In particular, in the case where directories are dispersedly arranged in each processor element so that each processor element can quickly check the presence or absence of data caching in another processor element,
The total capacity of the directory can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic circuit configuration diagram of a multiprocessor system according to a first embodiment of the present invention.

FIG. 2 is a cache device (11) used in the device of FIG.
FIG.

FIG. 3 is a schematic circuit configuration diagram of a compressed directory device (12) used in the device of FIG.

4 is a schematic circuit configuration diagram of a bit compression directory device (13) used in the device of FIG.

5 is a data structure diagram of a compression directory (40) used in the compression directory device of FIG.

6 is a data structure diagram of a bit compression directory (54) used in the bit compression directory device of FIG.

7 is a diagram illustrating a cache memory (3
0), the compression directory (40), and a diagram showing a specific example of data in the bit compression directory (54).

FIG. 8 is a diagram showing a cache memory (3
0), the compression directory (40), and a diagram showing another specific example of the data in the bit compression directory (54).

9 is a diagram showing a cache memory (3
0), the compression directory (40), and a diagram showing still another specific example of the data in the bit compression directory (54).

10 is a diagram showing the relationship between the bit compression directories (54, 55, 56) in each processor element of the apparatus of FIG. 1 and other processor elements.

FIG. 11 is a schematic circuit configuration diagram of a compressed directory device (12) used in a multiprocessor system according to a second embodiment of the present invention.

FIG. 12 is a bit compression directory device (13) used in a multiprocessor system according to a second embodiment of the present invention.
FIG.

FIG. 13 is a schematic circuit configuration diagram of a compressed directory device (12) used in a multiprocessor system according to a third embodiment of the present invention.

FIG. 14 is a bit compression directory device (13) used in a multiprocessor system according to a third embodiment of the present invention.
FIG.

FIG. 15 is a schematic circuit configuration diagram of a compressed directory device (12) used in a multiprocessor system according to a fourth embodiment of the present invention.

FIG. 16 is a bit compression directory device (13) used in a multiprocessor system according to a fourth embodiment of the present invention.
FIG.

[Explanation of symbols]

1 ... Shared bus, 40, 46, 60 ... Compressed directory,
54 to 56, 81 to 83 ... Bit compression directory.

Claims (17)

[Claims] 1. A processor having a plurality of processor elements and a storage device shared by the plurality of processor elements, each processor element having a processor and a plurality of blocks of a first size held in the storage device. In a multiprocessor system having a cache for holding at least one of a plurality of unit areas having a second size larger than the first size and configuring the storage device, at least one of the processor elements is cached. A first directory containing information for at least identifying a plurality of unit areas having one block and the other processor elements for the respective unit areas, and storing a first directory by a processor in any one of the first processor elements. Access to the storage device issued In response to the request for the database, based on the information in the first directory,
It is detected whether or not there is a second processor element that is caching any block in a specific unit area to which the data of the address specified by the access request belongs, and the second processor element is detected. At this time, a request to execute a specific process for maintaining the coherence between caches is selectively sent to the detected second processor element, and in the second processor element, the second processor element in the second processor element It is hit-checked whether a specific block having the address specified by the access request actually exists in the cache of the above, and as a result of the hit check, it is found that the specific block actually exists in the second cache. If this is the case, the requested specific processing is executed for the second cache. Yasshu control method. 2. As information corresponding to each processor element, a plurality of unit areas having at least one block cached in the corresponding processor element among the plurality of unit areas constituting the storage device, and respectively. Storing a second directory containing information identifying at least the number of cached blocks belonging to the unit area of the block, and as a result of executing the access request, the cached blocks are stored in the first processor element. When changed, the information in the second directory related to the specific processor element is updated depending on the change, and the information in the second directory before the update related to the specific processor element is updated. Based on the information and the information in the updated second directory. Determine whether or not at least one of the plurality of unit areas to which the cached block of the specific processor element belongs has been changed, and the plurality of unit areas of the plurality of unit areas having the cached block in the particular processor element are determined. The cache control method according to claim 1, further comprising a step of changing information related to the specific processor element in the first directory when at least one is changed. 3. The first directory is provided in each processor element, and comprises a plurality of directories each having information relating to caching by another processor element other than the processor element, and the second directory comprises: Each processor element is provided in a distributed manner and comprises a plurality of directories each having information about the processor element. Detection of the second processor element is performed by another processor provided in the first processor element. When the second processor element is detected in the first processor element based on the first directory regarding the element and the second processor element is detected, a request for executing a specific process for maintaining inter-cache coherence is issued. Process 1 If a block selectively sent from the sub-element to the second processor element and held in the cache in the first processor element is changed, depending on the change, The update of the first directory information is performed in the first processor element, and other than the first processor element when at least one of the plurality of unit areas held in the cache is changed. In updating the second directory for the first processor element in the processor element of, the first processor element notifies another processor element of the change of the unit area, and the other processor receiving the notification In the element,
3. The cache control method according to claim 2, wherein, of the second directory information held in the other processor element, information regarding the changed upper unit area is changed based on the notification. 4. The second processor element performs a hit check as to whether or not a specific block having an address designated by the access request actually exists in the second cache in the processor element, If it is found as a result of the hit check that the specific block actually exists in the second cache, the requested specific process is executed for the second cache, and the specific block of the second cache is specified. 4. The cache control method according to claim 3, wherein the execution of the requested specific processing is stopped when it is determined that the block of <1> does not exist. 5. The cache control method according to claim 3, wherein the ratio of the second size to the first size is at least twice the total number of the plurality of processor elements. 6. A processor having a plurality of processor elements and a storage device shared by the plurality of processor elements, each processor element having a processor and a plurality of blocks of a first size held in the storage device. In a multiprocessor system having a cache for holding a plurality of unit areas having a second size larger than the first size and configuring the storage device in each processor element, other than the processor element Storing a plurality of unit areas having at least one block cached in another processor element and first directory information for at least identifying the other processor element with respect to each unit area; Processor in one processor element In response to the access request to the storage device issued by the server, based on the first directory information provided in the first processor element, the specific data to which the address specified by the access request belongs is specified. Whether or not there is a second processor element that is caching any block in the unit area
Request for execution of a specific process for maintaining inter-cache coherence depending on the type of the access request and the result of the first hit check when the second processor element is detected. Is selectively transmitted from the first processor element to the detected second processor element, and a second hit check is performed to determine whether or not the block is cached in the second processor element. If the second hit check reveals that the second processor element is caching the block, the requested specific processing is included in the second processor element. A cache control method executed for the second cache. 7. The cache control method according to claim 6, wherein the ratio of the second size to the first size is at least twice the total number of the plurality of processor elements. 8. When a plurality of other processor elements are detected as the other second processor element as a result of the detection, execution of the processing is performed on each of the detected plurality of processor elements. 7. The cache control method according to claim 6, wherein a request is selectively made from said first processor element. 9. If the processing requested by the access request should be executed after execution of the specific processing,
9. The method according to claim 6, further comprising delaying execution of the processing requested by the access request by the first processor element until execution of the specific processing by the second processor element is completed. The described cache control method. 10. When the second hit check reveals that the second processor element is not caching the specific block, the second processor element changes from the first processor element to the first processor element. Is notified of the end or cancellation of the execution of the specific processing, and when the processing requested by the access request should be executed after the execution of the specific processing, 7. The cache control method according to claim 6, wherein the execution of the processing requested by the access request is delayed until the end or cancellation of execution of the specific processing is notified. 11. A plurality of processor elements each having at least one block held in the storage device and held in a cache in the processor element among a plurality of unit areas larger than the first size in each processor element. Of the unit area of each processor area and second directory information for identifying at least the number of blocks currently held in the cache, and the block held in the cache in any of the processor elements. Is changed, the second directory information in the processor element is updated depending on the change, and the second directory information is updated based on the first directory information before update and the first directory information after update. A plurality of blocks to which the cache held in the processor element belongs It is determined whether at least one of the unit areas has been changed, and when at least one of the plurality of unit areas held in the cache has been changed, the change of the unit area is notified to another processor element, and the notification is given. 7. The other processor element that has received the information further includes a step of changing information about the changed unit area in the first directory information held in the other processor element based on the notification. The described cache control method. 12. A processor having a plurality of processor elements and a storage device shared by the plurality of processor elements, each processor element having a processor and a plurality of blocks of a first size held in the storage device. In a multiprocessor system having a cache for holding, a plurality of unit areas held in the storage device and larger than the first size in each processor element,
A plurality of unit areas having at least one block held in a cache in a processor element other than the processor element and directory information for at least identifying the other processor element are stored, and any one of In response to an access request to the storage device issued by the processor in one processor element, for the block of the address specified by the access request, to the first cache included in the first processor element. Whether or not there is a second processor element that performs a first hit check and has a second cache that holds any block in the unit area to which the data of the above address belongs based on the above directory information Is detected and the second processor When an element is detected, a request to execute a specific process for maintaining inter-cache coherence, which depends on the type of the access request and the result of the first hit check, is sent to the detected second processor element. Selectively sending to the second processor element, the second processor element determines whether or not the block currently exists in the second cache.
If the second hit check reveals that the specific block actually exists in the other cache, the requested specific processing is performed on the second cache. If the specified block of the second cache does not exist as a result of the second hit check, the execution of the requested specific process is stopped, and the second processor element executes the first process. When the processing requested by the access request is to be executed after the execution of the specific processing, the second processor is notified of the end or cancellation of the execution of the specific processing. Until the element notifies the end or cancellation of the execution of the specific processing, the processing requested by the access request is performed by the first program. Cache control method to delay to run on processor element. 13. When a plurality of other processor elements are detected as the other second processor element, execution of the processing is selectively performed for each of the detected plurality of processor elements. 13. The cache control method according to claim 12, wherein a request is made, and in the first processor element, execution of the processing requested by the access request is delayed until the notification is made from each of the plurality of detected processor elements. . 14. A processor having a plurality of processor elements and a shared storage device shared by the plurality of processor elements, each processor element including a processor, a cache for the storage device, and a block held in the cache. Corresponding to each of a plurality of unit areas of the storage device having a size larger than the size of the first storage area, the first directory information indicating the number of blocks registered in the cache and belonging to the unit area is stored. A first table to be held, and whether the number of blocks held by the first directory information in the other processor element is 0 for the plurality of unit areas of the storage device, which is provided for each other processor element. A second table that holds the second directory information that indicates whether or not the block has been registered in the cache. Unit area in which the first directory information is updated according to a change in the number of registered blocks, and the corresponding number of registered blocks is changed from 0 to 1 or from 1 to 0 according to the update of the first directory information. In response to the notification of the unit area from the directory management circuit of the other processor element, the first directory management circuit detecting the detected unit area and notifying the other processor element of the detected unit area. A second directory management circuit for updating the number of registered blocks for the notified unit area in the second directory information provided corresponding to the above, and an access to the storage device issued from the processor. In response to the request, the second directory information provided corresponding to the other processor element is searched and its access is searched. Should the other processor element be requested to execute a specific process for coherence control based on the information contained in the second directory information corresponding to the unit area to which the address specified by the request belongs? A multiprocessor system comprising: a circuit for determining whether or not there is a circuit, and a circuit for controlling whether or not the specific processing is requested to another processor element according to the result of the determination by the determination circuit. 15. The first directory information includes the number of blocks registered in the cache for each of a plurality of unit areas obtained by dividing the entire area of the storage device by a size of a fixed length. The described multiprocessor system. 16. The first directory information is registered in the cache for each of a plurality of unit areas having blocks currently registered in the cache among the plurality of unit areas of the storage device. 15. The multiprocessor system according to claim 14, wherein the number of blocks registered in the cache is not included in the unit areas other than the some of the plurality of unit areas. 17. The first directory information is registered in a cache for each of a plurality of unit areas registered in a TLB in the processor among the plurality of unit areas in the storage device. 15. The multiprocessor system according to claim 14, wherein the multiprocessor system includes the number of blocks and does not include the number of blocks registered in the cache regarding unit areas other than the some of the plurality of unit areas.