JPH0823812B2 - Floating point data calculation method and calculation device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a central processing unit of a digital computer or the like, and in particular, four arithmetic operations of floating-point data, and further, ANSI / IEEE. The present invention relates to an arithmetic method and arithmetic unit for floating-point data that performs four arithmetic operations and rounding and normalizing operations of floating-point data that conform to the floating-point arithmetic standard P754 and the like.

[0002]

2. Description of the Related Art As a conventional floating-point data calculation method and calculation device, for example, Motorola Technical
Developments October 1988 "Floating Point Pipeline Partitioning"("FLOATI
NG POINT PIPELINE PARTITIONING ", MOTOROLA TECHNICAL
DEVELOPMENTS, Vol.8, pp.29, Oct. 1988).

FIG. 42 is a block diagram of an adder / subtractor of the conventional floating point data arithmetic unit. However, in order to clarify the difference from the present invention, the configuration of the original block diagram is changed and shown. Further, in the following, addition means subtraction with different signs or addition performed on mantissa data at the time of addition with the same sign, and subtraction means subtraction performed on mantissa data at addition with different signs or subtraction with the same sign. Show. It is assumed that addition or subtraction is determined prior to the operation depending on the sign of the input data and the type of instruction.

In FIG. 42, 151 is a register for storing the mantissa of the two floating-point data whose exponent is not smaller, and 152 is the mantissa of the two floating-point data whose exponent is smaller is the exponent of the smaller exponent. A register for storing the digit-matched one, and 153 is 1 of the output of the register 152 during subtraction
154 is a complementer that takes the complement of the register 151 and the complementer 153 as inputs, and carries out addition by setting the carry input (Cin) to the least significant bit to 0 at the time of addition, and carries the carry input (Cin) at 1 at the time of subtraction. And adder to perform subtraction, 155 is an adder
A register for storing the output of 154, 156 is a shift number generation circuit for generating a shift number for normalizing the output of the adder 154, and 157 is a shift number generation circuit 156 for the output of the register 155 for normalization. Barrel shifter that shifts by the number of bits indicated by, 158 is a register that stores the output of barrel shifter 157, and 159 determines whether or not to add a rounding addition value according to the value held in register 158 and the rounding mode and rounding precision. When rounding up is performed, the least significant bit (L) corresponding to the rounding precision is set to 1 and the other bits are set to 0 to generate a rounded addition value. When rounding down is performed, all bits are set to 0. A rounding value generation circuit that generates a rounding addition value, 160 is the output of the register 158 and the rounding value generation circuit 15
An adder that adds the outputs of 9; 161 is an R1 shifter that shifts the output of the adder 160 by 1 bit in the least significant bit direction (hereinafter referred to as right). 162 is a mantissa of the addition / subtraction result obtained from the output of the R1 shifter 161. Register.

The operation of the conventional floating point data adder / subtractor configured as described above will be described below.

First, the addend / subtract and the addend / subtract are ANSI / IEE
E Floating-point Arithmetic Standard Basic format according to P754 Single-precision format (hereinafter simply referred to as single-precision) A case where a sum or difference is rounded to single-precision will be described. (1) Before the start of processing step The mantissa whose exponent is the smaller one of the augend and the addend is added to the register 151, and the mantissa of the augend and the addend which has the smaller exponent is aligned with the exponent which is not the smaller. The result is stored in the register 152. The missing bit at the time of digit alignment is the bit one digit below the least significant bit (L), the rounding bit (R) with a weight of 2 ^-24 , and the bit below the bit with a weight of 2 ^-25. The sticky bit (S), which is the sum, is also stored in the register 152. (2) Step 1 Complement calculator 153 and adder 154 are registered in register 151 and register 152.
The two mantissas held in the are added and subtracted, and the result is stored in the register 155. At the time of addition, the complement unit 153 is set in the register 152.
Of the Cin of the adder 154
Is 0. At the time of subtraction, the complement unit 153 takes the 1's complement of the output of the register 152 and outputs it to the adder 154 to set Cin to 1. (3) Step 2 The shift number generation circuit 156 generates the shift number for normalizing the output of the adder 154, and the barrel shifter 157 registers the register 155.
Is shifted based on the output of the shift number generation circuit 156 to perform the normalization shift on the operation result of step 1. At that time, the barrel shifter 157 shifts up to the least significant bit (L), rounds bits (R) with a weight of 2 ^-24 , which is one digit below the least significant bit, and 2 ^-25.
A sticky bit (S), which is the logical sum of bits less than or equal to the weighted bit, is generated and stored in the register 158. (4) Step 3 The rounding value generation circuit 159 performs rounding according to the least significant bit (L), the rounding bit (R), the sticky bit (S), the rounding mode, the rounding precision, and the sign of the operation result held in the register 158. Generate an added value. The rounding addition value to be generated is 2 when the rounding addition signal is 1 according to the input / output relationship diagram shown in FIG.
^-Set the bit with a weight of ^-23 to 1 and the other bits to 0
When the rounded addition signal is 0, the rounded value obtained by setting all the bits to 0 is generated. RM, RP, RN, RZ are ANSI / IE
In the rounding mode specified in EE floating point arithmetic standard P754,
Negative rounding, positive rounding, and even rounding are shown in order. The adder 160 outputs the output of the register 158 and the rounding value generation circuit 15
The output from 9 is added, and the R1 shifter 161 adds the adder 160
Therefore, when a digit overflow occurs, the output of the adder 160 is shifted to the right by 1 bit, and in other cases, the output of the adder 160 is stored in the register 162 as it is, and the process is terminated.

Next, the case where the sum or difference is rounded to double precision in the basic format double precision format (hereinafter, simply referred to as double precision) according to ANSI / IEEE floating point arithmetic standard P754 will be described. (1) Before the start of processing step The mantissa whose exponent is the smaller one of the augend and the addend is added to the register 151, and the mantissa of the augend and the addend which has the smaller exponent is aligned with the exponent which is not the smaller. The result is stored in the register 152. The digit lost during digit alignment is the bit one digit below the least significant bit (L), the rounding bit (R) with a weight of 2 ^-53 , and the logic of the bits below the bit with a weight of 2 ^-54. The sticky bit (S), which is the sum, is also stored in the register 152. (2) Step 1 Complement calculator 153 and adder 154 are registered in register 151 and register 152.
The two mantissas held in the are added and subtracted, and the result is stored in the register 155. At the time of addition, the complement unit 153 is set in the register 152.
Of the Cin of the adder 154
Is 0. At the time of subtraction, the complement unit 153 takes the 1's complement of the output of the register 152 and outputs it to the adder 154 to set Cin to 1. (3) Step 2 The shift number generation circuit 156 generates the shift number for normalizing the output of the adder 154, and the barrel shifter 157 registers the register 155.
Is shifted based on the output of the shift number generation circuit 156 to perform the normalization shift on the operation result of step 1. At that time, the barrel shifter 157 shifts the result up to the least significant bit (L), rounds down the bit one digit below the least significant bit (R) and has a weight of 2 ^-53 , and 2 ^-54.
A sticky bit (S), which is the logical sum of bits less than or equal to the weighted bit, is generated and stored in the register 158. (4) Step 3 The rounding value generation circuit 159 performs rounding according to the least significant bit (L), the rounding bit (R), the sticky bit (S), the rounding mode, the rounding precision, and the sign of the operation result held in the register 158. Generate an added value. The rounding addition value to be generated is 2 when the rounding addition signal is 1 according to the input / output relationship diagram shown in FIG.
^Set the bit with the weight of ^-52 to 1 and the other bits to 0
When the rounded addition signal is 0, the rounded value obtained by setting all the bits to 0 is generated. RM, RP, RN, RZ are ANSI / IE
In the rounding mode specified in EE floating point arithmetic standard P754,
Negative rounding, positive rounding, and even rounding are shown in order. The adder 160 outputs the output of the register 158 and the rounding value generation circuit 15
The output from 9 is added, and the R1 shifter 161 adds the adder 160
If an overflow occurs at, the output of adder 160 is set to the right by 1.
In the other cases, the output of the adder 160 is stored in the register 162 as it is, and the processing is terminated.

FIG. 43 is a block diagram of a conventional floating point data multiplication device. However, in order to clarify the difference from the present invention, the configuration of the original block diagram is changed and shown. 251 is a multiplicand register that holds a multiplicand, and a 1-bit sign part 251s and an 11-bit exponent part 251e.
It consists of a 53-bit mantissa part 251f. 252 is a multiplier register for holding a multiplier, and is composed of a 1-bit sign part 252s, an 11-bit exponent part 252e, and a 53-bit mantissa part 252f. So-called "hidden bit" most significant bit of the multiplicand register mantissa portion 251f and the multiplier register mantissa portion 252f is with the weight of any 2 ⁰
In the case of a normalized number, the value is 1, and except for this bit, the multiplicand register 251 and the multiplier register 252 both match with double precision. 253 is a code generation circuit that reads the multiplicand and the sign of the multiplier from the multiplicand register encoder 251s and the multiplier register encoder 252s and generates the sign of the product. An 11-bit exponent adder that reads out the exponent and calculates the exponent of the product, 255 and 256 are 2 of the exponent adder 254, respectively.
11-bit selector for selecting one input, 257 is an 11-bit latch for holding the output of the exponent adder 254 and inputting it again to the exponent adder 254 through the selector 255, 258 is the process of calculating the exponent of the product 11-bit bias of
A bias correction value generation circuit for generating a correction value, 259 is a normalized correction value generation circuit for generating a constant for incrementing the exponent by 1 with the normalization of the 1-bit shift of the mantissa of the product,
260 reads the multiplicand register mantissa part 251f and outputs the higher 27
Bit or lower 27 bits (the most significant bit is 0 at this time) is selected and output, the multiplicand upper and lower selection circuit, 261 reads the multiplier register mantissa part 252f and outputs the upper 2
Multiplier upper / lower selection circuit that selects and outputs 7 bits or lower 27 bits (most significant bit is 0 at this time), 262 is output of 27-bit multiplicand upper / lower selection circuit 260 and 27-bit multiplier upper / lower Multipliers that multiply the output of the selection circuit 261 and output a sum (sum) and carry (carry) of 54 bits respectively, and 263 and 264 are 54-bits that hold the sum output and carry output of the multiplier 262, respectively. Latch, 265 is a 54-bit product generation adder that adds the sum output and carry output of the multiplier 262 held in the latch 263 and the latch 264, and 266 is a 54-bit latch that holds the output of the product generation adder 265. , 2
67 is a rounding addition value generation circuit that generates a constant when performing addition to round the mantissa of the product to single precision or double precision, and 268 selects the output of the rounding addition value generation circuit 267 and the value of the latch 266. A bit selector, 269 is a 54-bit mantissa adder that adds the output of the selector 268 and the value held in a latch 273 described later, and 270 is a overflow and mantissa addition from the most significant bit of the product generation adder 265. An OR gate for calculating the logical sum of overflow from the most significant bit of the device 269, 271 is a 54-bit shifter that shifts the output of the mantissa adder 269 by 0 bit, 1 bit or 26 bits toward the least significant bit, 272 Is the lower 30 bits of the mantissa adder 269 output and the shifter
A sticky bit generation circuit that inputs a shift overflow from the 26 least significant bits in 271 and generates a sticky bit according to whether the rounding precision is single precision or double precision,
273 is a 54-bit latch that holds the output of shifter 271, 27
4 is a product register that holds the product, and is a 1-bit sign part 274s.
And 11-bit exponent part 274e and 53-bit mantissa part 274f. When normalized number with a so-called "hidden bit", also the most significant bit of the product register mantissa portion 274f having a 2 ⁰ weight is 1, product register 274 except for this bit meets the precision. FIG. 44 is an operation explanatory diagram showing constants generated by the rounded addition value generation circuit 267 shown in FIG. 43.
A rounded addition value D in which only the first bit is 1 and the others are 0 and a rounded addition value E in which only the second bit is 1 and the other bits are 0 are generated from the least significant bit.

The operation of the conventional floating-point data multiplication device configured as described above will be described below.

First, the case where the multiplicand and the multiplier are single precision and the product is rounded with single precision will be described with reference to the operation flow chart of single precision multiplication shown in FIG. The figure shows the exponent adder 254 and multiplier 2
62 shows the contents of the operation of each processing step of the product generation adder 265, the mantissa adder 269, and the shifter 271. (1) Before the start of processing step The single precision multiplicand and the multiplicand are expanded to double precision and stored in the multiplicand register 251 and the multiplier register 252, respectively. At this time, the multiplicand register exponent part 251e and the multiplier register exponent part 25
Both 2e are converted into a double-precision bias expression (true exponent value = exponent part value-1023 ₍₁₀₎ ), and the multiplicand register mantissa part 25
Zeros are filled in 1f and the lower 29 bits of the mantissa part 252f of the multiplier register. Clear the latch 273 to 0. Where ₍₁₀₎
Indicates that the number is in decimal notation. (2) Step 1 The selectors 255 and 256 input the exponents of the multiplicand and the multiplier from the multiplicand register exponent part 251e and the multiplier register exponent part 252e to the exponent adder 254, add them, and store the addition result in the latch 257. The multiplicand upper / lower selection circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa part 251f (including all effective bits of the mantissa part of the multiplicand), and the multiplier upper / lower selection circuit 261 outputs the multiplier register mantissa part 2
The upper 27 bits of 52f are read out and output (this includes all the significant bits of the mantissa part of the multiplier). Multiplier 262
Performs multiplication based on inputs from the multiplicand upper / lower selection circuit 260 and the multiplier upper / lower selection circuit 261, and stores the sum output and the carry output in the latch 263 and the latch 264, respectively. At the same time, in the code generation circuit 253, the multiplicand register code unit 251s and the multiplier register code unit 252s read the multiplicand and multiplier codes, take the exclusive OR of both, generate the product code, and store it in the product register code unit 724s. . (3) Step 2 Since the value held by the latch 257 is the sum of the exponents expressing the multiplicand and the bias, the bias is doubly applied. Therefore, from the bias correction value generation circuit 258-
1023 (actually represented by 2's complement) is output, and the values of the latch 257 and the output of the bias correction value generation circuit 258 are added by the selector 255 and the selector 256 in the exponent adder 254 and stored in the latch 257 again. To do. Product generation adder 265
Stores the addition result in the latch 266 by adding the sum output and the carry output of the multiplier 262 held in the latch 263 and the latch 264. (4) Step 3 The mantissa adder 269 adds the value held in the latch 266 by the selector 268 and the value 0 in the latch 273. Step 2
When there is an overflow from the product generator adder 265 at
That is, when the product of the mantissas is 2 or more, the shifter 271 shifts the output from the mantissa adder 269 in the direction of the least significant bit by 1 bit (at this time, the most significant bit is filled with 1). The result is stored in the latch 273, the exponent adder 254 adds the value of the latch 257 and the constant 1 output from the normalized correction value generation circuit 259 by the selectors 255 and 256, and stores the result again in the latch 257. When there is no overflow from the product generation adder 265 in step 2, that is, when the product of the mantissa part is greater than or equal to 1 and less than 2, the shifter 271 does not need to perform normalization, and thus the output from the mantissa adder 269 is output. The value is stored in the latch 273 as it is without being shifted, and the exponent adder 254 outputs the value of the latch 257 as it is by the selector 255 and the selector 256 and stores it in the latch 257 again. The sticky bit generation circuit 272 takes the logical sum of the lower 30 bits of the output of the mantissa adder 269 and sets the sticky bit output to 1 if there is even one bit of the value 1 in 30 bits, and all 30 bits have the value 0. If so, the sticky bit output is set to 0. (5) Step 4 The rounding addition value generation circuit 267 is in the rounding mode, the value of the 25th bit from the most significant bit, which is the rounding bit of the value held in the latch 273, and the sign of the product output by the code generation circuit 253. (Required when the rounding mode is the positive direction rounding mode and the negative direction rounding mode) and the sticky bit generation circuit 272.
Determines whether or not the rounding addition is necessary based on the value of the sticky bit output by the above, and outputs the rounding addition value D shown in FIG. 44 when the rounding addition is required, and outputs 0 when the rounding addition is not required. The mantissa adder 269 adds the rounding addition value output from the rounding addition value generation circuit 267 and the value held in the latch 273 by the selector 268. At this time, if a digit overflow occurs in the mantissa adder 269, that is, when the mantissa value becomes 2 or more due to rounding up, the shifter 271 re-normalizes the output from the mantissa adder 269 by 1 bit. The value is shifted in the lower bit direction (at this time, the most significant bit is filled with 1), and the selector 255 and the selector 256 cause the exponent adder 254 to add the value of the latch 257 and the constant 1 output from the normalized correction value generation circuit 259. . When no overflow occurs in the mantissa adder 269, that is, when the mantissa value is 1 or more and less than 2, the shifter 271 does not need to perform normalization, and therefore the output from the mantissa adder 269 is output as it is without shifting. The selector 255 and selector 256
4 also outputs the value of latch 257 as it is. In either case, the output of the exponent adder 254 is stored in the product register exponent part 274e, the lower 29 bits of 53 bits excluding the least significant bit of the output of the shifter 271 are masked to 0, and the product register mantissa part 274f.
Then, the process ends.

Next, the case where the multiplicand and the multiplier are double precision and the product is rounded with double precision will be described with reference to the operation flow chart of double precision multiplication shown in FIG. Also in the figure, the exponent adder 254, the multiplier 262,
The operation contents of the product generation adder 265, the mantissa adder 269, and the shifter 271 are shown for each processing step. (1) Before the start of processing step Double precision multiplicand and multiplicand
Stored in 1 and multiplier register 252. At this time, both the multiplicand register exponent part 251e and the multiplier register exponent part 252e are double-precision bias expressions (true exponent value = exponent part value−1023 ₍₁₀₎ )
It has become. Clear the latch 273 to 0. (2) Step 1 The selectors 255 and 256 input the exponents of the multiplicand and the multiplier from the multiplicand register exponent part 251e and the multiplier register exponent part 252e to the exponent adder 254, add them, and store the addition result in the latch 257. The multiplicand upper / lower selection circuit 260 reads and outputs the upper 27 bits (the most significant bit is 0) of the multiplicand register mantissa part 251f, and the multiplier upper / lower selection circuit 261 outputs the lower 27 bits (most significant bit is the highest bit of the multiplier register mantissa part 252f). 0) is read and output. The multiplier 262 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 260 and the multiplier upper / lower selection circuit 261, and stores the sum output and the carry output in the latch 263 and the latch 264, respectively. At the same time, in the code generation circuit 253, the multiplicand register code unit 251s and the multiplier register code unit 252s read the multiplicand and multiplier codes, take the exclusive OR of both, generate the product code, and store it in the product register code unit 724s. . (3) Step 2 Since the value held by the latch 257 is the sum of the exponents expressing the multiplicand and the bias, the bias is doubly applied. Therefore, from the bias correction value generation circuit 258-
1023 (actually represented by 2's complement) is output, and the values of the latch 257 and the output of the bias correction value generation circuit 258 are added by the selector 255 and the selector 256 in the exponent adder 254 and stored in the latch 257 again. To do. Product generation adder 265
Stores the addition result in the latch 266 by adding the sum output and the carry output of the multiplier 262 held in the latch 263 and the latch 264. The value stored in latch 266 is the lowest partial product. At the same time, the multiplicand upper / lower selection circuit 260 determines the lower 27 bits (the most significant bit is 0) of the multiplicand register mantissa 251f.
Is output and the multiplier upper / lower selection circuit 261 reads and outputs the upper 27 bits of the multiplier register mantissa part 252f. The multiplier 262 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 260 and the multiplier upper / lower selection circuit 261, and outputs the sum output and the carry output to the latch 263 and the latch 2 respectively.
Store in 64. (4) Step 3 The mantissa adder 269 adds the value held in the latch 266 by the selector 268 and the value 0 in the latch 273. The shifter 271 logically ORs the 54 bits of the addition result in the mantissa adder 269 with the overflow from the product generation adder 265 in step 2 and the overflow from the mantissa adder 269 in step 3 with the OR gate 270. 1 bit taken is added to the most significant bit side 55
The bit data is shifted by 26 bits in the direction of the least significant bit and the result is stored in the latch 273. The product generation adder 265 adds the sum output and the carry output of the multiplier 262 held in the latch 263 and the latch 264, and stores the addition result in the latch 266.
The value stored in latch 266 is the first medium partial product. At the same time, the multiplicand upper / lower selection circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa part 251f, and the multiplier upper / lower selection circuit 261 outputs the lower 2 bits of the multiplier register mantissa part 252f.
Reads and outputs 7 bits (most significant bit is 0). The multiplier 262 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 260 and the multiplier upper / lower selection circuit 261, and stores the sum output and the carry output in the latch 263 and the latch 264, respectively. (5) Step 4 The mantissa adder 269 adds the value held in the latch 266 by the selector 268 and the output of the shifter 271 held in the latch 273. The shifter 271 outputs the 54 bits of the addition result in the mantissa adder 269 as it is without shifting and latches it.
Store in 3. The product generation adder 265 is a latch 263 and a latch 264.
The sum output of the multiplier 262 and the carry output held by are added, and the addition result is stored in the latch 266. The value stored in latch 266 is the second medium partial product. At the same time, the multiplicand upper / lower selection circuit 260 determines the upper 2 of the multiplicand register mantissa 251f.
The 7 bits are read and output, and the multiplier upper / lower selection circuit 261 reads and outputs the upper 27 bits of the multiplier register mantissa part 252f. The multiplier 262 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 260 and the multiplier upper / lower selection circuit 261, and stores the sum output and the carry output in the latch 263 and the latch 264, respectively. (6) Step 5 The mantissa adder 269 adds the value held in the latch 266 by the selector 268 and the output of the shifter 271 held in the latch 273. The shifter 271 ORs the 54 bits of the addition result in the mantissa adder 269 with the overflow from the product generation adder 265 in step 4 and the overflow from the mantissa adder 269 in step 5 with the OR gate 270. The 55-bit data obtained by adding the taken 1 bit to the most significant bit side is shifted by 26 bits in the least significant bit direction, and the result is stored in the latch 273. The product generation adder 265 adds the sum output and carry output of the multiplier 262 held in the latch 263 and the latch 264 to add the carry output to the latch 2
The addition result is stored in 66. The value stored in latch 266 is the highest partial product. (7) Step 6 The mantissa adder 269 adds the value held in the latch 266 by the selector 268 and the output of the shifter 271 held in the latch 273. When the value obtained by logically summing the overflow from the product generation adder 265 in step 5 and the overflow from the mantissa adder 269 in step 6 by the OR gate 270 is 1, that is, the product of the mantissa part. Is greater than or equal to 2, the shifter 271 shifts the output from the mantissa adder 269 toward the least significant bit by 1 bit (fills the most significant bit with 1) for normalization and outputs the result to the latch 273. After storing, the exponent adder 254 adds the value of the latch 257 and the constant 1 output from the normalized correction value generation circuit 259 by the selector 255 and the selector 256, and stores again in the latch 257. When the value obtained by ORing with the OR gate 270 is 0, that is, the product of the mantissa is 1 or more 2
When it is less than, since the shifter 271 does not need to perform normalization, the output from the mantissa adder 269 is directly stored in the latch 273 without being shifted, and the exponent adder 254 causes the selector 255 and the selector 256 to store the output in the latch 257. The value is output as it is and stored in the latch 257 again. Sticky bit generation circuit 2
72 is shift overflow from the least significant bit of 26 bits in shifter 271 in step 3 and shifter 27 in step 5
A value of 1 in 52 bits is calculated by ORing 52 bits including the shift overflow from the 26 least significant bits in 1
If there is even one bit of the sticky bit output, the sticky bit output is set to 1, and if all the 52 bits have the value 0, the sticky bit output is set to 0. (8) Step 7 The rounding addition value generation circuit 267 is in the rounding mode, the value of the least significant bit which is the rounding bit of the value held in the latch 273, the sign of the product output by the code generation circuit 253 (the rounding mode is the forward direction). (Necessary in the rounding mode and the negative direction rounding mode) and the value of the sticky bit output from the sticky bit generation circuit 272 determines whether the rounding addition is necessary, and when the rounding addition is necessary, the rounding addition value E shown in FIG. Is output, and 0 is output when rounding addition is not necessary. The mantissa adder 269 adds the rounding addition value output from the rounding addition value generation circuit 267 and the value held in the latch 273 by the selector 268.
At this time, when a digit overflow occurs in the mantissa adder 269, that is, when the mantissa value becomes 2 or more due to rounding up, the shifter 271 again uses the mantissa adder 2 for normalization.
The output from 69 is shifted by 1 bit toward the least significant bit (at this time, the most significant bit is filled with 1), and the selector 255
The selector 256 causes the exponent adder 254 to add the value of the latch 257 and the constant 1 output from the normalized correction value generation circuit 259. When the mantissa adder 269 does not overflow, that is, when the mantissa value is 1 or more and less than 2, the shifter 271 does not need to perform normalization, and therefore the output from the mantissa adder 269 is output as it is without shifting. Then, the exponent adder 254 also outputs the value of the latch 257 as it is by the selector 255 and the selector 256. In either case, the output of the exponent adder 254 is stored in the product register exponent 274e, and 53 bits excluding the least significant bit of the output of the shifter 271 are used as the product register mantissa 274f.
And the process ends.

Further, in the conventional floating point data division method and division apparatus, in order to obtain the exponent part of the quotient, the exponent part of the multiplicand is first subtracted from the exponent part of the divisor. Since the subtracted values are both the difference between the exponents expressed in the bias, the bias is canceled. Therefore, the bias value is added to this subtraction value to generate the exponent part of the quotient that is correctly expressed in the bias.

[0013]

However, in the conventional floating point data adder / subtractor, the position of the least significant bit (L) to which the rounded addition value is added is not fixed with respect to the input / output of the adder 154. Since it is first determined after the normalization shift in the barrel shifter 157, the processing flow is always addition, subtraction, normalization, and rounding. Therefore, it is necessary to perform addition and subtraction of the two mantissas and addition of the rounded addition value independently of each other, which requires at least four processing steps including digit alignment as shown in FIG. 23 (a). Since the addition and subtraction of is performed by the adder 154 and the latter addition is performed by the adder 160,
There is a problem that two adders are required and the hardware is increased.

In view of the above point, the present invention makes it possible to simultaneously add and subtract mantissas and add rounded addition values in the same adder, and as a result, floating-point data rounded in a specified rounding mode and rounding precision. It is an object of the present invention to provide an addition / subtraction method and an addition / subtraction device for floating-point data, which requires a small number of processing steps to obtain the mantissa part of the sum and difference of And

Further, in the conventional floating point data multiplication device, since addition of sum and carry from multiplier 262, addition for accumulating partial products, and addition of rounded addition value are performed independently of each other, In the case of single-precision multiplication, 4 steps are required, and in the case of double-precision multiplication, as many as 7 steps are required, and the former one addition is performed by the product generation adder 265 and the latter two addition is performed by the mantissa adder 269. Therefore, you need two adders,
It has a problem that the hardware increases.

[0016] The present invention is seen paragon of the above points, to perform simultaneously the addition of the sum and carry from adder and a multiplier for accumulating sum or partial product sum value rounding the mantissa of the same adder As a result, the number of processing steps required to obtain the product of rounding corresponding to each rounding mode with the specified rounding precision is small, and the hardware is less than the conventional floating-point data multiplication device. An object of the present invention is to provide a multiplication method and a multiplication device for floating point data.

Further, in the conventional floating point data division device, the exponent part of the dividend and the exponent part of the divisor are first simply subtracted, so that the bias of the subtracted value is offset, and a step of correcting the bias is required later. Therefore, there is a problem that the hardware for bias correction increases.

In view of such a point, the present invention provides a method and a device for dividing floating-point data, which does not require the step of correcting the bias of the exponent and has less hardware than the conventional device for dividing floating-point data. The purpose is to do.

[0019]

According to a first aspect of the present invention, when the operation of floating-point data is addition of the same sign or subtraction of different signs, the true mantissa addition is performed, the digits are aligned with the same exponent. The addition of the second mantissa and the addition result and a rounding addition value uniquely determined by the rounding precision, the rounding mode, and the sign of the operation result are performed at the same time, and the floating-point data operation is performed by subtraction with the same sign or with different sign. In the case of true mantissa subtraction, which is addition, subtraction of the first and second mantissas with which the same exponent is aligned, and the rounding addition value uniquely determined by the subtraction result, the rounding precision, the rounding mode, and the sign of the operation result. And the second mantissa and the rounded addition value are added and subtracted, and when the operation result is a denormalized number, the operation result is shifted by 1 bit for normalization, and then the normalization is performed. Positive The normalized operation by inspecting a plurality of bits including the least significant bit determined by the type of operation and the rounding precision, which indicates whether it is true mantissa addition or true mantissa subtraction from the converted operation result Among the results, whether the values up to the least significant bit determined by the rounding precision match the true mantissa addition or the true mantissa subtraction of the first mantissa and the second mantissa rounded to a predetermined precision, or higher than the checked bit To the inspected bit and the inspected bit does not match, or the carry to the higher order than the inspected bit does not match to the higher order bit than the inspected bit. The processing is ended by correcting part or all of the bits inspected with respect to the normalized operation result, or the processing is ended, or the rounded addition value is added again to the normalized operation result. A subtraction process of floating-point data to perform either the processing ends.

[0020]

According to a second aspect of the present invention, the operation of floating-point data is either true mantissa addition, which is addition with the same sign or subtraction with different signs, or subtraction with the same sign, or true mantissa subtraction, which is addition with different signs. Rounding addition value generation means for generating a rounding addition value that is uniquely determined by the type of operation indicating whether or not, rounding precision, rounding mode, and sign of the operation result, and digit alignment for the same exponent during true mantissa addition. And the second mantissa and the addition result and the rounding addition value generated by the rounding addition value generation means are performed at the same time, and when the true mantissa is subtracted, digits are aligned to the same exponent. Mantissa addition / subtraction executing means for simultaneously performing the subtraction of the mantissa and the addition of the subtraction result and the rounding addition value generated by the rounding addition value generation means, and when the operation result by the mantissa addition / subtraction execution means is a denormalized number, The calculation result And normalizing means for normalizing and shifted,
A plurality of bits including the least significant bit determined by the rounding precision are inspected from the output of the normalizing means, and the least significant bit determined by the rounding precision of the output of the normalizing means is rounded to a predetermined precision. Whether the mantissa of 1 matches the true mantissa addition or subtraction of the second mantissa, whether the carry to the higher order than the inspected bit matches, and only the inspected bit does not match, the inspected bit Operation result inspection means for determining whether the carry to the higher order or the higher bits than the inspected bit do not match, and a part or all of the bits inspected by the operation result inspection means with respect to the output of the normalizing means. Is a floating-point data addition / subtraction device including rounding correction means for correcting

[0022]

[0023]

A third aspect of the invention is to multiply the mantissas of the multiplicand and the multiplier in floating-point format and sum the products (sum).
And carry (carry) separately, and after the multiplication, the sum and the carry, rounding precision and rounding mode and the rounded addition value that is uniquely determined by the sign of the multiplicand and the multiplier are added, After the operation, when the operation result is a non-normalized number, the operation result is shifted by 1 bit for normalization, and a plurality of least significant bits are determined from the normalized operation result after the normalization and determined by rounding precision. Of the bits of the normalized operation result up to the least significant bit determined by the rounding precision, and whether the product of the mantissa of the multiplicand and the mantissa of the multiplier rounded to a predetermined precision matches. Carry higher than the checked bit and only the checked bit does not match, or carry higher than the checked bit and higher bits than the checked bit do not match. Whether or not the processing is terminated based on the result of the determination, the processing is terminated by correcting some or all of the bits inspected for the normalized operation result, or the processing is terminated. This is a method of multiplying floating-point data, in which the rounded addition value is added again to the operation result and the processing is ended.

[0025]

According to a fourth aspect of the invention, the bit widths of the two inputs are both equal to or longer than the length of the mantissa part of the multiplicand and the multiplier in floating-point format, and are longer than the length of the mantissa part. Mantissa multiplication means that outputs the sum (sum) and carry (carry) of double bit width, and rounding addition that generates a rounding addition value that is uniquely determined by the rounding precision, the rounding mode, and the sign of two floating point data. The value generation means, the mantissa addition means for simultaneously performing the sum output and carry output of the mantissa multiplication means, and the three additions of the rounded addition values from the rounded addition value generation means, and the calculation result by the mantissa addition means In the case of a normalized number, a normalizing means for shifting and normalizing the operation result, and a plurality of bits including the least significant bit determined by the rounding precision from the output of the normalizing means are inspected. Of the output of the normalizing means, up to the least significant bit determined by the rounding precision is equal to the product of the mantissa of the multiplicand and the mantissa of the multiplier rounded to a predetermined precision, or a carry is carried out higher than the inspected bit. Are matched and only the inspected bits do not match, or the operation result inspecting means for determining whether the carry to the upper bits of the inspected bits or the upper bits of the inspected bits do not match, and the output of the normalizing means. On the other hand, the floating-point data multiplication device is provided with rounding correction means for correcting a part or all of the bits inspected by the operation result inspection means.

According to a fifth aspect of the present invention, a multiplicand holding means for holding a mantissa part of a multiplicand in a floating point format, a multiplier holding means for holding a mantissa part of a multiplier in a floating point format, and at least one of two inputs A mantissa multiplication means for outputting a sum (sum) and a carry (carry) of at least twice the bit width of the input, the bit width of which is shorter than the length of the mantissa part of the multiplicand and the multiplier, and When the bit width of the multiplicand input of the mantissa multiplication means is shorter than the length of the mantissa part of the multiplicand, a plurality of mantissas from the most significant bit to the least significant bit of the mantissa part of the multiplicand held in the multiplicand holding means are provided. A partial multiplicand selecting unit that divides into a partial mantissa part having a bit width of the multiplicand input of the multiplying unit and selects and outputs one for each processing step, and a bit of the multiplier input of the mantissa multiplying unit. When the width is shorter than the length of the mantissa part of the multiplier, from the most significant bit to the least significant bit of the mantissa part of the multiplier held in the multiplier holding means, the bit width of the multiplier input of the plurality of mantissa multiplying means is determined. A partial addition part that is divided into partial mantissas, one of which is selected and output for each processing step, and a rounding addition value that is uniquely determined by the rounding precision, the rounding mode, and the sign of the two floating-point data are generated. And a rounding addition value generating means for performing the first step of the processing by simultaneously performing the sum output and the carry output of the mantissa multiplication means and the addition of the three rounding addition values from the rounding addition value generating means at the same time. And a mantissa for generating a new partial product by simultaneously performing the sum output and carry output of the mantissa multiplication means and the addition of the three of the shifted partial products generated in the immediately preceding step. The arithmetic means and the first or intermediate step of the process are the least significant bit direction by the number of bits determined by the position of the partial mantissa part of the multiplier and the multiplicand multiplied by the partial product obtained from the mantissa adding means in the step. Shift to the final step, and when the operation result obtained from the mantissa adding means is a denormalized number, shift means for shifting and normalizing the operation result, and the shift means for the first or intermediate step of the process. Of the partial product holding means for holding the output as an input to the mantissa adding means in the next step, each bit of the shift overflow in the shift means in the first or intermediate step of the processing and the output of the shift means in the final step of the processing Multiple bits, including the least significant bit determined by the rounding precision of In the output of the shift means, up to the least significant bit determined by the rounding precision match the product of the mantissa of the multiplicand and the mantissa of the multiplier rounded to a predetermined precision, or a digit higher than the inspected bit The operation result inspecting means for deciding whether or not only the inspected bits are not coincident with each other and the carry up to the inspected bit is not coincident with the inspected bit, and the output of the shift means is provided. On the other hand, it is a floating point data multiplication device comprising rounding correction means for correcting a part or all of the bits inspected by the operation result inspection means.

According to a sixth aspect of the present invention, a calculation is performed to obtain a value smaller by 1 from the exponent part of the dividend in the floating-point format having the deviated exponent part minus the exponent part of the divisor in the same floating-point format. This is a method of dividing floating-point data in which the most significant bit of the operation result is inverted after performing the operation.

A seventh invention is an exponent subtraction means for obtaining a value smaller by 1 from a value obtained by subtracting the exponent part of a divisor in the same floating-point format from the exponent part of a dividend in a floating-point format having a deviated exponent part, A floating point data division device comprising a most significant bit correcting means for inverting the most significant bit of the output of the exponent subtracting means.

[0030]

According to the first aspect of the invention, the first and second steps are performed by the above-mentioned procedure.
Simply add and subtract the mantissa of and the addition of the rounded addition value to perform normalization, and either end the process as it is or correct the result and end the process, or simply add the rounded addition value. The processing can be terminated, requiring fewer processing steps to obtain the sum or difference .

According to the second aspect of the present invention, with the above configuration, the mantissa of two floating point data and the sum of the three of the rounded addition values from the rounded addition value generating means or the difference of the former two and the sum of the latter are added and subtracted by the mantissa. After the result obtained by the executing means is normalized by the normalizing means, if the output of the normalizing means matches the mantissa of the sum or difference rounded to a predetermined precision by the judgment of the calculation result checking means, it is processed as it is. If the carry to the higher order than the inspected bit matches and only the inspected bit does not match, the rounding correction means can correct part or all of the output of the normalization means and end the processing. If the carry to the upper side of the bit and the upper bit to the checked bit do not match, the rounding addition value generation means and the mantissa addition / subtraction executing means again round the rounding addition to the output of the normalizing means. It can be terminated only by process adding the value. Therefore, the number of processing steps required to obtain the sum or difference is small, and the addition and subtraction of two mantissas and the addition of rounding are performed by a single adder with respect to the mantissa part. Can be reduced.

[0032]

[0033]

According to the third aspect of the present invention, the sum of the products of the multiplicand and the mantissa part of the multiplier, the carry and the rounding addition value are added at the same time for normalization by the above-mentioned procedure, and the processing is terminated as it is or the result is returned. The processing can be ended by correcting and ending the processing, or by simply adding the rounding addition value, and the number of processing steps required to obtain the product can be reduced.

[0035]

According to the fourth aspect of the present invention, with the above-mentioned configuration, the sum output and carry output obtained by inputting the mantissa parts of the multiplicand and the multiplier in the floating point format into the mantissa multiplication means and the rounding from the rounded addition value generation means The sum of the three added values is calculated by the mantissa adding means, and the result is normalized by the normalizing means. If they match, the processing can be terminated as it is, and if the carry to the higher order than the inspected bit matches and only the inspected bit does not match, the rounding correction means corrects part or all of the output of the normalization means. If the carry to the upper bit of the inspected bit and the bit of the upper bit to the inspected bit do not match, the rounding addition value generating means and the provisional Can be terminated only by process adds the addition value rounding again by adding means. for that reason,
The number of processing steps required to obtain the product is small, and since the addition, carry addition, and rounding addition are performed by a single adder for the mantissa, the required hardware can be reduced. .

According to the fifth aspect of the present invention, the partial multiplicand selecting means and the partial multiplier selecting means select the combinations of the mantissa parts of the multiplicand and the multiplier from the lower order and input all the combinations to the mantissa multiplying means. , The sum output, the carry output, and the rounding addition value from the rounding addition value generation means or the sum of the values held in the partial product holding means are obtained by the mantissa addition means, and the result is shifted by the shift means. Then, after storing again in the partial product holding means or by normalizing the final operation result by the shift means, the output of the shift means matches the mantissa of the product rounded to a predetermined precision by the judgment of the operation result inspection means. If so, the processing can be terminated as it is, and if the carry to the higher order than the inspected bit matches and only the inspected bit does not match, the rounding correction means causes the shift means. If a part or all of the output can be corrected and the processing can be ended, and the carry to the higher order of the inspected bit and the higher order bit of the inspected bit do not match, the rounding addition value generation means and the output of the shift means The process can be ended only by adding the rounding addition value by the mantissa adding means. As a result, the number of processing steps required to obtain the product is small, and a single adder performs addition and carry addition and rounding addition or addition for accumulating partial products with respect to the mantissa part. Therefore, the required hardware can be reduced.

According to the sixth aspect of the present invention, the addition of the bias value is realized by obtaining the value smaller by 1 and inverting the most significant bit by the above-mentioned procedure, and the quotient in the floating point format is biased like the dividend and the divisor. Since the exponent part of the can be obtained in a single processing step, the step of correcting the bias of the exponent part is not required.

According to the seventh aspect of the present invention, with the above-mentioned configuration, the operation for obtaining a value smaller by 1 by the exponent subtraction means, the inversion of the most significant bit and the addition of the bias value performed by the most significant bit correction means are realized, and the dividend and the divisor are divided. Similarly, the exponent part of the biased floating-point quotient can be obtained in a single processing step, eliminating the step of correcting the exponent part bias and increasing the hardware for bias correction. Can also be avoided.

[0040]

1 is a block diagram of a floating point data adder / subtractor according to a first embodiment of the present invention. In FIG. 1, 101 is a register for storing the mantissa whose exponent is the smaller of the two floating point data, 102
Is a register for storing the digit of the mantissa of the smaller exponent of the two floating-point data and the exponent of the smaller exponent, and 103 is a rounding correction repetition control circuit 109 to be described later instructing insertion of a new processing step. Is a multiplexer for selecting the register 110 described later and the register 101 for other normal operations, and 104 is a constant 0 for other normal operations when the rounding correction repetition control circuit 109 described later instructs the insertion of a new processing step. Sometimes a multiplexer is selected by the register 102, and 105 is a multiplexer 104 when subtracting
Complement calculator for taking the one's complement of the output of 106 determines the position of the round addition according to the exponent difference of two floating point data, the type of operation and the rounding mode, and sets the bit for round addition to 1
A rounding value generation circuit for generating data in which other bits are set to 0. 107 sets the carry input (Cin) to 0 at the time of addition and sets the carry input (Cin) to 1 at the time of subtraction to output the output of the multiplexer 103 and the output of the complement unit 105. An adder that simultaneously executes temporary rounding and calculation by adding the output of the rounding value generation circuit 106, 108 is the output of the adder 107 when the bit of the output of the adder 107 having a weight of 2 ¹ is 1. Least significant bit direction (hereinafter,
1 bit to right) and adder 1 when both the bit with the weight of 2 ^{1 and} the bit with the weight of 2 ⁰ are 0
LR1 shifter that shifts the output of 07 by 1 bit in the most significant bit direction (hereinafter referred to as left) and outputs the output of the adder 107 as it is at other times. Is the rounding done by the adder 107 correct for 109? If it is possible to obtain a correct rounding result only by correcting the least significant bit or the least significant bit and the bit of one upper digit, the corrected value is stored in the register 10 described later and the processing ends. And a rounding correction repeat control circuit for instructing the insertion of a processing step when it is necessary to execute re-addition of rounding values to obtain a correct rounding result, 110 is a register for storing the output of the LR1 shifter 108, 111 Is a shift number generation circuit for generating a shift number for normalizing the value held in the register 110, 112 is a bit indicated by the shift number generation circuit 111 for the output of the register 110 for normalization A barrel shifter that shifts by the number, and 113 is a register that stores the output of the barrel shifter 112. 3, FIG. 4, FIG. 5, and FIG. 6 are control relation diagrams of the rounding correction repeating control circuit 109 shown in FIG. 1 when the rounding mode is the nearest even rounding mode. subtraction of two floating point data of the code (hereinafter, referred to as mantissa addition) when executed and rounding accuracy of single precision, as shown in FIG. 3, 2 ^1, 2 ^-22 of the output of the adder 107, 2 ^- Bits with weights of ²³ , 2 ^-24 and 2
^-A sticky bit S, which is the logical sum of bits less than or equal to the bit having a weight of ^-25 , and the necessity of bit correction of the output of the adder 107 and the necessity of re-addition of the rounded addition value are determined, and mantissa addition is executed. When the rounding precision is double precision, as shown in FIG. 4, the output of the adder 107 has bits with weights of 2 ¹ , 2 ⁻⁵¹ , 2 ⁻⁵² , 2 ⁻⁵³ and 2 ^−54. The necessity of bit correction of the output of the adder 107 and the necessity of re-addition of the rounded addition value are determined from the sticky bit S which is the logical sum of bits less than or equal to the bit, and the subtraction of two floating point data of the same sign Alternatively, when two floating point data of different signs are added (hereinafter referred to as mantissa subtraction) and the rounding precision is single precision, as shown in FIG. 5, the output of the adder 107 is 2 ⁰ , 2 ^-23 ,
Bits with weights of 2 ^-24 and 2 ^-25 Sticky bits S, which is the logical sum of bits with weights of 2 ^-26 or less, and the necessity of bit correction of the output of the adder 107 and the re-addition of the rounded addition value When the necessity of addition is determined, the mantissa subtraction is executed, and the rounding precision is double precision, as shown in FIG. 6, 2 ⁰ , 2 ^-52 , 2 ^-53 , 2 ^-54 of the outputs of the adder 107 are output. Whether the bit correction of the output of the adder 107 and the necessity of re-adding the rounded addition value are determined from the sticky bit S which is the logical sum of the bit having the weight of 2 and the bit having the weight of 2 ⁻⁵⁵ or less. decide. 7, FIG. 8, FIG. 9, and FIG. 10 are control relation diagrams of the rounding correction repeating control circuit 109 shown in FIG. 1 when the rounding mode is the positive direction rounding mode and the sign of the operation result is positive. subtraction of two floating point data of the addition or of opposite sign floating point data (hereinafter, referred to as mantissa addition) when executed and rounding accuracy of single precision, as shown in FIG. 7, the output of the adder 107 2 ^{1 ,} 2 ^-22 , 2 ^-23 , and bits with weights of 2 ^-24 and 2 ^-25
The sticky bit S, which is the logical sum of bits less than or equal to the bit having the weight of, determines whether the bit correction of the output of the adder 107 and the necessity of re-adding the rounded addition value are performed, and the mantissa addition is performed, and When the rounding precision is double precision, as shown in FIG.
From the output of the adder 107, a bit having a weight of 2 ¹ , 2 ⁻⁵¹ , 2 ⁻⁵² , 2 ⁻⁵³ and a sticky bit S which is a logical sum of bits equal to or less than a bit having a weight of 2 ⁻⁵⁴ are added to the adder 107. Of whether the bit correction of the output of the above and the necessity of re-adding the rounded addition value are determined, subtraction of two floating point data of the same sign or addition of two floating point data of different signs (hereinafter referred to as mantissa subtraction ) Is executed and the rounding precision is single precision, as shown in FIG. 9, the output of the adder 107 is 2 ⁰ , 2 ^-23 , 2 ^-24 , 2
Whether or not the bit correction of the output of the adder 107 and the re-addition of the rounded addition value are necessary based on the sticky bit S which is the logical sum of the bit having the weight of ^{-25 and} the bit having the weight of 2 ^-26 or less. And when mantissa subtraction is executed and the rounding precision is double precision, as shown in FIG. 10, the outputs of the adder 107 have weights of 2 ⁰ , 2 ⁻⁵² , 2 ⁻⁵³ , 2 ^−54. Bit and ^2-55
The necessity of bit correction of the output of the adder 107 and the necessity of re-addition of the rounded addition value are determined from the sticky bit S which is the logical sum of bits less than or equal to the bit having the weight. Figure 24, Figure 25
Is an input / output relationship diagram of the rounding value generation circuit 106 shown in FIG. 1, and determines the rounding addition value according to the rounding mode, the sign of the operation result, the type of operation, and whether or not the rounding is to be re-added. The rounding value generation circuit 106 is based on FIG. 24 when the rounding precision is single precision and on the basis of FIG. 24 when the rounding precision is double precision. To generate. The subtraction device floating point data of this embodiment constructed as described <br/> above, will be described first principle. here,
The case where the rounding precision is single precision will be taken as an example, but the case of double precision is also based on the same idea.

Letting f1 and f2 be the mantissa and the mantissa part of the addend and subtraction, and e1 and e2 (where e1≤e2) be the exponent part of the addend and subtraction and the addend and subtraction, respectively, the mantissa part A of the sum at the time of adding the mantissa is ,

[0042]

[Equation 1]

It is expressed as follows. Where the range of values of the normalized mantissa

[0044]

[Equation 2]

Considering

[0046]

(Equation 3)

Accordingly, the number of shifts required for normalization after addition of the mantissa is 1 bit to the right at the maximum. ₍₂₎ indicates that the numerical value is expressed in binary. The mantissa part A of the difference when the mantissa is subtracted is

[0048]

[Equation 4]

It is expressed as Here, depending on the value of e1-e2, (1) When e1-e2 = 0

[0050]

(Equation 5)

Therefore, the number of shifts required for normalization after the mantissa subtraction is 23 bits from 0 to the maximum left.

(2) When e1-e2 = 1

[0053]

(Equation 6)

Therefore, the number of shifts required for normalization after the mantissa subtraction is 24 bits from 0 to the maximum left.

(3) When e1−e2 = 2

[0056]

(Equation 7)

As a result, the number of shifts required for normalization after the mantissa subtraction is 1 bit leftward at the maximum.

(4) When e1−e2 = 3

[0059]

(Equation 8)

Therefore, the number of shifts required for normalization after the mantissa subtraction is at most 1 bit on the left.

Similarly, when e1−e2 ≧ 4, the number of shifts required for normalization after mantissa subtraction is 1 bit on the left at the maximum, so when e1−e2 ≧ 2, the number of shifts after mantissa subtraction is The maximum number of shifts required for normalization is 1 bit to the left.

From the above facts, at the time of mantissa addition or at the time of mantissa subtraction other than the exponent difference 0 or 1, it is not necessary to shift more than 2 bits after the mantissa operation, and the former weights 2 ^-22 before normalization. The bit that has or the weight of 2 ^-23 becomes the least significant bit (L) of the result, and in the latter, the bit that has the weight of 2 ^-23 or the bit that has the weight of 2 ^-24 is the least significant bit (L) of the result. )become. Therefore, when adding mantissa or exponent difference is 0,
For mantissa subtraction other than 1, rounding may be performed at the positions of these bits at the same time as addition and subtraction, and then 1-bit normalization shift may be performed to the right or left. It is necessary to shift by more than 2 bits after the operation only when mantissa subtraction with exponent difference of 0 or 1 is performed. When the exponent difference is 0, digit alignment shift before operation is not performed, so it is effective in the lower order than the least significant bit. Has no value and does not require rounding. When the exponent difference is 1, the digit shift number before calculation is 1 bit, so the least significant bit is 1.
Although having only valid values under digit (round bit R), a shift for bit 1, then normalized with the weight of 2 ⁰ requires only rounding unnecessary, the bit having the weight of 2 ⁰ If 0, the rounding bit is moved to the least significant bit or higher bits by the shift for normalization, and thus rounding is not required after normalization. Therefore, when mantissa subtraction with an exponent difference of 0 or 1, only at least one of shifting or rounding for normalization needs to be performed after the operation. FIG. 29 (a) shows the position of the least significant bit (L) at the time of adding a mantissa, and (b) the position of the least significant bit (L) at the time of subtracting a mantissa other than the exponent difference 0 or 1. Next , the principle of realizing even rounding recently is shown. To round to the nearest value, the bit to be rounded and added, that is, the least significant bit (L) of 1
Whether to add to the least significant bit is determined depending on whether the smaller bit (rounding bit R) is 1 or 0. Rounding bit is 0
, The data before rounding and the data after rounding are the same, and when the rounding bit is 1, 1 is added to the least significant bit. This rounding addition can be automatically realized by adding 1 to the rounding bit and using the carry from the rounding bit to perform addition to the least significant bit. In this method, since a bit smaller than the rounding bit is not determined, even in the case of an intermediate value in which the rounding bit is 1 and the smaller bits are 0, the rounding addition is performed to round to the larger one. However, the ANSI / IEEE floating-point arithmetic standard P754 stipulates rounding to the nearest even number, and as shown in the RN column in FIG.
, If the sticky bit indicating whether the portion smaller than the rounding bit is 0 is an intermediate value,
Rounding is performed so that the least significant bit is always an even number. More specifically, when the least significant bit is 1, rounded addition is performed, and when the least significant bit is 0, rounded addition is not performed.

Here, a noteworthy fact is the carry to the least significant bit when the rounding addition is performed on the rounding bit. When the rounding bit is 1, the rounding addition causes the rounding bit to become 0, and the carry generated by the rounding addition is added to the least significant bit. When the least significant bit is 1, as shown in Fig. 28 (a). Carry propagates to the upper bits. However, when the least significant bit is 0, the least significant bit is 1, and the carry does not propagate, as shown in FIG. 28 (b). Therefore, for an intermediate value in which the rounding bit is 1 and the sticky bit is 0, if the rounding bit and the sticky bit are both 0 after unconditional addition to the rounding bit, the least significant bit is corrected to 0. By doing so, even rounding can be accurately executed recently. That is, if the position of the rounding bit can be determined before the operation, the rounding and the operation can be executed simultaneously.

[0064] Therefore, when the mantissa addition is to bits if having a weight of 2 ^-24, when subtracting non exponent difference 0, 1 if 2 ^-25
After 1 is added to the bit with the weight of, the true rounding bit is determined by the bit with the weight of 2 ¹ and 2 ⁰ of the operation result, and the rounding result is corrected temporarily To realize. When adding a mantissa, one bit is obtained by ORing the bits with weights of 2 ^-22 , 2 ^-23, and 2 ^-24 of the result of tentative rounding addition, and each bit smaller than that. B. By the resulting bits having weights of 2 ^-23 , 2 ^-24, and 2 ^-25 , and 1 bit obtained by logically adding each bit smaller than that, b. When correct results are obtained b. Correct results can be obtained by correcting bits with weights of 2 ^-22 or 2 ^-23 c. ^Judge that the correct result cannot be obtained only by correcting the bit having the weight of 2 ^-22 or 2 ^-23 , and correct the bit in case of b, and add the same rounding again in case of c. To obtain the correct calculation result.

Next, the operation of the floating point data adding / subtracting device of the present embodiment having the above-described structure will be described below. The explanation is recently round even mode, positive direction rounding mode, negative direction rounding mode, zero direction rounding mode,
Rounding precision is divided into single precision and double precision. 1 Recent even rounding mode 1-1 When the sum or difference of the augend and the addend is rounded in single precision with single precision (1) Before the start of the processing step Is the exponent of the two floating point data, the sign and the instruction addition? Based on whether it is a subtraction, the type of operation of mantissa addition or mantissa subtraction and the sign of the operation result are determined as shown in the sign operation relation diagram of FIG. The mantissa whose exponent is the smaller of the augend and the addend is stored in register 101, and the mantissa of the augend that is smaller is stored in the register 102. To do. The digit with which the digit was dropped during digit alignment is the least significant bit.
Rounding bit with a weight of 2 ^-24 that is one digit below (L)
(R) and a sticky bit (S) which is a logical sum of bits having a weight of 2 ^-25 or less and stored in the register 102 together. (2) Step 1-When adding mantissa: The multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of ^2-24 is set to 1 and other bits are set to 0. The complementer 105 uses the output of the multiplexer 104 as it is as an input of the adder 107, and at this time, Cin is set to 0 to execute (register 1) + (register 2) + (rounded addition value). L
When the bit of the output of the adder 107 having the weight of 2 ¹ is 1, the R1 shifter 108 shifts to the right by 1 bit. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
^-One bit (S) is generated by taking the logical sum of the bits below the bit having a weight of ^-25 , and the output of adder 107 is 2 ¹ and 2 ^-22
When 2 ^-23 and the bit and the S bit having the weight of 2 ^-24, register 110 inverts the bits having 2 ^-23 weight of the output of LR1 shifter 108 when the correction signal shown in Figure 3 is 01
When the correction signal is 00, the output of the LR1 shifter 108 is directly stored in the register 110. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has performed is completed. Mantissa subtraction other than the exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of 2 ^-25 is set to 1 and other bits are set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) + (rounded addition value) is executed. L
R1 when the bit having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
Generate 1 bit (S) by ORing each bit less than or equal to the bit with ^-26 weight, and output 2 ⁰ and 2 ^-23 of the output of adder 107.
When the correction signal shown in FIG. 5 is 01, the bit having the weight of 2 ^-23 of the output of the LR1 shifter 108 is inverted by the bit having the weight of 2 ^-24 and the bit of 2 ^-25 and the S bit, and the register 110
When the correction signal is 00, the output of the LR1 shifter 108 is directly stored in the register 110. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has been performed ends. When mantissa subtraction with exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) is executed. LR1
When bits having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. In the rounding correction iterative control circuit 109, the outputs of the adder 107 are 2 ⁰ , 2 ^-23 and 2
^-When all 3 bits with a weight of ^-24 are 1, it indicates the insertion of a step for rounding. On the other hand, the shift number generation circuit 111 generates a shift number necessary for normalizing the output of the LR1 shifter 108, and when this shift number is 0, the insertion of a step for normalization is instructed. When neither the insertion of a rounding step nor the insertion of a normalization step occurs, the operation ends at this step. (3) Insertion step (only when insertion of a step is instructed) -When adding mantissa Select the output of the register 110 with the multiplexer 103, select the constant 0 with the multiplexer 104, and output the output of the multiplexer 103 and the multiplexer 104 as they are. Complementer 105
Output and 2 generated by the rounding value generation circuit 106 in step 1
^{When the} bit having a weight of ^-24 is set to 1 and the data having the other bits set to 0 are added by the adder 107, and the bit having a weight of 2 ¹ of the output of the adder 107 is 1 by the LR1 shifter 108, When the bit having the weight of 2 ¹ is 0, the value is stored in the register 110 as it is and the processing is completed. When the mantissa is subtracted except for the exponent difference 0 or 1, the output of the register 110 is selected by the multiplexer 103, the constant 0 is selected by the multiplexer 104, and the output of the multiplexer 103 and the complementer 105 that outputs the multiplexer 104 as they are.
Output and 2 generated by the rounding value generation circuit 106 in step 1
Add data with a bit with a weight of ^-25 to 1 and other bits to 0 with an adder 107, and with an LR1 shifter 108, when the bit with a weight of 2 ¹ of the adder 107 is 1, it is right. To 1
Bit shift is performed so that the bit having a weight of 2 ¹ becomes 0.
In the case of, the value as it is is stored in the register 110 and the process is terminated. -When mantissa subtraction with exponent difference 0 or 1 When the shift number generation circuit 111 instructs the insertion of a step for normalization, the barrel shifter 112 receives the register 110 as input, and only the shift number generated by the shift number generation circuit 111 is input. The process shifts to the left, stores it in the register 113, and ends the process.

On the other hand, when the rounding correction iterative control circuit 9 instructs to insert a step for rounding, the register 110
Select the output of the multiplexer 103 with multiplexer 1
A constant 0 is selected in 04, the output of the multiplexer 103, the output of the complementer 105 which is output from the multiplexer 104 as it is, and the bit having a weight of 2 ^-23 generated by the rounding value generation circuit 106 are set to 1 and the other bits are set to 0. and adder 107 and the data was, by performing 1-bit shift to the right when the bit is 1 with 2 ¹ of the weights of the output of the adder 107 in LR1 shifter 108, the bit having the weight of 2 ¹ When is 0, the same value is stored in the register 110 and the process is terminated.

1-2 When the sum or difference of the augend and subtraction is double-precision and the difference is double-precision (1) Before the start of the processing step The exponent and the sign of the two floating-point data and the instruction are addition or subtraction. Based on whether or not there is a mantissa addition or a mantissa subtraction, the type of operation and the sign of the operation result are determined as shown in the sign operation relation diagram of FIG. The mantissa whose exponent is the smaller of the augend and the addend is stored in register 101, and the mantissa of the augend that is smaller is stored in the register 102. To do. The digit with which the digit was dropped during digit alignment is the least significant bit.
Rounding bit that is one digit below (L) and has a weight of 2 ^-53
(R) and a sticky bit (S) which is a logical sum of bits having a weight of 2 ⁻⁵⁴ or less and stored in the register 102. (2) Step 1-When adding mantissa: The multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of 2 ⁻⁵³ is set to 1 and other bits are set to 0. The complementer 105 uses the output of the multiplexer 104 as it is as an input of the adder 107, and at this time, Cin is set to 0 to execute (register 1) + (register 2) + (rounded addition value). L
When the bit of the output of the adder 107 having the weight of 2 ¹ is 1, the R1 shifter 108 shifts to the right by 1 bit. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
^-One bit (S) is generated by ORing the bits below the bit having the weight of ^-54 , and the output of adder 107 is 2 ¹ and 2 ^-51
When the correction signal shown in FIG. 6 is 01, the bit having the weight of 2 ⁻⁵² of the output of the LR1 shifter 108 is inverted by the bit having the weight of 2 ⁻⁵² and 2 ⁻⁵³ and the S bit, and the register 110
When the correction signal is 00, the output of the LR1 shifter 108 is directly stored in the register 110. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has performed is completed. Mantissa subtraction other than the exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of 2 ⁻⁵⁴ is set to 1 and other bits are set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) + (rounded addition value) is executed. L
R1 when the bit having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
Generate a 1-bit (S) that is the logical sum of bits less than or equal to the bit having the weight of ^-55 , and output 2 ⁰ and 2 ^-52 of the adder 107.
When the correction signal shown in FIG. 6 is 01, the bit having the weight of 2 ^-52 of the output of the LR1 shifter is inverted by the bit having the weight of 2 ^-53 and 2 ^-54 and the S bit, and the register 110
When the correction signal is 00, the output of the LR1 shifter 108 is directly stored in the register 110. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has been performed ends. When mantissa subtraction with exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) is executed. LR1
When bits having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. In the rounding correction iterative control circuit 109, the outputs of the adder 107 are 2 ⁰ , 2 ^-52 and 2
^When all the 3 bits with a weight of ^-53 are 1, it indicates the insertion of the step for rounding. On the other hand, the shift number generation circuit 111 generates a shift number necessary for normalizing the output of the LR1 shifter 108, and when this shift number is not 0, the insertion of a step for normalization is instructed. When neither the insertion of a rounding step nor the insertion of a normalization step occurs, the operation ends at this step. (3) Insertion step (only when insertion of a step is instructed) -When adding mantissa Select the output of the register 110 with the multiplexer 103, select the constant 0 with the multiplexer 104, and output the output of the multiplexer 103 and the multiplexer 104 as they are. Complementer 105
Output and 2 generated by the rounding value generation circuit 106 in step 1
^{When the} bit having the weight of ^-53 is set to 1 and the other bit is set to 0, the data is added by the adder 107, and when the bit having the weight of 2 ¹ of the output of the adder 107 is 1 by the LR1 shifter 108, When the bit having the weight of 2 ¹ is 0, the value is stored in the register 110 as it is and the processing is completed. When the mantissa is subtracted except for the exponent difference 0 or 1, the output of the register 110 is selected by the multiplexer 103, the constant 0 is selected by the multiplexer 104, and the output of the multiplexer 103 and the complementer 105 that outputs the multiplexer 104 as they are.
Output and 2 generated by the rounding value generation circuit 106 in step 1
^{When the} bit having the weight of ^-54 is set to 1 and the other bit is set to 0, the data is added by the adder 107, and when the bit having the weight of 2 ¹ of the output of the adder 107 is 1 by the LR1 shifter 108, When the bit having the weight of 2 ¹ is 0, the value is stored in the register 110 as it is and the processing is completed. -When mantissa subtraction with exponent difference 0 or 1 When the shift number generation circuit 111 instructs the insertion of a step for normalization, the barrel shifter 112 receives the register 110 as input, and only the shift number generated by the shift number generation circuit 111 is input. The process shifts to the left, stores it in the register 113, and ends the process.

On the other hand, when the rounding correction repeat control circuit 9 instructs to insert a step for rounding, the register 110
Select the output of the multiplexer 103 with multiplexer 1
A constant 0 is selected in 04, and the output of the multiplexer 103, the output of the complementer 105 which is output from the multiplexer 104 as they are, and the bit having a weight of 2 ⁻⁵² generated by the rounding value generation circuit 106 are set to 1 and the other bits are set to 0. and adder 107 and the data was, by performing 1-bit shift to the right when the bit is 1 with 2 ¹ of the weights of the output of the adder 107 in LR1 shifter 108, the bit having the weight of 2 ¹ When is 0, the same value is stored in the register 110 and the process is terminated.

2 Positive direction rounding mode and negative direction rounding mode
Is over de 2-1 subtraction or the acceleration speed and acceleration number is the exponent and sign and instructions addition of two floating point data when (1) the process steps start before rounding the sum or difference with single precision precision Based on whether or not, the type of operation for mantissa addition or mantissa subtraction and the sign of the operation result are determined as shown in the sign operation relation diagram of FIG. When the sign of the operation result is negative in the positive direction rounding mode or when the sign of the operation result is positive in the negative direction rounding mode, the sign of the operation result is positive in the positive direction rounding mode according to the operation of zero direction rounding mode described later. Or when the sign of the operation result is negative in the negative direction rounding mode, the operation is as follows. The mantissa whose exponent is the smaller of the augend and the addend is stored in register 101, and the mantissa of the augend that is smaller is stored in the register 102. To do. The digit lost during digit alignment is the bit one digit below the least significant bit (L) and the rounding bit (R) with a weight of ^2-24 and ^2-25
It is also stored in the register 102 as a sticky bit (S) which is the logical sum of bits less than or equal to the weighted bit. (2) Step 1-When adding mantissa: The multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of ^2-24 is set to 1 and other bits are set to 0. The complementer 105 uses the output of the multiplexer 104 as it is as an input of the adder 107, and at this time, Cin is set to 0 to execute (register 1) + (register 2) + (rounded addition value). L
When the bit of the output of the adder 107 having the weight of 2 ¹ is 1, the R1 shifter 108 shifts to the right by 1 bit. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
^-One bit (S) is generated by taking the logical sum of the bits below the bit having a weight of ^-25 , and the output of adder 107 is 2 ¹ and 2 ^-22
When 2 ^-23 and the bit and the S bit having the weight of 2 ^-24, register 110 inverts the bits having 2 ^-23 weight of the output of LR1 shifter 108 when the correction signal shown in Figure 7 is 01
When the correction signal is 10, the bit with the weight of 2 ^-22 and 2 ^-23 of the output of the LR1 shifter 108 is inverted and registered.
When the correction signal is 00, the output of the LR1 shifter 108 is stored in the register 110 as it is. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has performed is completed. Mantissa subtraction other than the exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of 2 ^-25 is set to 1 and other bits are set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) + (rounded addition value) is executed. L
R1 when the bit having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
Generate 1 bit (S) by ORing each bit less than or equal to the bit with ^-26 weight, and output 2 ⁰ and 2 ^-23 of the output of adder 107.
When the correction signal shown in FIG. 9 is 01, the bit having the weight of 2 ^-23 of the output of the LR1 shifter 108 is inverted by the bit having the weight of 2 ^-24 and the bit of 2 ^-25 and the S bit, and the register 110
When the correction signal is 10, the bit with the weight of 2 ^-22 and 2 ^-23 of the output of the LR1 shifter 108 is inverted and registered.
When the correction signal is 00, the output of the LR1 shifter 108 is stored in the register 110 as it is. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has been performed ends. When mantissa subtraction with exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) is executed. LR1
When bits having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. Rounding correction repetitive control circuit 109, and instructs the insertion of the step for rounding when two bits are both 1 having a weight of 2 ⁰ and 2 ^-24 of the output of the adder 107. On the other hand, in the shift number generation circuit 111,
The number of shifts required to normalize the output of the LR1 shifter 108 is generated, and if the number of shifts is not 0, the insertion of a step for normalization is instructed. When neither the insertion of a rounding step nor the insertion of a normalization step occurs, the operation ends at this step. (3) Insertion step (only when insertion of a step is instructed) -When adding mantissa Select the output of the register 110 with the multiplexer 103, select the constant 0 with the multiplexer 104, and output the output of the multiplexer 103 and the multiplexer 104 as they are. Complementer 105
Output and 2 generated by the rounding value generation circuit 106 in step 1
^{When the} bit having a weight of ^-24 is set to 1 and the data having the other bits set to 0 are added by the adder 107, and the bit having a weight of 2 ¹ of the output of the adder 107 is 1 by the LR1 shifter 108, When the bit having the weight of 2 ¹ is 0, the value is stored in the register 110 as it is and the processing is completed. When the mantissa is subtracted except for the exponent difference 0 or 1, the output of the register 110 is selected by the multiplexer 103, the constant 0 is selected by the multiplexer 104, and the output of the multiplexer 103 and the complementer 105 that outputs the multiplexer 104 as they are.
Output and 2 generated by the rounding value generation circuit 106 in step 1
Add data with a bit with a weight of ^-25 to 1 and other bits to 0 with an adder 107, and with an LR1 shifter 108, when the bit with a weight of 2 ¹ of the adder 107 is 1, it is right. To 1
Bit shift is performed so that the bit having a weight of 2 ¹ becomes 0.
In the case of, the value as it is is stored in the register 110 and the process is terminated. -When mantissa subtraction with exponent difference 0 or 1 When the shift number generation circuit 111 instructs the insertion of a step for normalization, the barrel shifter 112 receives the register 110 as input, and only the shift number generated by the shift number generation circuit 111 is input. The process shifts to the left, stores it in the register 113, and ends the process.

On the other hand, when the rounding correction repeat control circuit 9 instructs to insert a step for rounding, the register 110
Select the output of the multiplexer 103 with multiplexer 1
A constant 0 is selected in 04, the output of the multiplexer 103, the output of the complementer 105 which is output from the multiplexer 104 as it is, and the bit having a weight of 2 ^-23 generated by the rounding value generation circuit 106 are set to 1 and the other bits are set to 0. and adder 107 and the data was, by performing 1-bit shift to the right when the bit is 1 with 2 ¹ of the weights of the output of the adder 107 in LR1 shifter 108, the bit having the weight of 2 ¹ When is 0, the same value is stored in the register 110 and the process is terminated.

2-2 When the sum and difference of the augend and subtraction and the addend are rounded to double precision (1) Before the start of the processing step Based on whether or not there is a mantissa addition or a mantissa subtraction, the type of operation and the sign of the operation result are determined as shown in the sign operation relation diagram of FIG. When the sign of the operation result is negative in the positive direction rounding mode or when the sign of the operation result is positive in the negative direction rounding mode, the sign of the operation result is positive in the positive direction rounding mode according to the operation of zero direction rounding mode described later. Or when the sign of the operation result is negative in the negative direction rounding mode, the operation is as follows. The mantissa whose exponent is the smaller of the augend and the addend is stored in register 101, and the mantissa of the augend that is smaller is stored in the register 102. To do. The digit that was lost during digit alignment is the bit one digit below the least significant bit (L) and the rounding bit (R) with a weight of 2 ^-53 and 2 ^-54
It is also stored in the register 102 as a sticky bit (S) which is the logical sum of bits less than or equal to the weighted bit. (2) Step 1-When adding mantissa: The multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of 2 ⁻⁵³ is set to 1 and other bits are set to 0. The complementer 105 uses the output of the multiplexer 104 as it is as an input of the adder 107, and at this time, Cin is set to 0 to execute (register 1) + (register 2) + (rounded addition value). L
When the bit of the output of the adder 107 having the weight of 2 ¹ is 1, the R1 shifter 108 shifts to the right by 1 bit. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
^-One bit (S) is generated by ORing the bits below the bit having the weight of ^-54 , and the output of adder 107 is 2 ¹ and 2 ^-51
When the correction signal shown in FIG. 8 is 00, the bit having the weight of 2 ^-52 of the output of the LR1 shifter 108 is inverted by the bit having the weight of 2 ^-52 and 2 ^-53 and the S bit, and the register 110
When the correction signal is 01, the bit with the weight of 2 ⁻⁵¹ and 2 ⁻⁵² of the output of the LR1 shifter 108 is inverted and registered.
When the correction signal is 01, the output of the LR1 shifter 108 is stored in the register 110 as it is. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has performed is completed. Mantissa subtraction other than the exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounding value generation circuit 106 generates data in which a bit having a weight of 2 ⁻⁵⁴ is set to 1 and other bits are set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) + (rounded addition value) is executed. L
R1 when the bit having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. On the other hand, in the rounding correction iterative control circuit 109, the output of the adder 107
Generate a 1-bit (S) that is the logical sum of bits less than or equal to the bit having the weight of ^-55 , and output 2 ⁰ and 2 ^-52 of the adder 107.
When the correction signal shown in FIG. 10 is 01, the bit having the weight of 2 ^-52 of the output of the LR1 shifter 108 is inverted by the bit having the weight of 2 ^-53 and 2 ^-54 and the S bit to register 110
When the correction signal is 01, the bit with the weight of 2 ⁻⁵¹ and 2 ⁻⁵² of the output of the LR1 shifter 108 is inverted and registered.
When the correction signal is 00, the output of the LR1 shifter 108 is stored in the register 110 as it is. When the re-rounding signal of the rounding correction iterative control circuit 109 is 1, an instruction to insert a new step for executing re-addition of the rounding value is made. When the re-rounding signal is 0, this step causes rounding corresponding to rounding accuracy The calculation that has been performed ends. When mantissa subtraction with exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) is executed. LR1
When bits having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. Rounding correction repetitive control circuit 109, and instructs the insertion of the step for rounding when two bits are both 1 having a weight of 2 ⁰ and 2 ^-53 of the output of the adder 107. On the other hand, in the shift number generation circuit 111,
The shift number required to normalize the output of the LR1 shifter 108 is generated, and if this shift number is not 0, the insertion of a step for normalization is instructed. When neither the insertion of a rounding step nor the insertion of a normalization step occurs, the operation ends at this step. (3) Insertion step (only when insertion of a step is instructed) -When adding mantissa Select the output of the register 110 with the multiplexer 103, select the constant 0 with the multiplexer 104, and output the output of the multiplexer 103 and the multiplexer 104 as they are. Complementer 105
Output and 2 generated by the rounding value generation circuit 106 in step 1
^{When the} bit having the weight of ^-53 is set to 1 and the other bit is set to 0, the data is added by the adder 107, and when the bit having the weight of 2 ¹ of the output of the adder 107 is 1 by the LR1 shifter 108, When the bit having the weight of 2 ¹ is 0, the value is stored in the register 110 as it is and the processing is completed. When the mantissa is subtracted except for the exponent difference 0 or 1, the output of the register 110 is selected by the multiplexer 103, the constant 0 is selected by the multiplexer 104, and the output of the multiplexer 103 and the complementer 105 that outputs the multiplexer 104 as they are.
Output and 2 generated by the rounding value generation circuit 106 in step 1
^{When the} bit having the weight of ^-54 is set to 1 and the other bit is set to 0, the data is added by the adder 107, and when the bit having the weight of 2 ¹ of the output of the adder 107 is 1 by the LR1 shifter 108, When the bit having the weight of 2 ¹ is 0, the value is stored in the register 110 as it is and the processing is completed. -When mantissa subtraction with exponent difference 0 or 1 When the shift number generation circuit 111 instructs the insertion of a step for normalization, the barrel shifter 112 receives the register 110 as input, and only the shift number generated by the shift number generation circuit 111 is input. The process shifts to the left, stores it in the register 113, and ends the process.

On the other hand, when the rounding correction repetition control circuit 9 instructs the insertion of a step for rounding, the register 110
Select the output of the multiplexer 103 with multiplexer 1
The constant 0 is selected in 04, and the output of the multiplexer 103, the output of the complementer 105 that is output from the multiplexer 104 as it is, and the bit with a weight of 2 ^-52 generated by the rounding value generation circuit 106 are set to 1
Then, the data having the other bits set to 0 are added by the adder 107, and when the bit having the weight of 2 ¹ of the output of the adder 107 is 1, the LR1 shifter 108 shifts to the right by 1 bit, When the bit having the weight of 2 ¹ is 0, the same value is stored in the register 110 and the process is terminated. 3 Zero direction rounding mode (When the addend / subtract and addend / subtract are single precision and the sum or difference is rounded in single precision, and when the addend / subtract and addend / subtract are double precision and the sum or difference is double precision round Common) (1) Before the start of the processing step Based on the exponent and sign of the two floating point data and whether the instruction is addition or subtraction, the type of operation for mantissa addition or mantissa subtraction and the sign of the operation result are set. It is determined as shown in the sign operation relation diagram of FIG. The mantissa whose exponent is the smaller of the augend and the addend is stored in register 101, and the mantissa of the augend that is smaller is stored in the register 102. To do. (2) Step 1-When adding mantissa: The multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 uses the output of the multiplexer 104 as it is as an input of the adder 107, and at this time, Cin is set to 0 to execute (register 1) + (register 2). LR
When the bit having a weight of 2 ¹ in the output of the adder 107 is 1 in the 1-shifter 108, 1-bit shift is performed to the right and the operation is completed. Mantissa subtraction other than the exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) is executed. LR1
When bit having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 and ends the operation performed one bit shift to the left. When mantissa subtraction with exponent difference 0 or 1, the multiplexer 103 selects the output of the register 101, and the multiplexer 104 selects the output of the register 102. The rounded value generation circuit 106 generates data with all bits set to 0. The complementer 105 inverts the output of the multiplexer 104 and uses it as the input of the adder 107. At this time, by setting Cin to 1, (register 1)-(register 2) is executed. LR1
When bits having the weight of 2 ⁰ of the output of the adder 107 by the shifter 108 is 0 performs a 1-bit shift to the left. The shift number generation circuit 111 generates the shift number necessary for normalizing the output of the LR1 shifter 108, and when this shift number is not 0, the insertion of a step for normalization is instructed. When the insertion of the step for normalization does not occur, the calculation ends at this step. (3) Insertion Step (when inserting steps are indicated only) and mantissa subtraction only when the barrel shifter 112 in exponent difference 0, 1 and inputs the register 110, shifts to left by the shift number generated by the shift number generating circuit 111 Is stored in the register 113 and the process is terminated.

As described above, according to the present embodiment, at the time of adding a mantissa or subtracting a mantissa other than the exponent difference 0 or 1, the sum of the mantissas of two floating point data and the rounded addition value or the former two. In most cases, the processing can be ended by simultaneously performing the sum of the difference between the above and the latter by the adder 107 and normalizing the result by the LR shifter 108. Further, even if the output of the LR shifter 108 needs to be corrected by the instruction of the rounding correction iterative control circuit 109, the processing can be ended without increasing the number of processing steps, and the addition of the rounding addition value in the adder 107 is required again. Only when you do this, you can finish by inserting one step. The probability that one step needs to be inserted is 2/32 in the recent even rounding mode, 32/3 in the positive rounding mode or the negative rounding mode, and 0 in the zero rounding mode (mantissa). (Assuming that the bit pattern is evenly distributed). As a result, in most cases (30/32 in recent even rounding mode, 29/32 in positive rounding or negative rounding mode, 1 in zero rounding mode), it is necessary for addition and subtraction. number of processing steps is as small as 2. The these processing flow shown in FIG. 23 (b). Further, since the single adder 107 performs addition and subtraction of the mantissa and addition of the rounded addition value, the required hardware is less than that of the conventional floating point data addition and subtraction apparatus.

In this embodiment, when the rounding mode is the positive direction rounding mode or the negative direction rounding mode, the mantissa addition is performed by the single precision rounding, the mantissa subtraction of the exponent difference 0 or 1 is performed by the single precision rounding, and the mantissa addition is performed by the double precision rounding. , Rounding value generation circuit 10 depending on the case of mantissa subtraction with double precision rounding and exponent difference 0 or 1
6, the data having the weights of 2 ^-24 , 2 ^-25 , 2 ^-53 , and 2 ^-54 is set to 1 and the other bits are set to 0, and the rounding correction iterative control circuit 109 generates the data shown in FIG. 8, Figure 9, Figure 10
When the correction signal shown in the control relation diagram of is LR1 shifter 10
Bits with weights of 2 ^-23 , 2 ^-23 , 2 ^-52 , 2 ^-52 of 8 outputs are 2 ^-22 and 2 ^-23 , 2 ^-22 and 2 when the correction signal is 10.
^-23 , bits with weights of 2 ^-51 and 2 ^-52 , 2 ^-51 and 2 ^-52 are inverted and stored in the register 110, and when the re-rounding signal of the rounding correction repeat control circuit 109 is 1, the rounding value Although it is instructed to insert a new step of adding the rounded addition value generated by the generation circuit 106 again, the rounding value generation circuit 106 causes 2 ^-23 ,
2 ^-24, 2 ^{- 52,} 2 ^-51 of the other bits by bit to 1 with a weight to generate the data to 0, the rounding correction repetitive control circuit 109 by 11, 12, 13, 14 When the correction signal is 01 in the control relation diagram of, the output of the LR1 shifter 108 is 2
Bits with weights of ^-23 , 2 ^-23 , 2 ^-52 , 2 ^-52 , and 2 ^-22 and 2 ^-23 , 2 ^-22 and 2 ^-23- , 2 ^-51 and 2 when the correction signal is 10 ^The bit having the weight of ^-52 is inverted and stored in the register 110, and when the re-rounding signal of the rounding correction repeating control circuit 109 is 1 and the correction signal is 00, the rounding addition value generated by the rounding value generation circuit 106 is again restored. When the re-rounding signal is 1 and the correction signal is 11, the addition of a new step is instructed to insert a new step of subtracting the rounding addition value generated by the rounding value generation circuit 106 from the value held in the register 110. You may
By doing this, the probability that one step insertion
It is reduced to 2/32, and as a result, the calculation speed is improved.

Further, in this embodiment, when the rounding mode is the positive direction rounding mode or the negative direction rounding mode, the mantissa addition is performed by the single precision rounding, the mantissa subtraction of the exponent difference 0 or 1 is performed by the single precision rounding, and the mantissa addition is performed by the double precision rounding. , Rounding value generation circuit 10 depending on the case of mantissa subtraction with double precision rounding and exponent difference 0 or 1
6 generates data in which bits having weights of 2 ⁻²⁴ , 2 ⁻²⁵ , 2 ⁻⁵³ , and 2 ⁻⁵⁴ are set to 1 and other bits are set to 0, and the rounding correction iterative control circuit 109 generates the data shown in FIGS. 9, although the direct insertion step of re-adding the correction or rounding addition value of a bit by the correction signal and the re-rounding signal indicating the control relationship diagram of FIG. 10, and 2 ^-24 rounding value generating circuit 106 all less, all 2 ^-25 and less, 2 ^{- 53} and less all the bit with all the weight of the 2 ^-54 lower 1
To generate data in which other bits are set to 0, and the rounding correction repeating control circuit 109 corrects or rounds the bits by the correction signal and the re-rounding signal shown in the control relation diagrams of FIGS. 15, 16, 17, and 18. The insertion of the step of re-adding the added value may be instructed. By doing this
The probability that a step needs to be inserted is reduced to 2/32, and as a result, the operation speed is improved. This is the addition of 1 for rounding to the least significant bit (L) when either rounding bit (R) or sticky bit (S) is 1 when the rounding mode is positive rounding mode or negative rounding mode. Rounding addition to the least significant bit using the carry generated by adding the rounded bit and the data in which the bit positions of all bits below it are set to 1. Take advantage of what you can do. FIG. 28 (c) shows the case where the rounding bit and the sticky bit are both 0 and no rounding addition occurs, and FIGS. 28 (d), (e), (f) shows the case where the addition of 1 for rounding occurs otherwise. ).

In the present embodiment, the precision of the augend / subtract and the addend / subtract and the rounding precision are both single precision or double precision. However, the rounding addition value generated by the rounding value generation circuit 106 is set as a rounding bit corresponding to the rounding precision, and the adder 107
By adjusting the number of input bits of (1) to the maximum number of bits of data to be handled, rounding according to the rounding precision can be realized without depending on the precision of the augendable number and the addend / subtract number.

In this embodiment, the mantissa addition is performed by single precision rounding.
Arithmetic, single precision rounding, exponent difference 0 or 1 mantissa subtraction, double precision
Rounding adds mantissa, double precision rounding adds mantissa with exponent difference 0 or 1.
Rounding correction repeat control
Path 109 is 2 of the output of adder 107 ¹And 2^{-twenty two}And 2^{-twenty three}And 2^{-twenty four},
2⁰And 2^{-twenty three}And 2^{-twenty four}And 2^{-twenty five}Two¹And 2^-51And 2^-52When
2^{- 53}Two⁰And 2^-52And 2^-53And 2^-54Bits with weight
And S bit are checked 2^{-twenty two}And 2^{-twenty three}Two^{-twenty two}and
2^{-twenty three}Two^-51And 2^-52Two^-51And 2^-52The weight of
I am instructing the correction of the bit I have, but with the bit to be inspected
The number of bits to be corrected may be increased toward the most significant bit.
Yes. 1 bit increase of inspection bit and correction bit
The probability of requiring one step insertion for each is halved,
As a result, the calculation speed is improved.

FIG. 2 is a block diagram of a floating point data addition / subtraction device according to the second embodiment of the present invention. 2, the same elements as those in FIG. 1 are designated by the same reference numerals. In the figure, 114 is a carry input (Cin) with a bit having a weight of ^2-24 in single precision,
In double precision, carry in a bit with a weight of 2 ^-53 (Cin)
Is a 2-input adder, and 115 is a carry input (C
This is a carry control device that determines (in). Figure 19, Figure 20, Figure 2
1 and FIG. 22 are control relation diagrams of the carry control device 115. When mantissa addition is performed and the rounding precision is single precision, FIG. 19 is shown. When mantissa addition is performed and the rounding precision is double precision, FIG. 20 is shown. When the mantissa subtraction is performed and the rounding precision is single precision, the carry input (Cin) shown in FIG. 21 is given to the adder 114, and when the mantissa subtraction is performed and the rounding precision is double precision, the carry input (Cin) shown in FIG.

The operation of the floating-point data adding / subtracting device of this embodiment having the above-described structure will be described below. This embodiment is the same as the first embodiment shown in FIG.
Instead of performing addition and subtraction of the mantissas of the two floating point data by the input adder 107 and addition of the rounded addition value generated by the rounding value generation circuit 106, carry control of the carry input (Cin) of the two-input adder 114 is carried out. The device 115 is operated to add and subtract mantissas and add rounded addition values. Only the operations of adding / subtracting the mantissa and adding the rounded addition value will be described below, but the other operations are the same as in the first embodiment.・ When adding mantissa If the sign of the operation result is positive in the recent even rounding mode or the positive direction rounding mode, or if the sign of the operation result is negative in the negative direction rounding mode, the rounding precision is single precision or double precision. Accordingly, in order to add 2 ^-24 , 2 ^-53 as a rounded addition value,
As shown in the columns of RN, RP (+) and RM (-) in FIGS. 19 and 20, the carry input (Cin) is set to 1 regardless of the input data.

When the sign of the operation result is negative in the positive direction rounding mode, or when the sign of the operation result is positive in the negative direction rounding mode or in the zero direction rounding mode, it is not necessary to add the rounding addition value. , Carry (Cin) is set to 0 irrespective of the input data as shown in the columns of RP (-), RM (+), RZ in FIGS. -When mantissa is subtracted except for exponent difference 0 or 1, rounding precision is improved when the result is positive in the even rounding mode or in the positive rounding mode, or when the sign is negative in the negative rounding mode. Depending on whether it is single precision or double precision, it is necessary to add 2 ^-25 and 2 ^-54 as rounded addition values and add 1 to the position of the sticky bit (S) for 2's complementing. These additions are 2 ^-25 digits and sticky bit (S) of the data to be added (digit-aligned and 1's complement), 2 ^-54 digits and sticky bit.
When at least one of the (S) is 1 2 ^{- 24,} 2 ^-53 carry input to the (Cin) to 1, 2 ^-25 of digits and the sticky bit data to be added (S), 2 ^-54 When both the digit and the sticky bit (S) are 0, it can be realized by setting the carry input (Cin) to 2 ^-24 , 2 ^-53 to 0. Therefore, in FIG.
The carry input (Cin) depending on the input data as shown in the fields of RN, RP (+), RM (-) in FIG. 22 is generated.

When the sign of the operation result is negative in the positive direction rounding mode, or when the sign of the operation result is positive in the negative direction rounding mode or in the zero direction rounding mode, the rounding precision depends on whether it is single precision or double precision. Therefore, it is necessary to add 1 to the position of the sticky bit (S) for 2's complementing. These additions are performed by adding at least one of 2 ^-25 digits and sticky bit (S), 2 ^-54 digits and sticky bit (S) of the data (digit-aligned and 1's complemented). When it is 0, carry input (Cin) to 2 ^-24 , 2 ^-53 is set to 0, and the digit of 2 ^-25 of the data to be added and the sticky bit (S),
When both the digit of 2 ^-54 and the sticky bit (S) are 1, it can be realized by setting the carry input (Cin) to 2 ^-24 , 2 ^-53 to 1. Therefore, the carry input (Cin) depending on the input data as shown in the columns of RP (−), RM (+), RZ in FIGS. 21 and 22 is generated.・ When mantissa subtraction with exponent difference 0 or 1 Rounding is not executed at the same time as mantissa subtraction. However, depending on whether the rounding precision is single precision or double precision, the sticky bit
It is necessary to add 1 to the position of (S) for 2's complementing. These additions are performed by adding at least one of 2 ^-25 digits and sticky bit (S), 2 ^-54 digits and sticky bit (S) of the data (digit-aligned and 1's complemented). Carry input to 2 ^-24 , 2 ^-53 when 0
Set (Cin) to 0 and add ^2-25 digits and sticky bits (S), 2 ^-54 digits and sticky bits.
When both (S) are 1, carry input to 2 ^-24 , 2 ^-53 (Cin)
It can be realized by setting 1 to 1. Therefore, the RP of FIGS.
Generate carry input (Cin) depending on the input data as shown in the columns of (-), RM (+), RZ.

In any of the above cases, the rounding performed by inserting a step is carried out to add 2 ^-24 , 2 ^-53 as a rounding addition value depending on whether the rounding precision is single precision or double precision. Realize by setting (Cin) to 1.

As described above, according to the present embodiment as well, when adding mantissas or subtracting mantissas other than exponent differences 0 and 1, the sum of the mantissas of two floating point data and the rounded addition value or the former two is calculated. As a result of simultaneously performing the difference and the sum of the latter in the adder 114, in most cases (3/32 in the recent even rounding mode)
0, 32 in positive direction rounding mode or negative direction rounding mode
Min 29, when the null direction rounding mode 1), the processing step number necessary for the addition and subtraction are 2 decreases. Also a single adder
Since the addition and subtraction of the mantissa and the addition of the rounded addition value are executed by 114, the required hardware is smaller than that of the conventional floating point data addition and subtraction device, and the adder 114 is configured with two inputs. The hardware is further reduced as compared with the above embodiment.

FIG. 30 is a block diagram of a floating point data multiplication device according to the third embodiment of the present invention. In FIG. 30, 201 is a multiplicand register that holds the multiplicand, and is a 1-bit sign part 201s and an 11-bit exponent part 201e.
And a 53-bit mantissa part 201f. Reference numeral 202 denotes a multiplier register that holds a multiplier, and includes a 1-bit sign part 202s, an 11-bit exponent part 202e, and a 53-bit mantissa part 202f. When normalized number with a so-called "hidden bit" most significant bit of the multiplicand register mantissa portion 201f and the multiplier register mantissa portion 202f is with the weight of either 2 ⁰ is 1, the multiplicand register 201 and the multiplier except the bit Both registers 202 are in double precision. Reference numeral 203 denotes a code generation circuit that reads out the sign of the multiplicand and the multiplier from the multiplicand register encoder 201s and the multiplier register encoder 202s and generates the sign of the product. An 11-bit exponent adder that reads out the exponent and calculates the exponent of the product. Adds the A and B inputs with Cin as a 1-bit carry input. 205 and 206 are 11-bit selectors that select two inputs of the exponent adder 204 respectively, 207 is a most significant bit correction circuit that inverts the most significant bit of the output of the exponent adder 204, and 208 is addition in the exponent adder 204. A 1-bit latch that holds the overflow from the most significant bit at the time, 209 is the upper overflow (overflow) and the lower overflow (underflow) of the product from the arithmetic precision specified by the output of exponent adder 204 and the value of latch 208. ), 210 is an 11-bit register for holding the output of the exponent adder 204 whose most significant bit is inverted by the most significant bit correction circuit 207 and inputting it again to the exponent adder 204 through the selector 205. A latch 211 is a normalized correction value generation circuit that generates a constant for incrementing the exponent by 1 in accordance with the normalization of the 1-bit shift of the mantissa of the product. 212 is a multiplicand register mantissa part 201f. The high-order 27 bits or lower
A multiplicand upper / lower selection circuit that selects and outputs 27 bits (the most significant bit at this time is 0), and 213 reads the multiplier register mantissa part 202f and outputs the upper 27 bits or the lower 27 bits.
A multiplier upper / lower selection circuit that selects and outputs 27 bits (the most significant bit at this time is 0), and 214 indicates the output of the 27-bit multiplicand upper / lower selection circuit 212 and the 27-bit multiplier upper / lower selection circuit 213. Multiplier that multiplies outputs and outputs 54-bit sum (sum) and carry (carry), 21
Reference numerals 5 and 216 are 54-bit latches that hold the sum output and carry output of the multiplier 214, respectively, and 217 is a rounded addition value that generates a constant when performing addition to round the mantissa of the product to single precision or double precision. A generation circuit, 218 is a 54-bit selector for selecting the value of the latch 216 and the output of the rounded addition value generation circuit 217, 2
19 is the output of the rounded addition value generation circuit 217 and the latch 225 described later.
54-bit selector, which selects the value held in
Reference numeral 220 denotes a 54-bit mantissa adder that adds the value held in the latch 215 and the output of the selector 218 and the output of the selector 219, and 221 denotes 0 or 1 bit of the output of the mantissa adder 220 in the least significant bit direction. Or a 54-bit shifter that shifts by 26 bits, 222 indicates a shift overflow from 22 bits from the most significant bit to the 47th bit of the output of the mantissa adder 220 and the 26 least significant bit of the shifter 221. To generate a sticky bit depending on whether the rounding precision is single precision or double precision, 223 rounds the 24th bit from the most significant bit of the shifter 221 output when the rounding precision is single precision. When the precision is double precision, the mantissa correction circuit that inverts and outputs the 53rd bit as necessary, 224 indicates the most significant bit of the output of the mantissa adder 220
A total of 6 bits from the 23rd bit to the 25th bit, the least significant bit to the 3rd bit to the least significant bit, and one overflow bit from the most significant bit at the time of addition in the mantissa adder 220 and the sticky bit generation circuit 222 And the mantissa correction for controlling the bit inversion performed by the mantissa correction circuit 223 and the addition of the rounding addition value in the mantissa adder 220 depending on whether the rounding precision is single precision or double precision. A control circuit, 225 is a 54-bit latch that holds the output of the shifter 221, and 226 is a product register that holds the product. 1-bit sign part 226s and 11-bit exponent part 226e and 53
It consists of the mantissa part 226f of the bit. When normalized number with a so-called "hidden bit", also the most significant bit of the product register mantissa portion 226f having a 2 ⁰ weight is 1, product register 226 except for this bit meets the precision. FIG. 31 is an internal block diagram of the multiplicand upper / lower selection circuit 212 and the multiplier upper / lower selection circuit 213 shown in FIG. 30, in which 227 extends 0 to the upper 27 bits or the lower 26 bits of the 53-bit input.
This is a selector that selects a 27-bit type. 32 is an operation explanatory diagram showing constants generated by the rounded addition value generation circuit 217 shown in FIG. 30, and only the 25th bit from the most significant bit is 1
Then, a rounded addition value A of 0 is generated for the other and a rounded addition value B of 2 for only the second bit from the most significant bit is 0, and a rounded addition value C of 1 for only the least significant bit is 1 and the other is 0. Figure 33 and Figure 34
In the control relation diagram of the mantissa correction control circuit 224 shown in FIG. 30, when the rounding precision is single precision, as shown in FIG.
23th to 25th bits (Z
₂₂ , Z ₂₃ , Z ₂₄ ), the sticky bit (S) output by the sticky bit generation circuit 222, and the overflow in the mantissa adder 220.
The necessity of bit inversion of the mantissa and the necessity of re-addition of the rounded addition value are determined from (Cout). When the rounding precision is double precision, as shown in FIG. 34, from the third least significant bit to the least significant bit (Z ₅₁ , Z ₅₂ , Z ₅₃ ) of the output of the mantissa adder 220 and the sticky bit generation circuit 222. Determines the necessity of bit inversion of the mantissa and the necessity of re-addition of the rounded addition value based on the sticky bit (S) output by the above and the overflow (Cout) in the mantissa adder 220.

The operation of the floating point data multiplication device of this embodiment having the above-described configuration will be described below. Here, the rounding mode is the even rounding mode as an example.

First, the case where the multiplicand and the multiplier are single precision and the product is rounded with single precision will be described with reference to the operation flow diagram of single precision multiplication shown in FIG. 35 and the mode diagram of addition and shift in single precision multiplication shown in FIG. . FIG. 35 shows the exponent adder 204, the exception detection circuit 209, the multiplier 214, the mantissa adder 220, and the shifter 22.
1. The contents of the operation of each processing step of the mantissa correction circuit 223 are shown. FIG. 36 shows the mantissa adder 220 and the shifter 221 among them.
3 shows a detailed operation mode in FIG. (1) Before start of processing step The single precision multiplicand and the multiplicand are expanded to double precision and stored in the multiplicand register 201 and the multiplier register 202, respectively. At this time, the multiplicand register exponent part 201e and the multiplier register exponent part 20
Both 2e are converted into a double-precision bias expression (true exponent value = exponent part value-1023 ₍₁₀₎ ), and the multiplicand register mantissa part 20
Zeros are filled in 1f and the lower 29 bits of the multiplier register mantissa part 202f. (2) Step 1 The selector 205 inputs the exponent of the multiplicand held in the multiplicand register exponent unit 201e to the A input of the exponent adder 204,
The exponent of the multiplier held in the multiplier register exponent unit 202e by the selector 206 is input to the B input of the exponent adder 204, and the carry input Cin is set to 1 to perform addition in the exponent adder 204. The most significant bit of the addition result is inverted by the most significant bit correction circuit 207. The addition result in which the most significant bit is inverted is stored in the latch 210 .

[0087]

[0088]

[0089]

The latch 208 holds the overflow in the exponent adder 204 at this time. The multiplicand upper / lower selection circuit 212 reads and outputs the upper 27 bits of the multiplicand register mantissa part 201f (the value A shown in FIG. 36 (a) includes all the effective bits of the mantissa part of the multiplicand and the lower 3 The bit is 0), and the multiplier upper / lower selection circuit 213 is a multiplier register mantissa part 2
The upper 27 bits of 02f are read and output (the value B shown in FIG. 36 (a) includes all effective bits of the mantissa part of the multiplier, and the lower 3 bits are 0). The multiplier 214 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 212 and the multiplier upper / lower selection circuit 213, and stores the sum output and the carry output in the latch 215 and the latch 216, respectively. At the same time, in the code generation circuit 203, the multiplicand register code part 201s and the multiplier register code part 202s are read out to obtain the codes of the multiplicand and the multiplier, the exclusive OR of the two is taken, and the product code is generated and stored in the product register code part 226s. . (3) Step 2 The mantissa adder 220 outputs the sum output (lower 7 bits are 0) of the multiplier 214 held in the latch 215 and the latch 2 by the selector 218.
The carry output (the lower 7 bits are 0) of the multiplier 214 held in 16 and the rounding addition value A generated by the rounding addition value generation circuit 217 are added by the selector 219. Mantissa adder at this time
Depending on the presence / absence of a digit overflow (Z ₋₁ ) from 220: When there is a digit overflow from the mantissa adder 220, that is, when the product of the mantissa parts is 2 or more, the shifter 221 outputs from the mantissa adder 220 for normalization. 1 bit in the direction of the least significant bit (at this time, the most significant bit is filled with 1), and the selector 205 and the selector 2
According to 06, the exponent adder 204 adds the value of the latch 210 and the constant 1 output from the normalized correction value generation circuit 211 and stores the result in the product register exponent part 226e. When there is no overflow from the mantissa adder 220, that is, when the product of the mantissa parts is 1 or more and less than 2, the shifter 221 does not need to perform normalization, so the mantissa adder 2
Output from 20 as it is without shifting, selector
205 and selector 206 cause exponent adder 204 to latch 210
The value of is output as it is and stored in the product register exponent part 226e. Do one of the following. The value of latch 208 does not change. The exception detection circuit 209 detects the upper overflow (OVF) and the lower overflow (UNF) of the single-precision product based on the output (denoted by E) of the exponent adder 204 based on the following logic.

[0091]

[Equation 11]

The sticky bit generation circuit 222 takes the logical sum of 22 bits from the 26th bit to the 47th bit (Z ₂₅ , ... Z ₄₆ ) from the most significant bit of the output of the mantissa adder 220 and outputs the value in 22 bits. Sticky bit output if there is even one bit
(S) is set to 1, and if all 22 bits have the value 0, the sticky bit output (S) is set to 0. Mantissa correction control circuit 224
Is the 23rd to the 25th bit (Z ₂₂ , Z ₂₃ , Z _{2 4} ) from the most significant bit of the output of the mantissa adder 220, the sticky bit (S) output from the sticky bit generation circuit 222, and the mantissa adder 22.
Mantissa correction circuit based on overflow at 0 (Cout = Z _-1 )
Controlling 223, the mantissa correction circuit 223 inverts the 24th bit (R ₂₃ ) from the most significant output of the shifter 221 if the correction signal column in FIG. 33 is 1, and outputs it without inverting if it is 0. . At the same time, if the rounded addition signal column in the figure is 0, the mantissa correction circuit 22
The lower 29 bits of 53 bits excluding the most significant bit of the output of 3 are masked to 0 and stored in the product register mantissa 226f, and the processing is ended. Mantissa correction circuit if the rounded addition signal column is 1.
After storing the output of 223 in latch 225, the next insertion step is performed. (3) Insertion step (only when the rounding addition signal column is 1) The mantissa adder 220 is a rounding addition value generation circuit by the selector 218.
Latched by rounding addition value A generated by 217 and selector 219
The value held by 225 is added. Mantissa adder 220 at this time
No overflow occurs. Shifter 221 is mantissa adder 220
Of the mantissa correction circuit 22
3 also outputs the output of the shifter 221 as it is without bit inversion. After that, the lower 29 bits of 53 bits excluding the most significant bit of the output of the mantissa correction circuit 223 are masked to 0 and stored in the product register mantissa part 226f, and the process is ended.

Next, an operation flow chart of double-precision multiplication shown in FIG. 37 and a mode diagram of addition and shift in double-precision multiplication shown in FIGS. 38 and 39 in the case where the multiplicand and the multiplier are double-precision and the product is rounded with double-precision. It demonstrates using. FIG. 37 shows the exponent adder 204,
Exception detection circuit 209, multiplier 214, mantissa adder 220, shifter 2
21, the contents of the operation of the mantissa correction circuit 223 for each processing step are shown, and FIG. 38 and FIG. 39 show the detailed operation modes of the mantissa adder 220 and the shifter 221 among them. (1) Before the start of the processing step The double-precision multiplicand and the multiplier are respectively set to the multiplicand register 20.
Stored in 1 and multiplier register 202. At this time, the multiplicand register exponent part 201e and the multiplier register exponent part 202e are both double-precision bias expressions (true exponent value = exponent part value−1023 ₍₁₀₎ )
It has become. (2) Step 1 The selector 205 inputs the exponent of the multiplicand held in the multiplicand register exponent unit 201e to the A input of the exponent adder 204,
The exponent of the multiplier held in the multiplier register exponent unit 202e by the selector 206 is input to the B input of the exponent adder 204, and the carry input Cin is set to 1 to perform addition in the exponent adder 204. The most significant bit of the addition result is inverted by the most significant bit correction circuit 207. The addition result in which the most significant bit is inverted is stored in the latch 210 . The latch 208 holds the overflow in the exponent adder 204 at this time. The multiplicand upper / lower selection circuit 212 reads out and outputs the lower 27 bits of the multiplicand register mantissa part 201f (AL shown in FIG. 38, the most significant bit is 0).
The multiplier upper / lower selection circuit 213 reads out and outputs the lower 27 bits of the multiplier register mantissa 202f (value BL shown in FIG. 38, the most significant bit is 0). The multiplier 214 includes a multiplicand upper / lower selection circuit 212 and a multiplier upper / lower selection circuit 2
Multiply is executed based on the input from 13 and the sum output and the carry output are stored in the latch 215 and the latch 216, respectively. At the same time, in the code generation circuit 203, the multiplicand register encoder 201s
And the sign of the multiplicand and the multiplier are read from the multiplier register encoder 202s, the exclusive OR of the two is taken, the product code is generated and stored in the product register encoder 226s. (3) Step 2 The mantissa adder 220 outputs the sum output of the multiplier 214 held in the latch 215 (the upper 2 bits and the lowermost bit are 0) and the selector 21.
The carry output of the multiplier 214 (the upper 2 bits and the least significant bit are 0) held in the latch 216 by 8 and the rounding addition value B generated by the rounding addition value generation circuit 217 are added by the selector 219. At this time, the mantissa adder 220 does not overflow. The shifter 221 outputs the mantissa adder 220 output (W ₀ , ..., W
_52,0 ) is shifted 26 bits in the direction of the least significant bit (0 is filled in at the higher order at this time) and the result (0, ..., 0, W ₀ , ..., W ₂₇ ) is stored in the latch 225. To do. The value stored in latch 225 is the lowest partial product. At the same time, the multiplicand upper / lower selection circuit 21
2 reads out and outputs the lower 27 bits of the multiplicand register mantissa part 201f (value AL shown in FIG. 38, the most significant bit is 0), and the multiplier upper / lower select circuit 213 causes the multiplier register mantissa part 2
Reads and outputs the upper 27 bits of 02f (value B shown in Fig. 38)
U). The multiplier 214 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 212 and the multiplier upper / lower selection circuit 213, and stores the sum output and the carry output in the latch 215 and the latch 216, respectively. (4) Step 3 The mantissa adder 220 outputs the sum output (the most significant bit and the least significant bit are 0) of the multiplier 214 held in the latch 215 and the selector 21.
The carry output of the multiplier 214 held in the latch 216 by 8 (the most significant bit and the least significant bit is 0) and the output of the shifter 221 held in the latch 225 by the selector 219 (the upper 26 bits are 0) are added. To do. At this time, no overflow occurs from the mantissa adder 220. The shifter 221 is a mantissa adder 220 (X ₀ ,
..., X ₅₃ ) output is output as it is without shifting and latched
Store in 225. The value stored in latch 225 is an accumulation up to the first middle partial product. The multiplicand upper / lower selection circuit 212 reads and outputs the upper 27 bits of the multiplicand register mantissa part 201f (value AU shown in FIG. 38), and the multiplier upper / lower selection circuit 213 reads and outputs the lower 27 bits of the multiplier register mantissa part 202f. (The value BL shown in FIG. 38 has the most significant bit 0). The multiplier 214 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 212 and the multiplier upper / lower selection circuit 213, and latches the sum output and the carry output respectively.
And store in latch 216. (5) Step 4 The mantissa adder 220 outputs the sum output (the most significant bit and the least significant bit are 0) of the multiplier 214 held in the latch 215 and the selector 21.
The carry output (the most significant bit and the least significant bit are 0) of the multiplier 214 held in the latch 216 by 8 is added to the output of the shifter 221. The shifter 221 is 55-bit data in which 54 bits (Y ₀ , ... Y ₅₃ ) of the output of the mantissa adder 220 are added with 1-bit overflow (Y _-1 ) from the mantissa adder 220 on the most significant bit side.
(Y _-1,, Y ₀ , ..., Y ₅₃ ) is shifted by 26 bits in the direction of the least significant bit (at this time, the higher order is filled with 0) and the result (0, ..., 0,
Y ₋₁ , Y ₀ , ..., Y ₂₇ ) are stored in the latch 225. The value stored in latch 225 is an accumulation up to the second middle partial product. At the same time, the multiplicand upper / lower selecting circuit 212 reads and outputs the upper 27 bits of the multiplicand register mantissa part 201f (value AU shown in FIG. 38), and the multiplier upper / lower selecting circuit 213 reads the upper 27 bits of the multiplier register mantissa part 202f. Output (value BU shown in FIG. 38). The multiplier 214 executes multiplication based on the inputs from the multiplicand upper / lower selection circuit 212 and the multiplier upper / lower selection circuit 213, and stores the sum output and the carry output in the latch 215 and the latch 216, respectively. (6) Step 5 The mantissa adder 220 outputs the sum output (the least significant bit is 0) of the multiplier 214 held in the latch 215 and the latch 2 by the selector 218.
The carry output of the multiplier 214 held in 16 (the least significant bit is 0) and the output of the shifter 221 held in the latch 225 by the selector 219 (the upper 25 bits are 0) are added. Depending on the presence or absence of a digit overflow (Z ₋₁ ) from the mantissa adder 220 at this time: When there is a digit overflow from the mantissa adder 220, that is, when the product of the mantissa parts is 2 or more, the shifter 221 uses the mantissa for normalization. The output from the adder 220 is shifted toward the least significant bit by 1 bit (at this time, the most significant bit is filled with 1), and the selector 205 and the selector 2
According to 06, the exponent adder 204 adds the value of the latch 210 and the constant 1 output from the normalized correction value generation circuit 211 and stores the result in the product register exponent part 226e. -When there is no overflow from the mantissa adder 220, that is, when the product of the mantissa part is 1 or more and less than 2, the shifter 221 does not need to perform normalization, and therefore the output from the mantissa adder 220 is output as it is without shifting. Then, the exponent adder 204 outputs the value of the latch 210 as it is by the selector 205 and the selector 206 and stores it in the product register exponent part 226e. Do one of the following. The value of latch 208 does not change. The exception detection circuit 209 outputs the output of the exponent adder 204 (E ₀ , ..., E ₁₀ ) and the latch 208.
The value of ( value of Ce) is the upper overflow (OV
F) and lower overflow (UNF) are detected based on the following formula. However, ￣X represents the inversion of X.

[0094]

[Equation 12]

The sticky bit generation circuit 222 shifts overflows (W ₂₈ , ..., W _52,0 ) from the least significant bit of the 26 bits in the shifter 221 in step 2 and the 26 bits of the 26 bits in the shifter 221 in step 4. The 52 bit OR including the shift overflow (Y ₂₈ , ..., Y ₅₃ ) from the least significant bit is taken, and if there is even one bit of value 1 in 52 bits, the sticky bit output (S) is output. Set to 1 and all 52 bits have value 0
If so, the sticky bit output (S) is set to 0. The mantissa correction control circuit 224 outputs the third bit from the least significant bit (Z ₅₁ , Z ₅₂ , Z ₅₃ ) of the output of the mantissa adder 220 and the sticky bit (S) output by the sticky bit generation circuit 222.
And the mantissa correction circuit 223 is controlled based on the overflow (Cout = Z ₋₁ ) in the mantissa adder 220,
If the column of the correction signal of 34 is 1, the second least significant bit (R ₅₂ ) of the output of the shifter 221 is inverted, and if it is 0, it is output without being inverted. At the same time, if the rounded addition signal column in the figure is 0, 53 bits excluding the least significant bit of the output of the mantissa correction circuit 223 are stored in the product register mantissa part 226f, and the process ends. If the rounded addition signal column is 1, the output of the mantissa correction circuit 223 is stored in the latch 225, and then the following insertion step is executed. (6) Insertion step (only when the rounding addition signal column is 1) The mantissa adder 220 is a rounding addition value generation circuit by the selector 218.
Rounded addition value C generated by 217 and latched by selector 219
The value held by 225 is added. Mantissa adder 220 at this time
No overflow occurs. Shifter 221 is mantissa adder 220
Of the mantissa correction circuit 22
3 also outputs the output of the shifter 221 as it is without bit inversion. After that, 53 bits excluding the least significant bit of the output of the mantissa correction circuit 223 are stored in the product register mantissa part 226f, and the process is ended.

[0096]

As described above, according to the present embodiment , addition of rounding addition values in the mantissa part or addition for accumulating partial products, and sum output and carry output from the multiplier 214 are performed. The addition can be performed by the mantissa adder 220, and the result can be normalized by the shifter 221. In most cases, the processing can be ended. Further, even if correction by the mantissa correction circuit 223 is necessary, the processing can be ended without increasing the number of processing steps, and only one step is necessary when the addition of the rounded addition value by the mantissa adder 220 is required again. You can finish by inserting. The probability that one step needs to be inserted is as small as 2/32 (assuming that the mantissa bit pattern is evenly distributed). As a result, in most cases (probability of 30/32), the number of processing steps required for single-precision multiplication is 2, and the number of processing steps required for double-precision multiplication is 5. In addition, since the single mantissa adder 220 performs addition of sum and carry and addition of rounded addition value or addition for accumulating partial products, necessary hardware is Fewer than the multiplication device.

Although the present embodiment gives an example of realizing the even rounding mode recently, the rounding addition value generation circuit 217 and the mantissa correction control circuit are also used for the positive direction rounding mode, the negative direction rounding mode and the zero direction rounding mode. It can be easily handled by changing the control of 224. The operation related to rounding in this case is similar to that shown in the first embodiment, and the control of bit inversion of the mantissa operation result and the insertion of the processing step is performed with reference to FIGS.
9, FIG. 10 or FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG.
6, according to the control relationship diagram of FIG. 17, FIG.

In this embodiment, the case where the multiplicand and the multiplier are both single precision and the product is rounded to the single precision and the case where the multiplicand and the multiplier are both double precision and the product is rounded to the double precision are described. Even if the combination of precision and the rounding precision of products are combined, the sticky bit generation circuit
By causing the sticky bit generation logic in 222 to correspond to all valid bits lower than the rounding bit, it is possible to obtain a rounded product with a predetermined precision.

In this embodiment, depending on whether the rounding precision is single precision or double precision, the mantissa correction control circuit 224 causes the mantissa adder 220 to output from the most significant bit to the 23rd to 25th bits. The third bit to the least significant bit from the lower bit, the 1-bit overflow from the most significant bit at the time of addition in the mantissa adder 220, and the 1-bit sticky bit output from the sticky bit generation circuit 222 are inspected to correct the mantissa. Although the circuit 223 inverts the 24th bit or the 53rd bit from the most significant bit of the output of the shifter 221, the bit to be inspected and the bit to be inverted may be increased in the most significant bit direction. The probability that one step needs to be inserted for each increase of the bit to be checked and the bit to be inverted is halved, and as a result, the operation speed is improved.

FIG. 40 is a block diagram of a floating point data division device according to the fourth embodiment of the present invention. In FIG. 40, 301 is a dividend register for holding the dividend, which is a 1-bit sign part 301s and an 11-bit exponent part 301e.
And a 53-bit mantissa part 301f. Reference numeral 302 denotes a divisor register that holds a divisor, and includes a 1-bit sign part 302s, an 11-bit exponent part 302e, and a 53-bit mantissa part 302f. The most significant bit of the dividend register mantissa portion 301f and the divisor register mantissa 302f is 1 when the so-called the "hidden bit" of normalized number with the weight of any 2 ^0, the dividend register 301 and the divisor except this bit The registers 302 both match double precision. Reference numeral 303 denotes a code generation circuit that reads the code of the dividend and divisor from the dividend register code unit 301s and the divisor register code unit 302s to generate the code of the quotient, and 304 denotes the dividend and divisor from the dividend register exponent unit 301e and the divisor register exponent unit 302e. An 11-bit exponent subtractor that reads out the exponent and calculates the quotient exponent performs addition with Cin which is a 1-bit carry input and which is the one's complement of the A and B inputs. Reference numerals 305 and 306 denote 11-bit selectors that select the two inputs of the exponent subtractor 304, 307 denotes a most significant bit correction circuit that inverts the most significant bit of the output of the exponent subtractor 304, and 308.
Is a 1-bit latch that holds the overflow from the most significant bit at the time of addition in exponent subtractor 304, and 309 is the upper overflow of the quotient from the arithmetic precision specified by the output of exponent subtractor 304 and the value of latch 308 (overflow). ) And an exception detection circuit for detecting a lower overflow (underflow), 310 holds the output of the exponent subtractor 304 whose most significant bit has been inverted by the most significant bit correction circuit 307, and again passes through the selector 305 to the exponent subtractor 304. 11-bit latch for input, 311
Is an exponent with the normalization of the 1-bit shift of the quotient mantissa.
A normalization correction value generation circuit for generating a constant for decrementing only, 312 reads the dividend register mantissa part 301f and the divisor register mantissa part 302f and normalizes the mantissa of the quotient. A well-known mantissa arithmetic unit for obtaining a signal and
A quotient register 313 holds a quotient, and is a 1-bit code part 313.
It consists of s, an 11-bit exponent part 313e, and a 53-bit mantissa part 313f. Also the most significant bit of the quotient register mantissa portion 313f when the number of normalized so-called "hidden bit" with a weight of 2 ⁰ is 1, the quotient register 313 except for this bit meets the precision.

The operation of the floating point data division device of the present embodiment having the above configuration will be described below with reference to the operation flow chart of division shown in FIG. The figure shows the contents of the operations of the exponent subtractor 304, the exception detection circuit 309, and the mantissa calculator 312 for each processing step. (1) Before start of processing step When the dividend and the divisor are single precision, they are expanded to double precision and stored in the dividend register 301 and the divisor register 302, respectively. When the dividend and the divisor have double precision, they are stored in the dividend register 301 and the divisor register 302 as they are. In either case, the dividend register exponent part 301e and the divisor register exponent part 30
Both 2e are double-precision bias expressions (true exponent value = exponent part value−1023 ₍₁₀₎ ). (2) Step 1 Input the exponent of the dividend held in the dividend register exponent section 301e by the selector 305 to the A input of the exponent subtractor 304,
The exponent of the divisor held in the divisor register exponent unit 302e by the selector 306 is input to the B input of the exponent subtractor 304, and the carry input Cin is set to 0.
+ B + Cin is added (B is the one's complement of B, Cin =
When 0, this addition is equivalent to AB-1). The most significant bit of the addition result is inverted by the most significant bit correction circuit 307. The addition result with the most significant bit inverted is stored in the latch 310. It can be proved that the value held in the latch 310 is an index of the correctly biased quotient. (Begin proof) In ANSI / IEEE floating point arithmetic standard P754, double-precision bias value

[0103]

[Equation 13]

It is defined as On the other hand, e1: exponent part of dividend of bias expression (11 bits) e2: exponent part of divisor of bias expression (11 bits) ed: exponent part of quotient of bias expression (11 bits)

[0105]

[Numerical equation 14]

It can be transformed into (X is the inversion of X). Item 3
Addition of 100 0000 0000 ₍₂₎ can be realized by inverting the most significant bit. (End of certification) The latch 308 holds the overflow in the exponent subtractor 304 at this time. The mantissa calculator 312 reads the dividend and the divisor from the dividend register mantissa part 301f and the divisor register mantissa part 302f, and starts division. At the same time, the code generation circuit 303
At, the code of the dividend and the divisor are read from the dividend register code unit 301s and the divisor register code unit 302s, the exclusive OR of the two is taken, and the quotient code is generated and stored in the quotient register code unit 313s. (3) Step 2 The mantissa calculator 312 generates the mantissa part of the quotient and rounds it. When the mantissa part of the generated quotient is a denormalized number, that is, when the value is 0.5 or more and less than 1, the mantissa arithmetic unit 312 shifts the mantissa part of the generated quotient to the 1-bit most significant bit direction and normalizes it. The selector 305 and selector 306 cause the exponent subtractor 304 to subtract the constant 1 output from the normalized correction value generation circuit 311 from the value in the latch 310. When the mantissa part of the generated quotient is a normalized number, that is, when the value is 1 or more and less than 2, the mantissa operation part
The 312 outputs the mantissa part of the generated quotient as it is, and the exponent subtractor 304 also outputs the value of the latch 310 as it is by the selector 305. In either case, the mantissa calculator 312
Masks the lower 29 bits of the 53 bits excluding the least significant bit of the result to 0 when the rounding precision is single precision, and the 53 bits excluding the least significant bit of the result are rounded as they are when the rounding precision is double precision. Stored in register mantissa 313f, exponent subtractor 30
4 stores the result in the quotient register exponent part 313e. Latch 308
The value of does not change. When the rounding precision is single precision, the exception detection circuit 309 detects the upper overflow (OVF) and the lower overflow (UNF) of the quotient by the output (denoted by E) of the exponent subtractor 304 based on the following logic.

[0107]

[Equation 15]

If the rounding precision is double precision, the exponent subtractor 304
Of the quotient ( _{O 0} , ..., E ₁₀ ) and the value of the latch 308 (Ce), the upper overflow (OVF) and the lower overflow (UNF) of the quotient are detected based on the following logical expressions. However, ￣X represents the inversion of X.

[0109]

[Equation 16]

As described above, according to this embodiment, the exponent subtractor 304 subtracts (exponent of dividend)-(exponent of divisor) -1 by setting the carry input Cin to 0, and the most significant bit correction circuit. Since the addition of the bias value is realized by the inversion of the most significant bit in 307, and the exponent part of the biased floating-point quotient can be obtained in a single processing step like the dividend and divisor, the exponent part The step of correcting the bias of is unnecessary. Also, the most significant bit correction circuit 30
7 can be easily realized by a 1-bit exclusive OR gate,
No special hardware for bias correction is required and the hardware can be reduced.

[0111]

As described above, according to the present invention,
It is possible to reduce the number of processing steps required to obtain the mantissa part of the sum, difference, and product of rounded floating-point data with the specified rounding mode and rounding precision. It can be implemented with less hardware, and its practical effects are great.

Further, according to the present invention, it is possible to reduce the number of processing steps required to obtain the exponent part of the quotient of the bias-corrected floating-point data , and it is possible to reduce the number of processing steps compared to the conventional floating-point data arithmetic unit. It can be realized with less hardware, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a floating point data addition / subtraction device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a floating point data addition / subtraction device according to a second embodiment of the present invention.

FIG. 3 is a control relationship diagram of a rounding correction iterative control circuit 109 in a nearest even rounding mode of the floating point data adder / subtractor according to the first and second embodiments of the present invention.

FIG. 4 is a control relationship diagram of a rounding correction iterative control circuit 109 in a nearest even rounding mode of the floating point data adder / subtractor according to the first and second embodiments of the present invention.

FIG. 5 is a control relationship diagram of a rounding correction iterative control circuit 109 in the nearest even rounding mode of the floating point data adder / subtractor according to the first and second embodiments of the present invention.

FIG. 6 is a control relationship diagram of a rounding correction iterative control circuit 109 in the nearest even rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 7 is a control relationship diagram of a rounding correction iterative control circuit 109 in a positive rounding mode or a negative rounding mode of the floating-point data adding / subtracting device in the first and second embodiments of the present invention.

FIG. 8 is a control relationship diagram of a rounding correction iterative control circuit 109 in a positive rounding mode or a negative rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 9 is a control relationship diagram of a rounding correction repeating control circuit 109 in a positive rounding mode or a negative rounding mode of the floating-point data adding / subtracting device according to the first and second embodiments of the present invention.

FIG. 10 is a control relationship diagram of a rounding correction iterative control circuit 109 in a positive rounding mode or a negative rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 11 is a control relationship diagram of the rounding correction iterative control circuit 109 in the positive-direction rounding mode or the negative-direction rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 12 is a control relationship diagram of a rounding correction repeating control circuit 109 in a positive rounding mode or a negative rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 13 is a control relationship diagram of a rounding correction iterative control circuit 109 in a positive rounding mode or a negative rounding mode of a floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 14 is a control relationship diagram of a rounding correction iterative control circuit 109 in a positive rounding mode or a negative rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 15 is a control relationship diagram of the rounding correction iterative control circuit 109 in the positive-direction rounding mode or the negative-direction rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 16 is a control relationship diagram of the rounding correction iterative control circuit 109 in the positive-direction rounding mode or the negative-direction rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 17 is a control relationship diagram of the rounding correction iterative control circuit 109 in the positive rounding mode or the negative rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 18 is a control relationship diagram of the rounding correction iterative control circuit 109 in the positive rounding mode or the negative rounding mode of the floating-point data adding / subtracting device according to the first and second embodiments of the present invention.

FIG. 19 is a control relationship diagram of the carry control device 115 of the floating point data addition / subtraction device according to the second embodiment of the present invention.

FIG. 20 is a control relationship diagram of a carry control device 115 of the floating point data addition / subtraction device according to the second embodiment of the present invention.

FIG. 21 is a control relationship diagram of a carry control device 115 of an adding / subtracting device for floating-point data according to the second embodiment of the present invention.

FIG. 22 is a control relationship diagram of the carry control device 115 of the addition / subtraction device for floating-point data according to the second embodiment of the present invention.

FIG. 23 is a processing flowchart of a conventional floating point addition / subtraction device and floating point data addition / subtraction devices according to the first and second embodiments of the present invention.

FIG. 24 is an input / output relationship diagram of the rounding value generation circuit 106 of the floating point data addition / subtraction device according to the first embodiment of the present invention.

FIG. 25 is an input / output relationship diagram of the rounding value generation circuit 106 of the floating point data addition / subtraction device according to the first embodiment of the present invention.

FIG. 26 is a code operation relation diagram of the adder operation of the floating-point data addition / subtraction device and the operation result code determination method in the first and second embodiments of the present invention.

FIG. 27 is an explanatory diagram showing the presence / absence of rounding addition in the conventional floating point data addition / subtraction device and the floating point data addition / subtraction devices in the first and second embodiments of the present invention.

FIG. 28 is a principle diagram of a carry occurrence at the time of rounding addition in the nearest value rounding mode and the positive direction negative direction rounding mode rounding mode of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 29 is a mode diagram of addition / subtraction, which is the principle of the floating-point data addition / subtraction device in the first and second embodiments of the present invention.

FIG. 30 is a block diagram of a floating point data multiplication device according to a third embodiment of the present invention.

FIG. 31 is a multiplicand upper / lower selection circuit 212 in the embodiment.
And block diagram of multiplier upper / lower selection circuit 213

FIG. 32 is an operation explanatory diagram of the rounded addition value generation circuit 217 in the embodiment.

FIG. 33 is a control relation diagram of the mantissa correction control circuit 224 in the embodiment.

FIG. 34 is a control relationship diagram of the mantissa correction control circuit 224 in the same embodiment.

FIG. 35 is an operation flowchart of single precision multiplication in the embodiment.

FIG. 36 is a mode diagram of addition and shift at the time of single precision multiplication in the embodiment.

FIG. 37 is an operation flowchart of double-precision multiplication in the example.

FIG. 38 is a mode diagram of addition and shift at the time of double-precision multiplication in the example.

FIG. 39 is a mode diagram of addition and shift at the time of double-precision multiplication in the example.

FIG. 40 is a block diagram of a floating point data division device according to a fourth embodiment of the present invention.

FIG. 41 is an operation flowchart of division in the embodiment.

FIG. 42 is a block diagram of a conventional floating point data addition / subtraction device.

FIG. 43 is a block diagram of a conventional floating point data multiplication device.

FIG. 44 is an operation explanatory diagram of the rounded addition value generation circuit 267 in the conventional example.

FIG. 45 is an operation flowchart of single precision multiplication in the conventional example.

FIG. 46 is an operation flowchart of double precision multiplication in the conventional example.

[Explanation of symbols]

 101 register 102 register 110 register 113 register 103 multiplexer 103 multiplexer 105 complementer 106 rounding value generation circuit 107 adder 114 adder 108 LR1 shifter 109 rounding correction repetition control circuit 111 shift number generation circuit 112 barrel shifter 115 carry control device

Claims (41)

[Claims] 1. In the case of true mantissa addition in which floating-point data is arithmetically added with the same sign or subtracted with the different sign, addition and addition of the first and second mantissas in which the same exponent is aligned are performed. And a true mantissa subtraction in which the floating-point data is subtracted with the same sign or added with the different sign by simultaneously performing the addition with the rounding addition value that is uniquely determined by the rounding precision, the rounding mode, and the sign of the operation result. Simultaneously performs subtraction and subtraction of the first and second mantissas digit-matched to the same exponent and addition with a rounding addition value that is uniquely determined by the rounding precision, the rounding mode, and the sign of the operation result. After the addition and subtraction of the first and second mantissas and the rounded addition value, when the operation result is a denormalized number, the operation result is shifted by 1 bit for normalization, and the normalized operation is then performed. Rounding out of the normalized operation results by inspecting a plurality of bits including the least significant bit determined by the type of operation and the rounding precision that indicates whether it is true mantissa addition or true mantissa subtraction from the result Carry up to higher bits than the checked bit whether the least significant bit determined by precision matches the true mantissa addition or the true mantissa subtraction of the first mantissa and the second mantissa rounded to a predetermined precision. Is not matched, only a bit that has been inspected does not match, a carry to the higher order of the inspected bit or a higher order bit of the inspected bit does not match, and the process is terminated based on the result of the determination, A part or all of the bits inspected for the normalized operation result are corrected and the processing is terminated, or the rounded addition value is added again to the normalized operation result and the processing is terminated. Addition and subtraction method of floating-point data of the conduct either to. 2. The addition and subtraction of the first and second mantissas and the rounded addition value, the normalization of 1-bit shift, and the check are performed in one processing step, and as a result of the check, a carry to a higher order than the check bit is performed. If only the checked and matched bits do not match, a part or all of the checked bits are further corrected in the processing step, and if the result of the check is that the carry to the higher order bit does not match. 2. The floating point data addition / subtraction method according to claim 1, wherein the rounded addition value is re-added to the normalized operation result by inserting a new processing step after the processing step is completed. 3. The rounding addition value when the floating point data is calculated by adding a true mantissa is a single precision having a rounding precision of up to 23 decimal places, and is the nearest even rounding mode, or positive in the single precision. When the sign of the operation result is positive in the direction rounding mode or when the sign of the operation result is negative in the single-direction negative rounding mode, the bit having the weight of 2-24 is set to 1 and the other bits are set to 0. The rounding precision is a double precision having up to 52 decimal places in the rounding precision in the even even rounding mode or the positive precision in the double precision rounding mode and the sign of the operation result is positive or the negative in the double precision. -53 of 2 when the output sign is negative in direction rounding mode
2. A method of adding / subtracting floating-point data according to claim 1, wherein the bit having the weight of the power is a value set to 1 and the other bits are set to 0, and all other bits are set to 0 in the other cases. 4. The rounded addition value when the floating point data is calculated by adding a true mantissa, the rounding precision is a single precision having a binary fraction of up to 23 decimal places, and the sign of the operation result is positive in the positive direction rounding mode. If the sign of the operation result is negative in the negative precision rounding mode in the above single precision or the above-mentioned single precision, it is a numerical value in which the bit having a weight of 2-23 is set to 1 and the other bits are set to 0, and the rounding precision is a binary decimal. 52nd
If the sign of the operation result is positive in the double-precision, positive-direction rounding mode that has up to the order, or if the output sign is negative in the double-precision, negative-direction rounding mode, set the bit with the weight of -52 to 2 to 1 2. A method of adding / subtracting floating-point data according to claim 1, wherein the value is a value in which other bits are set to 0, and the value is set to 0 in all other cases except the above. 5. The rounded addition value when the floating-point data operation is a true mantissa addition is a single-precision forward rounding mode in which the rounding precision has up to 23 decimal places, and the sign of the operation result is positive. When the sign of the operation result is negative in the case of negative precision rounding mode in the above single precision, the bit having a weight of 2-24 and the bit having a weight less than that are set to 1 and the other bits are set to 0. Numerical value, the rounding precision is up to 52 decimal places, and is 2 when the sign of the operation result is positive in double precision and positive direction rounding mode or the output sign is negative in the double precision and negative direction rounding mode. -A number that sets the bit with weight of 5th power and the bit with weight less than 1 to 1 and other bits to 0,
The addition / subtraction method of floating-point data according to claim 1, wherein the value is a value in which all bits are set to 0 at times other than the above. 6. The rounding addition value when the floating-point data operation is true mantissa subtraction is a single precision having a rounding precision of up to 23 decimal places and is the nearest even rounding mode, or positive in the single precision. When the sign of the operation result is positive in the direction rounding mode or when the sign of the operation result is negative in the single-direction negative direction rounding mode, the bit having the weight of 2-25 is set to 1 and the other bits are set to 0. The rounding precision is a double precision having up to 52 decimal places in the rounding precision in the even even rounding mode or the positive precision in the double precision rounding mode and the sign of the operation result is positive or the negative in the double precision. -54 of 2 when the output sign is negative in the direction rounding mode
2. A method of adding / subtracting floating-point data according to claim 1, wherein the bit having the weight of the power is a value set to 1 and the other bits are set to 0, and all other bits are set to 0 in the other cases. 7. The rounded addition value when the floating point data is calculated by the true mantissa subtraction is single precision with the rounding precision having up to 23 decimal places, and the sign of the operation result is positive in the forward rounding mode. If the sign of the operation result is negative in the above-mentioned single-precision negative-direction rounding mode, the bit with a weight of 2-24 is set to 1 and the other bits are set to 0. Rounding precision is a binary decimal. 52nd
If the sign of the operation result is positive in the double-precision, positive-direction rounding mode that has up to the order, or if the output sign is negative in the double-precision, negative-direction rounding mode, set the bit with a weight of -53 to 2 to 1 2. A method of adding / subtracting floating-point data according to claim 1, wherein the value is a value in which other bits are set to 0, and the value is set to 0 in all other cases except the above. 8. The rounding addition value when the floating-point data operation is a true mantissa subtraction is a single-precision forward rounding mode in which the rounding precision has up to 23 decimal places, and the sign of the operation result is positive. If the sign of the operation result is negative in the negative precision rounding mode in the above single precision, the bit having a weight of 2-25 and the bit having a weight less than that are set to 1 and the other bits are set to 0. Numerical value, the rounding precision is up to 52 decimal places, and is 2 when the sign of the operation result is positive in double precision and positive direction rounding mode or the output sign is negative in the double precision and negative direction rounding mode. -A number that sets the bit with weight of 5 to the power of 4 and the bit with lower weight to 1 and other bits to 0,
The addition / subtraction method of floating-point data according to claim 1, wherein the value is a value in which all bits are set to 0 at times other than the above. 9. When the check bit of the normalized operation result after the normalization is single precision when the floating point data operation is true mantissa addition and the rounding precision has up to 23 decimal places of binary fraction. It is a 1-bit that is the logical sum of 3 bits with weights of −22, 2−23 and 2−24, and each bit with a weight less than that, with true mantissa addition and rounding precision. In the case of double precision with up to the 52th decimal place, the logical sum of 3 bits with the weight of 2 -51, 2 -52 and 2 -53 and each bit with less weight is calculated. 1 bit is taken, and in the case of the above-mentioned single precision in true mantissa subtraction, each bit having a weight of 2 -23 and 2 -24 is ORed with each bit having a weight less than 1 Bits with weights of -52, 2 -53 and 2 -54 when double precision is used in true mantissa subtraction and bits with weights smaller than that. 2. The method of adding / subtracting floating-point data according to claim 1, wherein the addition / subtraction is 1 bit obtained by logically summing the bits. 10. A bit to be corrected based on the judgment result is
2 if the rounding precision is single precision with up to 23 decimal places
Bits with weight of -23 or 2 -22 and 2 -23
Bits with power of 2 and rounding precision with double precision having up to 52 decimal places, bits with weight of -52 to 2 or weight of -51 to 2 and -52 to 2 The addition / subtraction method for floating-point data according to claim 1, wherein the addition / subtraction is a bit that has. 11. An operation indicating whether the operation of floating-point data is a true mantissa addition that is addition of the same sign or a subtraction of different signs, or a subtraction of the same sign or a true mantissa subtraction that is addition of different signs. Rounding addition value generation means for generating a rounding addition value that is uniquely determined by the type, rounding precision, rounding mode, and sign of the operation result, and the first and second numbers that perform digit alignment on the same exponent during true mantissa addition. Simultaneous addition of the mantissa and addition of the addition result and the rounded addition value generated by the rounding addition value generation means are performed at the same time, and at the time of true mantissa subtraction, the first and second mantissas are digit-matched to the same exponent. And the mantissa addition / subtraction executing means for simultaneously performing addition of the subtraction result and the rounding addition value generated by the rounding addition value generating means, and the operation result when the operation result by the mantissa addition / subtraction executing means is a denormalized number. Shift positive A plurality of bits including the least significant bit determined by rounding precision from the output of the normalizing means and the normalizing means, and the least significant bit determined by the rounding precision among the outputs of the normalizing means Only the bits that have been checked because they match the true mantissa addition or true mantissa subtraction of the first mantissa and the second mantissa rounded to a predetermined precision An operation result inspecting unit that determines whether they do not match, or whether a carry to an upper bit of the inspected bit does not match an upper bit of the inspected bit, and the operation result inspecting unit inspects the output of the normalizing unit. Rounding correction means for correcting a part or all of the processed bits, and the operation result inspection means outputs up to the least significant bit among the outputs of the normalization means. When it is determined that the first mantissa and the second mantissa rounded to a constant precision match in true mantissa addition or true mantissa subtraction, the process is terminated, and the carry to the higher bits than the inspected bit is one. If it is determined that only the inspected bits do not match, the rounding correction means corrects a part or all of the output of the normalization means to end the processing, and the carry to the higher order than the inspected bits is also inspected. If it is determined that the bits higher than the above bit do not match, the rounding addition value generating means and the mantissa addition / subtraction executing means add the rounding addition value again to the output of the normalizing means, and the processing is terminated. Characteristic floating point data addition / subtraction device. 12. A first and second mantissa addition / subtraction executing means.
The addition and subtraction of the mantissa and the rounded addition value, the normalization by the normalizing means, and the check by the operation result checking means are performed in one machine cycle, and as a result of the check, it is inspected that the carry to the higher order than the check bit is the same. If only the bits do not match, a part or all of the checked bits in the rounding correction means are further corrected within the machine cycle, and if the result of the check is that the carry to the higher order than the check bit does not match, 12. The addition / subtraction device for floating-point data according to claim 11, wherein the rounding addition value in the mantissa addition / subtraction executing means is added again by inserting a new machine cycle after the end of the machine cycle. 13. The rounded addition value generated by the rounded addition value generation means is when the operation of floating-point data is true mantissa addition,
Rounding precision with up to 23 decimal places in single precision in the even rounding mode or in the above single precision in the positive direction rounding mode When the sign of the operation result is positive or in the above single precision in the negative direction rounding mode When the sign of the result is negative, it is a numerical value in which the bit having the weight of 2-24 is set to 1 and the other bits are set to 0, and the rounding precision is the double even precision rounding up to the 52nd decimal place. In mode or in the double precision positive rounding mode when the sign of the operation result is positive or in the double precision negative direction rounding mode and the output sign is negative, set the bit with the weight of -53 to 2 to 1. And the other bits are set to 0, the floating-point data operation is true mantissa subtraction, the rounding precision is the single precision and the even rounding mode, or the single precision is the positive direction rounding mode. When the sign of is positive or in the single precision in the negative direction rounding mode -25 if the sign of the result is negative
A value in which the bit with the weight of the power of 1 is set to 1 and the other bits are set to 0. When the rounding precision is the double precision and the even rounding mode is in the nearest even rounding mode, or the double precision is the positive direction rounding mode, the sign of the operation result is positive. If the output sign is negative in negative double-precision rounding mode with the above double precision, it is a numerical value in which the bit having the weight of -54 to 2 is set to 1 and the other bits are set to 0. In other cases, all bits are set. 12. The floating point data adding / subtracting device according to claim 11, which is a numerical value in which is zero. 14. The rounded addition value generated by the rounded addition value generation means is when the operation of floating-point data is true mantissa addition,
If the sign of the operation result is positive in the single-precision, positive-direction rounding mode with rounding precision up to 23 decimal places, or if the sign of the operation result is negative in the single-precision, negative-direction rounding mode, the value of 2 is- 2
A numeric value in which the bit with the weight of the third power is set to 1 and the other bits are set to 0, and the rounding precision is double precision with binary fraction up to the 52nd decimal place. If the output sign is negative in the double-precision negative-direction rounding mode, it becomes 2
-A numerical value in which the bit with the weight of the 52nd power is set to 1 and the other bits are set to 0. When the floating point data is calculated by true mantissa subtraction, the rounding precision is the single precision and the calculation result in the forward rounding mode. When the sign of is positive or when the sign of the operation result is negative in the above-mentioned single precision negative direction rounding mode, the bit with weight of 2-24 is set to 1 and the other bits are set to 0, and rounded. When the precision is the above-mentioned double precision and the positive direction rounding mode and the sign of the operation result is positive, or when the above-mentioned double precision and the negative direction rounding mode and the output sign is negative, the bit having the weight of -53 to 2 is set to 1. 12. The floating-point data adding / subtracting device according to claim 11, which is a numerical value in which other bits are set to 0 and is set to a numerical value in which all the bits are set to 0 in cases other than the above. 15. The rounded addition value generated by the rounded addition value generation means is when the operation of floating-point data is true mantissa addition,
If the sign of the operation result is positive in the single-precision, positive-direction rounding mode with rounding precision up to 23 decimal places, or if the sign of the operation result is negative in the single-precision, negative-direction rounding mode, the value of 2 is- 2
It is a numerical value in which the bit with the weight of the fourth power and the bit with the weight less than that are set to 1 and the other bits are set to 0, and the rounding precision is double precision with up to the 52nd decimal place. When the sign of the operation result is positive or when the output sign is negative in the double-precision negative direction rounding mode, the bit having a weight of -53 to the power of 2 and the bit having a weight smaller than that are set to 1 and other bits are set. Is 0, the floating-point data operation is true mantissa subtraction, the rounding precision is the single precision and the positive direction rounding mode, and the sign of the operation result is positive, or the single precision is the negative direction rounding mode. When the sign of the operation result is negative,
-A numerical value in which bits with weights of -25th power and bits with lower weights are set to 1 and other bits are set to 0. Rounding precision is double precision, and the sign of the operation result is positive in the positive direction rounding mode. When the output sign is negative in negative precision rounding mode with double precision, the bit with weight of -54 to 2 and the bit with weight less than 1 are set to 1 and the other bits are set to 0. 12. The addition / subtraction device for floating-point data according to claim 11, which is a numerical value in which all bits are set to 0 at times other than the above. 16. The bit checked by the operation result checking means is
When the operation of floating-point data is true mantissa addition and the rounding precision is up to 23 decimal places, it has a weight of 2-22, 2-23 and 2-24. 1 bit that is the logical sum of 3 bits and each bit with a weight smaller than that, and in the case of true mantissa addition and double precision with rounding precision up to 52 decimal places, it is 2 −51 2 -52 and 2 -53
It is 1 bit that is the logical sum of 3 bits having the weight of the power of 2 and each bit having the weight less than that. In the case of the single precision by the true mantissa subtraction, the power of 2 -23 and the power of 2 -24 and 2 3 bits having a weight of -25 to the OR of each bit having a weight smaller than that, and 2 bits of -52 and 2 of -53 when the double precision is obtained by true mantissa subtraction. 12. The addition / subtraction device for floating-point data according to claim 11, wherein 3 bits having a weight of the power of 2 and −54 to a power of 2 and 1 bit obtained by logically adding each bit having a weight less than that. 17. When the bit to be corrected by the correction means is a single precision having a rounding precision of up to 23 decimal places, a bit having a weight of 2 -23 or 2 -22 and 2-. A bit with a weight of 23, and a bit with a weight of -52 to the power of 2 when the rounding precision is double precision with up to 52 decimal places or 2
12. Bits having weights of −51 and 2 −52.
Addition / subtraction device for the described floating point data. 18. Multiplying each mantissa part of a multiplicand and a multiplier in a floating point format to obtain a product by dividing the product into a sum (sum) and a carry (carry), and after the multiplication, the sum, the carry and the rounding. An operation of adding the rounding addition value uniquely determined by the precision and the rounding mode and the sign of the multiplicand and the multiplier is performed, and when the operation result is a denormalized number, the operation result is shifted by 1 bit. Normalize,
After the normalization, a plurality of bits including the least significant bit determined by the rounding precision are inspected from the normalized operation result, and up to the least significant bit determined by the rounding precision among the normalized operation results are predetermined. Whether the product of the mantissa of the multiplicand and the mantissa of the multiplier rounded to precision matches, or the carry to the upper bits of the inspected bits match and only the inspected bits do not match, or the higher bits than the inspected bits Carry is also determined whether the higher bits than the inspected bit do not match, the process is terminated based on the determination result, or a part or all of the bits inspected for the normalized operation result are Correct and finish the process,
A method of multiplying floating-point data, wherein the rounded addition value is added again to the normalized operation result and the processing is ended. 19. The sum, carry, rounding addition value addition, 1-bit shift normalization, and check are performed in one processing step, and as a result of the check, carry to a higher order than the check bit is matched. If only the bits examined by
If some or all of the inspected bits are further corrected in the processing step, and if the result of the inspection is that the carry to the higher order than the inspection bit does not match, the rounded addition value for the normalized operation result is added. 20. The floating point data multiplication method according to claim 18, wherein the re-addition is performed by inserting a new processing step after the completion of the processing step. 20. The rounding addition value has a rounding precision of a binary decimal number 23.
2 when the precision of the single-precision most recent rounding mode with up to the order or the positive sign of the operation result in the single-precision positive-direction rounding mode or the negative sign of the operation result in the single-precision negative-direction rounding mode A number that has a bit with a weight of -24 raised to 1 and other bits to 0. Rounding precision is double precision with up to 52 decimal places. When the sign of the operation result is positive in the direction rounding mode or when the output sign is negative in the double precision negative direction rounding mode, the bit having the weight of -53 to 2 is set to 1 and the other bits are set to 0. 19. The method of multiplying floating-point data according to claim 18, which is a numerical value and is a numerical value in which all bits are set to 0 except the above. 21. The rounding addition value has a rounding precision of a binary decimal number 23.
When the sign of the operation result is positive in the single-precision, positive-direction rounding mode with up to the order, or when the sign of the operation result is negative in the single-precision, negative-direction rounding mode, the bit with the weight of 2 to -23 is set. Rounding precision is 2 with 1 and other bits set to 0.
When the sign of the operation result is positive in the double-precision, positive-direction rounding mode having up to 52 decimal places, or when the output sign is negative in the double-precision, negative-direction rounding mode, the weight is 2 −52. 19. The method of multiplying floating-point data according to claim 18, wherein the value is a numerical value in which one bit is set to 1 and the other bits are set to 0, and all the bits are set to 0 in the cases other than the above. 22. The rounding addition value has a rounding precision of a binary decimal number 23.
When the sign of the operation result is positive in the single-precision, positive-direction rounding mode having up to the unit, or when the sign of the operation result is negative in the single-precision, negative-direction rounding mode, a bit having a weight of 2-24 When a bit with a smaller weight is set to 1 and the other bits are set to 0, the rounding precision is double precision with binary fraction up to the 52nd decimal place, and the sign of the operation result is positive in the positive direction rounding mode. Alternatively, when the output sign is negative in the double-precision negative-direction rounding mode, a bit having a weight of -53 to the power of 2 and a bit having a weight less than that are set to 1 and other bits are set to 0, 19. The method of multiplying floating-point data according to claim 18, which is a numerical value in which all bits are set to 0 at times other than the above. 23. When the check bit of the normalized operation result after the normalization is single precision having rounding precision up to the 23rd decimal place, 2-22 and 2-23. 3 bits with a weight of -24th power of 1 and 1 bit obtained by ORing each bit with a weight less than that. When rounding precision is double precision with up to 52 decimal places, it is -51 of 2 Square and 2-5 2 Square and 2-5
19. The method of multiplying floating-point data according to claim 18, wherein 3 bits having a weight of a cube of 3 and 1 bit having a weight less than that are ORed. 24. A bit to be corrected based on the judgment result is
2 if the rounding precision is single precision with up to 23 decimal places
Bits with weight of -23 or 2 -22 and 2 -23
Bits with power of 2 and rounding precision with double precision having up to 52 decimal places, bits with weight of -52 to 2 or weight of -51 to 2 and -52 to 2 19. The method of multiplying floating-point data according to claim 18, which is a bit that has. 25. The bit widths of the two inputs are both equal to or longer than the length of the mantissa part of the multiplicand and the multiplier in the floating-point format, and are longer than the length of the mantissa part, at least twice as many bits as the inputs. Mantissa multiplication means for outputting the sum (sum) of widths and carry (carry), and rounding addition value generation means for generating a rounding addition value uniquely determined by the rounding precision, the rounding mode, and the sign of the two floating point data. And a mantissa adding means for simultaneously performing the sum output and carry output of the mantissa multiplying means and the addition of the three rounding addition values from the rounding addition value generating means, and the operation result by the mantissa addition means being a denormalized number. In the case of, the normalization means for shifting and normalizing the operation result, and a plurality of bits including the least significant bit determined by the rounding precision among the outputs of the normalization means are inspected to perform the normalization procedure. Of the output of the above, up to the least significant bit determined by the rounding precision is the same as the product of the mantissa of the multiplicand and the mantissa of the multiplier rounded to a predetermined precision, or the carry to the higher bits than the inspected bit is the same. Operation result inspecting means for deciding whether only the inspected bits do not match, or whether the carry to the upper bits of the inspected bits or the upper bits of the inspected bits do not match, and Rounding correction means for correcting some or all of the bits inspected by the operation result inspection means, and the sum output and digit obtained by inputting the mantissa parts of the multiplicand and the multiplier in the floating point format into the mantissa multiplication means. The sum of the three values of the rounded output and the rounded addition value from the rounded addition value generation means is obtained by the mantissa addition means, and the result is normalized by the normalization means, and then the calculation is performed. If the result inspecting means determines that the least significant bit determined by the rounding precision among the outputs of the normalizing means matches the mantissa of the product rounded to a predetermined precision, the processing is terminated and the higher bits than the inspected bit Only the bits that the carry to
If it is determined that they do not match, the rounding correction means corrects a part or all of the output of the normalization means, and the processing is terminated. Carry to the higher bits than the inspected bits and bits higher than the inspected bits are performed. If it is determined that they do not match, the rounding addition value generating means and the mantissa adding means add the rounding addition values again to the output of the normalizing means, and the processing is terminated, and the multiplication of the floating point data is performed. apparatus. 26. Sum output, carry output, rounding addition value addition in the mantissa adding means, normalization in the normalization means, and inspection in the operation result inspection means are performed in one machine cycle, and the inspection result is concerned. If the carry to the upper bits is the same and only the inspected bit does not match, some or all of the inspected bits in the rounding correction means are further corrected within the machine cycle, and as a result of the inspection, the inspection concerned. 26. The floating-point data multiplication device according to claim 25, wherein when the carry to the upper bits does not match, the rounded addition value in the mantissa adding means is added again by inserting a new machine cycle after the end of the machine cycle. . 27. The rounding addition value generated by the rounding addition value generation means is calculated in the single precision nearest even rounding mode having a rounding precision of up to 23 decimal places or in the forward rounding mode in the single precision. When the sign of the result is positive or when the sign of the operation result in the negative precision rounding mode in the above-mentioned single precision is negative, it is a numerical value in which the bit with the weight of 2-24 is set to 1 and the other bits are set to 0, Rounding precision with up to 52 decimal places in double precision in the even rounding mode or in the double precision in the positive direction rounding mode, when the sign of the operation result is positive or in the double precision negative direction rounding mode, the output sign 25 is a numerical value in which a bit having a weight of 2 −53 is set to 1 and the other bits are set to 0, and otherwise is a numerical value in which all the bits are set to 0.
The described floating point data multiplication device. 28. The rounding addition value generated by the rounding addition value generating means is a single precision having a rounding precision of up to 23 decimal places in the forward rounding mode, and when the sign of the operation result is positive or the single precision. When the sign of the operation result is negative in the negative direction rounding mode, the bit with weight of 2-23 is set to 1 and the other bits are set to 0, and the rounding precision is up to the 52nd decimal place. If the sign of the operation result is positive in the double-precision, positive-direction rounding mode, or if the output sign is negative in the double-precision, negative-direction rounding mode, set the bit having the weight of -52 to 2 to 1 and set the other bits. Is a numerical value with 0 set, and in all other cases, all bits are set to 0
26. The floating-point data multiplication device according to claim 25, which is a numerical value of 29. The rounding addition value generated by the rounding addition value generation means is a single precision having a rounding precision of up to 23 decimal places in the positive rounding mode, and the sign of the operation result is positive or the single precision. In the negative direction rounding mode, when the sign of the operation result is negative, it is a numerical value in which the bit having the weight of 2-24 is set to 1 and the bit having the weight smaller than that, and the other bits are set to 0.
Rounding precision is up to 52 decimal places. In double precision and positive direction rounding mode, when the sign of the operation result is positive, or when the double precision negative direction rounding mode and the output sign is negative, 26. Floating-point data according to claim 25, which is a numerical value in which a bit having a weight and a bit having a smaller weight are set to 1 and other bits are set to 0, and in all other cases, all bits are set to 0. Multiplication device. 30. The bit checked by the operation result checking means is
2 if the rounding precision is single precision with up to 23 decimal places
Rounding precision is the 52nd place of the binary decimal number with 1 bit that is the logical sum of 3 bits with the weights of −22, 2−23 and 2−24 In case of double precision having up to, it is 1 bit obtained by ORing 3 bits having weights of -51 to 2 to -52 to 2 to -53 and each bit having less weight. 26. The floating point data multiplication device according to claim 25. 31. When the bit to be corrected by the correcting means is a single precision having a rounding precision of up to 23 decimal places, a bit having a weight of 2 -23 or 2 -22 and 2-. A bit with a weight of 23, and a bit with a weight of -52 to the power of 2 when the rounding precision is double precision with up to 52 decimal places or 2
26. Bits having weights of -51 and 2 -52.
The described floating point data multiplication device. 32. A multiplicand holding means for holding a mantissa part of a multiplicand in a floating point format, a multiplier holding means for holding a mantissa part of a multiplier in a floating point format, and a bit width of at least one of two inputs A mantissa multiplication means for outputting a sum (sum) and a carry (carry) of at least twice the bit width of the input, which is shorter than the length of the mantissa part of the multiplicand and the multiplier, and the mantissa multiplication means. When the bit width of the multiplicand input is shorter than the length of the mantissa part of the multiplicand, the multiplicand inputs of the mantissa multiplying means from the most significant bit to the least significant bit of the mantissa part of the multiplicand held in the multiplicand holding means The partial multiplicand selecting means for dividing the partial mantissa part having the bit width of 1 and selecting and outputting one for each processing step, and the bit width of the multiplier input of the mantissa multiplying means is the multiplier. When the mantissa part is shorter than the length, the most significant bit to the least significant bit of the mantissa part of the multiplier held in the multiplier holding means is divided into a plurality of partial mantissa parts of the bit width of the multiplier input of the mantissa multiplying means. Then, a partial multiplier selecting means for selecting and outputting one for each processing step among them, and a rounded addition value generation for generating a rounded addition value uniquely determined by the rounding precision, the rounding mode, and the sign of two floating point data Means and the first step of the processing, the sum output and carry output of the mantissa multiplication means and the addition of three of the rounding addition values from the rounding addition value generation means are performed at the same time to generate the first partial product. The step is a mantissa adding means for simultaneously performing the sum output carry output of the mantissa multiplying means and the addition of the three partial products generated in the immediately preceding step and shifted to generate a new partial product, and In the first or intermediate step, the partial product obtained from the mantissa adding means is shifted in the least significant bit direction by the number of bits determined by the positions of the partial mantissa parts of the multiplier and the multiplicand multiplied in the mantissa multiplying means in the step, and the final bit In the step, when the operation result obtained from the mantissa adding means is a non-normalized number, a shift means for shifting the operation result to normalize it and an output of the shift means in the first or intermediate step of the process The partial product holding means held as an input in the mantissa adding means, each bit of the shift overflow in the shift means in the first or intermediate step of the processing and the rounding precision determined by the rounding precision in the output of the shift means in the final step of the processing. The shift means in the final step of processing by inspecting a plurality of bits including lower bits Of the output of the above, up to the least significant bit determined by the rounding precision is the same as the product of the mantissa of the multiplicand and the mantissa of the multiplier rounded to a predetermined precision, or the carry to the higher bits than the inspected bit is the same. Operation result inspecting means for determining whether only the inspected bits do not match, or whether the carry to the upper bits of the inspected bits does not match the upper bits of the inspected bits, and the operation for the output of the shift means. Rounding correction means for correcting a part or all of the bits inspected by the result inspection means, and the partial multiplicand selection means and the mantissa part of the multiplicand in the partial multiplier selection means are arranged in order from the lowermost and all combinations. Is input to the mantissa multiplication means and sequentially obtained sum output and carry output, and the rounding addition value from the rounding addition value generating means or the section The sum of the three values held in the product holding means is obtained by the mantissa adding means and the result is shifted by the shift means and stored again in the partial product holding means, or the final calculation result is obtained by the shift means. After normalization, if the operation result inspection means determines that the least significant bit of the output of the shift means determined by the rounding precision matches the mantissa of the product rounded to a predetermined precision, the process is terminated, When it is determined that the carry to the higher order than the inspected bit matches and only the inspected bit does not match, a part or all of the output of the shift means is corrected by the rounding correction means, the processing is terminated, and the inspection is performed. If it is determined that the carry to the upper bits of the selected bits does not match the upper bits of the inspected bits, the rounded addition value is generated for the output of the shift means. Multiplier floating point data, characterized in that the process ends by adding the addition value rounding the stage and the mantissa addition means. 33. In the final step of the processing, the sum output and carry output in the mantissa adding means, the addition of the values held in the partial product holding means, the normalization in the shift means and the check in the operation result checking means are combined into one. In the machine cycle, if the result of the above check is that the carry to the higher order bit of the check bit matches and only the bit that has been checked does not match,
If some or all of the inspected bits in the rounding correction means are further modified within the machine cycle, and the result of the inspection is that the carry to the higher order than the inspection bit does not match, the rounded addition value in the mantissa adder means 33. The floating point data multiplication device according to claim 32, wherein the addition is performed by inserting a new machine cycle after the end of the machine cycle. 34. The rounding addition value generated by the rounding addition value generation means is calculated in the single precision nearest even rounding mode having the rounding precision up to the 23rd decimal place or in the forward rounding mode in the single precision. When the sign of the result is positive or when the sign of the operation result in the negative precision rounding mode in the above-mentioned single precision is negative, it is a numerical value in which the bit with the weight of 2-24 is set to 1 and the other bits are set to 0, Rounding precision with up to 52 decimal places in double precision in the even rounding mode or in the double precision in the positive direction rounding mode, when the sign of the operation result is positive or in the double precision negative direction rounding mode, the output sign 32 is a numerical value in which a bit having a weight of -53 to 2 is set to 1 and other bits are set to 0 when is negative, and is a numerical value in which all bits are set to 0 otherwise.
The described floating point data multiplication device. 35. The rounding addition value generated by the rounding addition value generating means is single precision having a rounding precision of up to 23 decimal places in the positive direction rounding mode, and the sign of the operation result is positive or the single precision. When the sign of the operation result is negative in the negative direction rounding mode, the bit with weight of 2-23 is set to 1 and the other bits are set to 0, and the rounding precision is up to the 52nd decimal place. If the sign of the operation result is positive in the double-precision, positive-direction rounding mode, or if the output sign is negative in the double-precision, negative-direction rounding mode, set the bit having the weight of -52 to 2 to 1 and set the other bits. Is a numerical value with 0 set, and in all other cases, all bits are set to 0
33. The multiplying device for floating-point data according to claim 32, which is a numerical value of 36. The rounding addition value generated by the rounding addition value generating means is a single precision having a rounding precision of up to 23 decimal places in the positive direction rounding mode and the sign of the operation result is positive, or the single precision. In the negative direction rounding mode, when the sign of the operation result is negative, it is a numerical value in which the bit having the weight of 2-24 is set to 1 and the bit having the weight smaller than that, and the other bits are set to 0.
Rounding precision is up to 52 decimal places. In double precision and positive direction rounding mode, when the sign of the operation result is positive, or when the double precision negative direction rounding mode and the output sign is negative, 33. Floating point data according to claim 32, which is a numerical value in which a bit having a weight and a bit having a smaller weight are set to 1 and other bits are set to 0, and all the bits are set to 0 in the cases other than the above. Multiplication device. 37. The bit checked by the operation result checking means is
2 if the rounding precision is single precision with up to 23 decimal places
Rounding precision is the 52nd place of the binary decimal number with 1 bit that is the logical sum of 3 bits with the weights of −22, 2−23 and 2−24 In case of double precision having up to, it is 1 bit obtained by ORing 3 bits having weights of -51 to 2 to -52 to 2 to -53 and each bit having less weight. 33. The floating point data multiplication device according to claim 32. 38. When the bit to be corrected by the correction means is a single precision having a rounding precision of up to 23 decimal places, a bit having a weight of 2-23 or 2-22 and 2-. A bit with a weight of 23, and a bit with a weight of -52 to the power of 2 when the rounding precision is double precision with up to 52 decimal places or 2
32. Bits having weights of -51 and 2 -52.
The described floating point data multiplication device. 39. An operation for obtaining a value smaller by one than the value obtained by subtracting the exponent part of the divisor in the same floating-point format from the exponent part of the dividend in the floating-point format having a deviated exponent part, and performing the above-mentioned operation After that, by inverting the most significant bit of the operation result, the exponent part of the quotient in the floating-point format, which is offset like the dividend and the divisor, is obtained in a single processing step. Division method. 40. An exponent subtraction means for obtaining a value smaller by 1 than a value obtained by subtracting the exponent part of the divisor in the same floating-point format from the exponent part of the dividend in the floating-point format having a deviated exponent part,
A most significant bit correcting means for inverting the most significant bit of the output of the exponent subtracting means, and simultaneously performing the subtraction of the exponent value of the two floating point data and the deviation correction, the same as the dividend and the divisor. An apparatus for dividing floating-point data, characterized in that the exponent part of the quotient of the floating-point format is obtained. 41. An exponent subtraction means for obtaining a value smaller by 1 than a value obtained by subtracting the exponent part of the divisor in the same floating-point format from the exponent part of the dividend in the floating-point format having a deviated exponent part,
The most significant bit correction means for inverting the most significant bit of the output of the exponent subtraction means, and the mantissa part of the dividend for the output of the exponent subtraction means having the most significant bit inverted by the most significant bit correction means. Normalized exponential correction means for adding / subtracting a number equal to the number of shift bits for normalizing the quotient obtained by dividing the mantissa part of the divisor, carry output indicating the carry from the most significant bit of the exponent subtracting means, and the normal An exception detection unit for detecting upper and lower overflows of the quotient based on the output from the variable exponent correction unit, and the subtraction of the exponent value of the two floating-point data and the deviation correction are simultaneously performed, and the dividend and Similar to the divisor, the exponent part of the quotient in the floating-point format is obtained, and the upper and lower overflows of the quotient from the predetermined arithmetic precision after normalizing the mantissa part of the quotient are detected. Divider unit of floating-point data, wherein the door.