JPH08237133A - Variable rate compressor and variable rate expander - Google Patents

Abstract

PURPOSE: To reduce the processing time required for the recording. CONSTITUTION: A video peak rate analysis circuit 22, an audio peak rate analysis circuit 23 and a data peak rate analysis circuit 24 analyze each peak rate of video, audio and other data respectively. A system controller 25 controls a compression rate of compression circuits 27-29 based on a result of peak rate analysis. Thus, the compression circuits 27-29 encode and provide an output of the,video, audio and other data so that an output rate of a multiplexer 30 is a rate below a recording and reproduction rate of a disk 33. The peak rate is controlled without requiring tentative coding.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable rate compression device and a variable rate expansion device suitable for a recording disk production system for recording video data, audio data and the like on a disk medium.

[0002]

2. Description of the Related Art In recent years, digitization of image information has been studied due to demands for higher image quality. Since the amount of data becomes huge when an image is digitized, it is necessary to compress the data for recording or transmission. As a compression method,
DCT with high compression rate and little deterioration of image quality due to compression
High-efficiency coding methods that adopt transform coding such as (discrete cosine transform) have become mainstream. In the high-efficiency coding method, the input image signal is divided into blocks of, for example, 8 pixels × pixels, and DCT processing is performed in units of this block (DCT block).

According to this standard, not only compression by DCT (intraframe compression) is performed within one frame, but also interframe compression for reducing redundancy in the time axis direction by utilizing correlation between frames is adopted. The inter-frame compression is to further reduce the bit rate by utilizing the property that a general moving image is very similar to the preceding and following frames and obtaining the difference between the preceding and following frames and performing the DCT process on the difference value. . In particular, motion-compensated interframe predictive coding that reduces the prediction error by predicting the motion of an image and obtaining the interframe difference is effective.

Regarding such a compression device, for example, the document IEEE Trans. On Broadcasting Vol. 36 No. 4 DEC 1990
Woo Paik: “Digital compatible HD-TV Broadcast
system ". FIG. 24 is a block diagram showing the compression device described in this document.

Image data is input to the input terminal 1.
This image data is input after the video signal is framed and divided into, for example, two-dimensional data of horizontal 8 pixels × vertical 8 lines (hereinafter referred to as block data). The image data is supplied to the motion evaluation circuit 5,
It is also supplied to the DCT circuit 3 via the subtraction circuit 2.

Now, it is assumed that the intra-frame compression mode is designated. In this case, the switch 8 is off. A signal in which one block is composed of 8 × 8 pixels is input to the DCT circuit 3, and the DCT circuit 3 is an 8 × 8 two-dimensional D
An input signal is converted from a spatial coordinate axis component into a frequency component by CT processing. This makes it possible to reduce spatial correlation components. That is, the output (transformation coefficient) of the DCT circuit 3 is given to the quantization circuit 4, and the quantization circuit 4 requantizes the transformation coefficient with a predetermined quantization width to reduce the redundancy of the signal of one block. To do. The quantization circuit 4 performs quantization by using a table based on the generated code amount, the assigned set code amount, and the like among a plurality of quantization tables having different quantization widths (quantization levels), The generation rate of the digitized output can be controlled.

The quantized data from the quantization circuit 4 is zigzag-scanned from the low band to the high band in the horizontal and vertical directions for each block and is given to the variable length coding circuit 5. The variable length coding circuit 5 two-dimensionally Huffman-codes the quantized output based on a predetermined variable-length code table, for example, a Huffman code table, and outputs a coded output. In the two-dimensional Huffman coding, a pair of data of the number of zero quantized outputs (zero run length) and the number of bits of non-zero coefficient is coded. As a result, short bits are assigned to data having a high appearance probability and long bits are assigned to data having a low appearance probability, thereby further reducing the transmission amount.

The coded output from the variable length coding circuit 5 is given to a first-in first-out circuit (hereinafter referred to as a FIFO) 6, and the FIFO 6 outputs the coded output inputted from an output terminal 10 at a predetermined speed. . The generation rate of the encoded output from the variable length encoding circuit 5 is a variable rate, and the FIFO 6 absorbs the difference between the generation rate of the encoded output and the transmission rate of the transmission path. The output from the output terminal 10 is supplied to a transmission line (not shown) after a control signal, voice data, synchronization data (SYNC), etc. are multiplexed by a multiplexer (not shown).

On the other hand, in the interframe compression coding mode, the switch 8 is turned on. The block data from the input terminal 1 is given to the subtraction circuit 2, and the subtraction circuit 2 calculates the difference for each pixel data between the block of the current frame and the block of the motion-compensated reference image (hereinafter referred to as the reference block). The prediction error is output to the DCT circuit 3. In this case, the DCT circuit 3 will perform DCT processing on the difference data.

The reference block is obtained by decoding the quantized output. That is, the output of the quantization circuit 4 is also given to the inverse quantization circuit 10. The inverse quantization circuit 10 inversely quantizes the quantized output, and the inverse DCT circuit 11 performs inverse DCT processing to restore the original video signal. Since the output of the subtraction circuit 2 is the difference information, the output of the inverse DCT circuit 11 is also the difference information. The output of the inverse DCT circuit 11 is given to the adder 12. The output of the adder 12 is fed back to the adder 12 via the frame delay circuit 13, the motion compensation circuit 14 and the switch 15, and the adder 12 adds the difference data to the data of the reference block from the motion compensation circuit 14. The block data (local decoded data) of the current frame is reproduced and output to the frame delay circuit 13. The frame delay circuit 13 stores the block data from the adder 15 in association with the screen position.

The frame delay circuit 13 delays the local decoded data from the adder 12 for, for example, one frame period and outputs it to the motion compensation circuit 14 and the motion evaluation circuit 9. The motion evaluation circuit 9 detects a motion vector from the block data of the current frame from the input terminal 1 and the block data of the reference image from the frame delay circuit 13 and outputs it to the motion compensation circuit 14. The motion compensation circuit 14 corrects the blocking position of the local decoded data of one frame before stored in the frame delay circuit 13 by the motion vector and outputs it to the subtraction circuit 2 as a motion-compensated reference block. In this way, the motion-compensated data of one frame before is supplied to the subtraction circuit 2 as a reference block, and the DCT processing is performed on the prediction error from the subtraction circuit 2. The motion vector from the motion evaluation circuit 9 is also given to the variable length coding circuit 5 and variable length coded by the variable length coding circuit 5 based on a predetermined variable length code table and output.

The switch 15 is interlocked with the switch 8. That is, in the intra-frame compression mode, the switch 8,
15 is turned off and the switches 8 and 15 are turned on in the inter-frame compression mode to supply the block data of the previous frame to the adder 12.

A reference image is required to decode a frame encoded in the interframe compression mode (hereinafter referred to as interframe compression frame). That is, the original image cannot be restored only with the inter-frame compressed frame. For this reason, a predetermined frame unit (hereinafter, GOP
That is, random access is enabled by creating an intra-frame compressed frame by intra-frame compression. It should be noted that even in the inter-frame compressed frame, a block is created by intra-frame compression in a predetermined block unit.

By the way, the transmission rate must be taken into consideration when recording and transmitting the encoded output. For example, when the encoded output is recorded by the VTR, the recording rate of the digital VTR cannot usually be changed, so that the transmission rate of the encoded output needs to be fixed. As described above, the generation rate of the encoded output is variable, but by using the FIFO 6 to absorb the difference between the predetermined fixed rate and the generation rate of the encoded output, it is possible to output at the fixed rate. is there.

However, since the capacity of the FIFO 6 is limited, in order to prevent the FIFO 6 from overflowing or underflowing, the quantization width is set based on the data amount of the FIFO 6, and the generation rate of the encoded output is set. Is adjusted. That is, for image data such as an intra-frame compressed frame (hereinafter referred to as an I picture) whose generated code amount is likely to be large, it is necessary to coarsen the quantization width and increase the compression rate. For this reason,
The image quality of the I picture is deteriorated. Similarly, when compressing an image at the time of a scene change and an image with a fine pattern, the generated code amount tends to be large, so the compression rate must be increased and the image quality deteriorates.

On the other hand, when the encoded output is recorded on the disk medium, the transmission rate can be variable. That is, in the reproducing apparatus for a disk medium, the pickup can move in the direction traversing the recording track, that is, in the radial direction of the disk, regardless of the moving speed during normal reproduction (hereinafter referred to as kicking). Therefore, the output rate of the encoded output is set to a rate equal to or lower than the maximum rate that can be reproduced by the reproducing apparatus of the disk medium,
When the encoded output is recorded at a rate lower than the maximum rate, the pickup can be kicked to reproduce an unnecessary track so that the encoded output at a low rate can be reproduced. Therefore, when the encoded output is recorded on the disk medium, the generation rate of each picture and the FI
The encoded output can be supplied to the recording device of the disk medium at a variable rate based on the capacity of the FO6.

However, the recording capacity of the disk medium is fixed. When a predetermined program is encoded and recorded, if recording is performed at a fixed rate, the recording time is determined based on the recording capacity of the disk medium and the fixed rate. On the other hand, when recording is performed at a variable rate, the recording time is not determined in advance. Therefore, when the image data of a predetermined program is encoded and recorded at a variable rate, a predetermined quantization coefficient is determined and once encoded to obtain a generated code amount, based on the generated code amount and the recording capacity of the disk medium. Then, the quantization coefficient is set again so that the generated code amount of the predetermined program falls within the recording capacity of the disk medium. That is, in this case, there is a problem that the encoding process needs to be performed twice.

When reproducing a disc,
When the rotational speed of the disk is increased to increase the transmission rate, the pickup control becomes unstable, which makes it difficult to perform normal kick processing.

[0019]

As described above, conventionally, when compression is performed with a variable transmission rate, the encoding process is performed twice in order to keep the code amount within a predetermined set code amount. There is a problem in that it needs to be performed, a processing time that is twice as long as the processing in real time is required, and there is a problem that the kick processing is unstable.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a variable rate compression device capable of significantly shortening the processing time.

Another object of the present invention is to provide a variable rate compression device capable of stable kicking when reproducing a disk medium in which encoded output is recorded at a variable rate.

It is another object of the present invention to provide a variable rate decompression device capable of stable kicking when reproducing a disk medium in which encoded output is recorded at a variable rate.

[Constitution of Invention]

According to a first aspect of the present invention, there is provided a variable rate compression apparatus which encodes input data and outputs it at a variable rate, and the input data in the encoding means. A rate analysis unit that analyzes the output rate of the encoding unit before the encoding process and outputs the estimated rate by approximating the code amount in the case of encoding, and the estimated rate is the encoding rate. And a peak rate control means for suppressing the output rate of the encoded output below the peak rate by increasing the compression rate of the encoding means when the peak rate allowed for the output of the means is exceeded. According to a ninth aspect of the present invention, there is provided a variable rate compression device, wherein an encoding unit that encodes input data and outputs the input data at a variable rate, and the input data to the encoding unit. Rate analysis means for analyzing the output rate of the encoding means before the encoding processing and outputting it as an approximate rate by approximating the code amount in the case where the approximate rate is output by the encoding means. When the peak rate allowed by the above is exceeded, the compression rate of the encoding means is increased to reduce the output rate of the encoded output to a peak rate or less, and the output of the encoding means. Storage means for storing and re-encoding means for re-encoding and outputting a part of the input data or the data stored in the storage means,
A variable rate compression apparatus according to claim 11 of the present invention comprises an encoding means for encoding input data and outputting the encoded data at a variable rate, and a code amount when the input data is encoded by the encoding means. By doing so, the output rate of the encoding means is analyzed before the encoding processing and output as an approximate rate, and the approximate rate exceeds a peak rate allowed for the output of the encoding means. Includes a peak rate control means for increasing the compression rate of the encoding means to reduce the output rate of the encoded output to a peak rate or less, an output rate of the encoding means and an output of the encoding means. The compression rate of the encoding means is changed based on the difference from the average rate based on the allowable total code quantity so that the total code quantity of the output of the encoding means corresponds to the allowable total code quantity. The variable rate compression apparatus according to claim 13 of the present invention comprises an encoding means for encoding input data and outputting the encoded data at a variable rate, and the input data as described above. Rate analysis means for analyzing the output rate of the encoding means before the encoding processing by estimating the code amount when encoded by the encoding means and outputting as an estimated rate; Peak rate control means for suppressing the output rate of the encoded output to a peak rate or less by increasing the compression rate of the encoding means when the peak rate allowed for the output of the means is exceeded, and the encoding means. The encoding rate is changed by changing the compression rate of the encoding means based on the difference between the output rate of the encoding means and the average rate based on the allowable total code amount allowed for the output of the encoding means. Average rate control means for making the total code amount of the output of the stage correspond to the allowable total code amount, storage means for storing the output of the encoding means, and a part of the input data or the data stored in the storage means. The variable rate compression apparatus according to claim 14 of the present invention includes an encoding means for encoding a plurality of types of data, and an encoding means for encoding the plurality of types of data. Multiplexing means for multiplexing the encoded outputs of the plurality of types of data from the encoding means and outputting them at a variable rate; and estimating the code amount when the plurality of types of data are encoded by the encoding means, respectively. When the sum of the code amount approximating means for outputting an approximate value and each approximate value per predetermined period exceeds the maximum permissible code amount per predetermined period allowed for the output of the multiplexing means, the plurality of types De By controlling each compression rate for the data based on the type of the data, the generated code amount suppressing means for suppressing the sum of the output code amounts of the encoded outputs per the predetermined period to be equal to or less than the allowable maximum code amount. According to a seventeenth aspect of the present invention, there is provided a variable rate compression device according to a seventeenth aspect of the present invention, wherein the variable rate compression device encodes input data and outputs the encoded data at a variable rate.
The variable rate compression apparatus according to claim 18 of the present invention is provided with a pointer adding means for adding a pointer indicating the generated code amount for each predetermined time to the output of the encoded output and outputting the same. Encoding means for encoding and outputting at a variable rate, and when recording the output of this encoded output on a disc medium, kick information of a pickup for reproducing the disc medium is set to the output rate of the encoding means. The variable rate decompression device according to claim 19 of the present invention is provided with kick information adding means for generating and adding the kick information created based on the kick information to the output of the encoding means. Reproducing means for reproducing by a pickup a disc on which an encoded output to which a pointer indicating the code amount of is recorded at a variable rate, and an output of this reproducing means are held. Recorded on the disc by kicking the pickup on the basis of the decoder buffer for outputting the output, the pointer detecting means for detecting the pointer from the reproduction signal of the reproducing means, and the pointer detected by the pointer detecting means. It is provided with a pickup control means for enabling reproduction at a reproduction rate corresponding to the recording rate of the encoded output.

[0024]

According to the first aspect of the present invention, the input data is rate-analyzed by the rate-analyzing means before being encoded by the encoding means to obtain an approximate rate. The peak rate control means sets the compression rate of the encoding means to a large value when the estimated rate exceeds the peak rate allowed for the output of the encoding means. The encoding means compresses the input data at the compression rate set by the peak rate control means and outputs it. As a result, even if the peak rate of the coded output is limited, the coded output having the peak rate or less is obtained in the first coding process without performing temporary coding.

In the ninth aspect of the present invention, the peak rate control means obtains the coded output with the peak rate limited from the coding means. The storage means stores the output of the encoding means. For example, when the code amount of the data stored in the storage means is larger than the predetermined set code amount,
The input data or the data stored in the storage means is re-encoded by the re-encoding means. In this way, an encoded output with an appropriate compression rate is obtained.

In the eleventh aspect of the present invention, the peak rate control means obtains the coded output with the peak rate limited from the coding means. Further, the average rate control means changes the compression rate of the encoding means on the basis of the difference between the output rate of the encoding means and the average rate based on the allowable total code amount allowed for the output of the encoding means. The total code amount of the output of the conversion means is made to correspond to the allowable total code amount. As a result, a coded output corresponding to the permissible total code amount is obtained in the first coding process without temporary coding.

In the thirteenth aspect of the present invention, the peak rate control means obtains the coded output with the peak rate limited from the coding means, and the average rate control means gives the total code corresponding to the allowable total code amount. A coded output of the quantity is obtained. Further, the re-encoding means re-encodes the input data or a part of the data stored in the storage means to obtain an encoded output with an appropriate compression rate.

In the fourteenth aspect of the present invention, a plurality of types of data are encoded by the encoding means, then multiplexed by the multiplexing means and output at a variable rate. The code amount approximating means roughly estimates the code amount for each type of data before encoding, and the generated code amount suppressing means compresses the sum of the estimated values of the respective code amounts so that the sum is equal to or less than the maximum allowable code amount. To control.

In the seventeenth aspect of the present invention, the pointer adding means adds a pointer indicating the generated code amount at every predetermined time to the encoded output output at the variable rate.

In the eighteenth aspect of the present invention, kick information is added to the encoded output. By using this kick information, a stable kick can be performed on the reproducing side.

In the nineteenth aspect of the present invention, the encoded output to which the pointer is added is reproduced from the disc by the reproducing means. The pointer detection means detects the pointer from the reproduction signal, and the pickup control means controls the kick of the pickup based on the detected pointer. It is possible to detect the margin of the decoder buffer by the pointer, and the stability of the kick processing of the pickup is improved.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a recording disk production system incorporating a variable rate compression device according to an embodiment of the present invention.

FIG. 1 shows the basic structure of a variable rate compression apparatus applied to a recording disk production system for recording on a digital video disk.

In FIG. 1, the studio equipment 21 creates video data, audio data and other data and gives them to the video encoder 50, the audio encoder 91 and the data encoder 120, respectively. Note that the video data includes luminance data Y and color difference data Pb and Pr, and the processing can be divided into a luminance system and a color difference system, but in FIG. 1, one system is used for simplification of the description. As described.

The video peak rate analysis circuit 22 of the video encoder 50 analyzes the generation rate of the coded output when the video data is coded in a predetermined time unit, for example, in 1 GOP unit, and the analysis result is sent to the system controller 25. It is designed to output. The audio peak rate analysis circuit 23 of the audio encoder 91 analyzes the generation rate of the encoded output when the audio data is encoded, for example, in a time unit corresponding to 1 GOP, and outputs the analysis result to the system controller 25. It is supposed to do. The data peak rate analysis circuit 24 of the data encoder 120 analyzes the generation rate of the encoded output when other data is encoded, for example, in a time unit corresponding to 1 GOP, and outputs the analysis result to the system controller 25. It has become.

The system controller 25 receives the analysis results from the peak rate analysis circuits 22, 23 and 24 and encodes the peak rate of the encoded output (hereinafter, referred to as
Video peak rate), peak rate of encoded output when audio data is encoded (hereinafter referred to as audio peak rate), and peak rate of encoded output when other data is encoded (hereinafter referred to as data peak rate) That is) is calculated.

Video peak rate analysis circuit 22, audio peak rate analysis circuit 23 and data peak rate analysis circuit 24
Delays video data, audio data and other data by a predetermined time (1 GOP period) required for peak rate analysis, and compresses the video compression circuit 27 and the audio compression circuit 28, respectively.
And to the data compression circuit 29. The video compression circuit 27
The input video data is DCT processed and then quantized to reduce the data amount. Further, the video compression circuit 27 performs variable length coding on the quantized output to further reduce the data amount. Also,
The voice compression circuit 28 compresses voice data using subband coding, and the data compression circuit 29 compresses other data. The encoded outputs from the compression circuits 27 to 29 are supplied to the multiplexer 30 and also to the system controller 25. The generation rate of the encoded output from the compression circuits 27 to 29 is a variable rate.

By the way, in the disk medium, the maximum recordable recording rate and reproduction rate (hereinafter referred to as the disk peak rate) are uniquely determined by the rotational speed of the disk. It is necessary to set such that the added value of the video peak rate, the audio peak rate, and the data peak rate at a predetermined timing does not exceed the disk peak rate.

For this reason, the system controller 25 changes the compression ratios of the video compression circuit 27, the audio compression circuit 28 and the data compression circuit 29 based on the approximate values of the video peak rate, the audio peak rate and the data peak rate. Then, the generation rate is controlled. For example, video compression circuit
The system controller 25 controls the quantization coefficient of 27.

Further, since the recording capacity of the disk medium is fixed, it is necessary to make the code amount of all recording data correspond to the recording capacity of the disk medium. Therefore, the system control device 25 cumulatively adds the code amounts of the encoded outputs from the compression circuits 27 to 29, and the compression circuits 27 to 29 so that the total generated code amount corresponds to the recording capacity based on the cumulative addition result. It is designed to control a compression ratio of 29.

The multiplexer 30 multiplexes the encoded outputs from the compression circuits 27 to 29 and outputs the multiplexed outputs to the recording processing circuit 31. The output of the multiplexer 30 also has a variable rate. The recording processing circuit 31 performs predetermined recording processing, for example, conversion processing of encoded output into recording format, addition processing of error correction code, modulation processing suitable for recording, etc., and supplies recording data to the cutting device 32. To do. The cutting device 32 optically modulates the recorded data and cuts the original disc 33. The servo circuit 35 controls the rotation of the motor 34, and the motor 34 rotates the original disk 33 at a constant speed for recording.

Next, each constituent block will be described in more detail.

FIG. 2 is a block diagram showing a concrete configuration of the studio equipment 21 in FIG. 1. A VTR (video tape recorder) 42 stores video data, an audio recorder 43 stores audio data, and data production. The unit 44 stores other data. These VTR 42, voice recorder 43, and data production unit 44 are controlled by the studio controller 41,
The house sync is supplied from the house sync generator 45 to be externally synchronized. As the house sync, a video sync signal, a black burst VD (vertical sync signal), an HD (horizontal sync signal) or the like is used. By using the house sync, it is possible to perform phase matching per frame.

The studio controller 41 is controlled by the operation unit 26, and controls the VTR 42, the audio recorder 43, and the data production unit 44. The studio controller 41 also controls the house sync generator 45 and a reference time generation circuit 81 (see FIG. 3) described later. Further, a house sync is similarly supplied to the video encoder 50, the audio encoder 91, and the data encoder 120 to synchronize the entire system.

The operation unit 26 is a GUI (Graphical User Interface).
face) is adopted. The GUI is an interface with the user, and inputs designated information necessary for encoding and displays the encoding result.

Video data from the VTR 42 is, for example, NTS.
It is composed of luminance data Y and color difference data Pb and Pr of the C system or PAL system, and is supplied to the video peak rate analysis circuit 22. The audio recorder 43 is composed of, for example, a D1VTR or a DAT (digital audio tape recorder) and the like, and converts audio data into an audio peak rate analysis circuit.
Supply to 23. Further, as other data from the data production unit 44, for example, subtitle data, text data,
There are caption (U.S. Caption) data, sub-picture data, etc., which are supplied to the data peak rate analysis circuit 24.

FIG. 3 is a block diagram showing a video encoder 50 constituted by the video peak rate analysis circuit 22 and the video compression circuit 27.

The video data is the video peak rate analysis circuit 22.
Is supplied to the frame memory 51. The frame memory 51 frames the input video data into a pre-filter 52.
The pre-filter 52 band-limits the video data and outputs it to the noise reduction circuit (hereinafter referred to as NR) 53. The NR 53 removes noise from the video data and outputs it to the frame memory 54, and also outputs it to the activity measuring circuit 55 and the scene change detecting circuit 56.

The activity measuring circuit 55 outputs the pixel correlation of the video data as an activity in a predetermined time unit. For example, the activity measuring circuit 55 is 1 GO
The activity is calculated from the squared error of the pixel value in P units. The activity shows the fineness of the design,
The activity can predict the code amount when encoded. The activity from the activity measuring circuit 55 is transmitted via the terminal 75 to the system controller 25.
It is supplied to the video code amount control circuit 58 constituting (FIG. 1).

The scene change detection circuit 56 has a frame memory (not shown), detects the scene change by comparing the images before and after, and outputs the scene change flag via the terminal 57 to the video code amount control circuit 58. Output to. The frame memory 54 delays the video data by, for example, 1 GOP period for detecting the video peak rate, and supplies the delayed video data to the shuffling circuit 59 of the video compression circuit 27. The outputs of the activity measurement circuit 55 and the scene change detection circuit 56 are the system code amount distribution circuit 152 (see FIG. 7) of the system controller 25 described later.
Is also being supplied to.

The shuffling circuit 59 shuffles the video data and outputs it to the scan conversion macroblocking circuit 60 and the motion detection circuit 61. The motion detection circuit 61 has a frame memory (not shown), detects motion of an image, and outputs a motion vector to the motion compensation circuit 70. In this embodiment, the motion vector is also supplied to the video code amount control circuit 58 and the system code amount distribution circuit 152 so that it can be used for peak rate analysis.

As described above, the orthogonal transformation is performed in block units (for example, 8 pixels × 8 lines). By the way, in the orthogonal transformation, the luminance signal and the color difference signal are processed separately. In this case, the size of the luminance block is different from that of the color difference block due to the difference in sampling clocks between the color difference signal and the luminance signal. For example, if the sampling clock of the color difference signal has a frequency of 1/4 of the sampling clock of the luminance signal, four luminance blocks and one color difference block have the same size. In this case, the encoding is performed in macroblock units, which is composed of four luminance blocks and one color difference block each. The scan conversion macroblock conversion circuit 60 converts the input video data into macroblocks and outputs the macroblocks to the subtractor 62 in block units.

The subtractor 62 receives the motion-compensated image data of the reference block from the switch 71, and in the inter-frame compression mode, the difference between the block data from the scan conversion macroblocking circuit 60 and the reference block data is a prediction error. Is supplied to the DCT circuit 63. In the intra-frame compression mode, the switch 71 is turned off, and the subtractor 62 outputs the output of the scan conversion macroblocking circuit 60 as it is to the DCT circuit.
Give to 63. The DCT circuit 63 performs DCT processing on the output of the subtractor 62 and outputs it to the quantization circuit 64. The quantization coefficient of the quantization circuit 64 is controlled by the video code amount control circuit 58, and the DCT conversion coefficient is quantized to generate a variable length coding circuit 65 and an inverse quantization circuit 66.
Output to. The variable length coding circuit 65 performs variable length coding on the quantized output from the quantization circuit 64 and outputs it to the multiplexer 73.

The inverse quantization circuit 66 inversely quantizes the quantized output, and the inverse DCT circuit 67 inversely DCT-processes the inversely quantized output to restore the pixel data before the DCT processing, and supplies the pixel data to the adder 68. The output of the adder 68 is fed back via the image memory 69, the motion compensation circuit 70 and the switch 71, and the adder 68 is inverse D
The motion compensated reference image data is added to the prediction error from the CT circuit 67 to restore the current frame data (local decoded data) and output to the image memory 69.

The image memory 69 can store reference image data for two frames, and outputs the stored reference image data to the motion compensation circuit 70. The motion compensation circuit 70 determines the blocking position of the reference image data based on the motion vector, and outputs the motion-compensated reference block data to the subtractor 62 and the adder 68 via the switch 71.

The overhead data generation circuit 74 generates information about the quantized coefficient used by the quantization circuit 64, information about the motion vector used for the inter-frame predictive coding, and outputs it as overhead data to the multiplexer 73. The multiplexer 73 adds the overhead data to the output of the variable length coding circuit 65 and stores it in the storage means 76, 7
7, output to the editing processing means 78 and the output terminal 79. The encoded output from the output terminal 79 is controlled by the system controller 25 in order to control the code amount based on the total generated code amount.
It is adapted to be supplied to an actual generated code amount for a predetermined time and a predetermined time storage means occupancy calculation circuit (see FIG. 7) 153 described later.

The output of the multiplexer 73 is the storage means 76, 77.
It is supplied to the multiplexer 30 via. In the multiplexer 30, as described above, the output of the video encoder 50, the output of the audio encoder 91 and the output of the data encoder 120 are combined. Therefore, it is necessary to manage the time of the entire system including each encoder.

Next, the time management will be described.

The reference time generation circuit 81 generates a time code indicating a reference time which serves as a time reference for the entire system. The reference time is synchronized with the house sync of the house sync generator 45. The time code is hours, minutes,
An SMPTE time code specifying seconds, frames and fields is used. VTR 42, audio recorder in which video data, audio data and other data are recorded respectively
The time code (source time code) for each data is also recorded on the source tape of 43 and the data production unit 44. The time code is registered for each scene, and the time code can be grasped even when the scenes are connected to each other to form a complete packet state.

When operating the video encoder 50, the audio encoder 91 and the data encoder 120 at the same time, the operating section 26 specifies the synchronization relationship between the time codes of the source video data, the source audio data and the other source data. , VTR 42, audio recorder 43, and data production section 44 are arranged to be in phase. As a result, the time relationship between each data can be associated.

The video encoder 50, the audio encoder 91 and the data encoder 120 perform time code conversion / correlation processing to convert the source time code into an encoder time code. That is, the reference time from the reference time generation circuit 81 is supplied to the video time information generation circuits 83 and 84 of the video encoder 50 via the terminals 82a and 82b. The video time information creation circuits 83 and 84 create encoder video time codes based on the reference time and store them in the storage means 7 respectively.
It outputs to 6 and 77.

For example, when the source video time code, the source audio time code and the source data time code occur asynchronously, the video time information creating circuit 83,
Reference numeral 84 creates an encoder video time code so as to associate the encoder time codes between the encoded outputs of the video data, the audio data and other data. For example, the video time information creation circuits 83 and 84 use the source video time code as it is as the encoder video time code, and use the audio encoder 91 and the data encoder 12 which will be described later.
The source video time code is also used as the encoder audio time code and the encoder data time code in the 0 audio time information generating circuit 108 (see FIG. 4) and the data time information generating circuit 128 (see FIG. 5). The video time information creation circuits 83 and 84 output the encoder video time code obtained by the time code conversion / association processing to the multiplexer 30.

On the other hand, the video encoder 50 and the audio encoder
When the 91 and the data encoder 120 are operated separately, the operation unit 26 is designed to specify the synchronization relationship between the source video time code, the source audio time code, and the source data time code. Then, the video encoder 50, the audio encoder 91, and the data encoder 120
Associates each source time code with each encoder time code and associates them with each encoded output. That is, the video time information creation circuits 83 and 84 associate the source video time code with the encoder video time code and associate them with the coded output of the video.

The encoder video time codes from the video time information creating circuits 83 and 84 are given to the storage means 76 and 77, respectively. The storage means 76 and 77 store the video encoded output given from the multiplexer 73, and perform reading while associating the source time code and the encoder time code corresponding to the stored encoded output. The storage means 76 functions as an encoder buffer, temporarily holds the input encoded output and outputs it to the multiplexer 30. As a result, the storage unit 76 smoothes the generated code amount of the encoded output of the video encoder 50 and adjusts the multiplexing timing of the encoded output of the multiplexer 30. By adjusting the multiplexing timing of the multiplexer 30,
The generated code amount of video data, audio data and other data can be smoothed.

On the other hand, the storage means 76 stores the data for editing and processing the encoded output, and is composed of, for example, a hard disk device or the like and stores a predetermined program.
The edit processing means 78 is given a signal based on the operation of the operator via the terminal 85, edits the encoded output read from the storage means 77, and outputs the edited output to the storage means 77 and the video time information creation circuit 84. The editing / processing means 78 also corrects the overhead data based on the editing / processing result. The storage unit 76 outputs the edited and encoded output to the multiplexer 30 while associating the source time with the encoding time. In the time code conversion / correspondence process, the drop frame and the full frame of the source tape are designated to correspond each time code of the video data, the audio data, and the other data.

FIG. 4 is a block diagram showing a specific structure of the audio encoder 91 which is composed of the audio peak rate analysis circuit 23 and the audio compression circuit 28.

The audio data input to the audio peak rate analysis circuit 23 of the audio encoder 91 is, for example, 10 Hz-
An audio signal having a voice signal band of about 20 kHz is sampled and digitized at a sampling frequency such as 48 kHz. The voice peak rate analysis circuit 23 includes a voice delay memory 92, a vowel / consonant / background sound detection circuit 93, and a voice code amount approximate determination circuit 94. The audio peak rate analysis circuit 23 obtains an approximate value of the audio generated code amount for a predetermined period (for example, a period corresponding to one GOP period of video), and delays the input audio data for a period necessary for the estimation of the code amount. And supplies it to the audio compression circuit 28.

The voice compression circuit 28 employs coding which reduces the amount of generated code by reducing the codes of the background sound and consonant parts. Therefore, the approximate value of the generated code amount can be obtained by detecting the vowels, consonants, and background sounds of the voice data. Vowel, consonant, background sound detection circuit 93
Detects vowels, consonants, and background sounds from the input voice data by using the periodicity of the signal. That is, the vowel, consonant, and background sound detection circuit 93 determines that a component having periodicity is a vowel, determines that a component having an impulse property and no periodicity is a consonant, and approximates random white noise. The components are judged as background sounds, and the detection result of each component is output to the speech code amount rough decision circuit 94.

The voice code amount estimation determining circuit 94 estimates the code amount of the encoded output in the voice compression circuit 28 based on the detection result of the vowel, consonant and background sound detecting circuit 93, and the estimated value is the system controller 25. It is output to the voice code amount control circuit 111 and the system code amount distribution circuit 152. Voice delay memory 92
The audio data is delayed by the period necessary for the calculation of the approximate value of the audio code amount and is output to the audio compression circuit 28.

The voice compression circuit 28 performs encoding using subband encoding. The sub-band coding is divided into a plurality of frequency bands for each predetermined number of samples (for example, 1536 samples) (audio frame), and the uneven distribution of power in each band is used to perform coding suitable for each band. It is something to do. The audio data input to the audio compression circuit 28 is, for example, 16-bit linear quantization, and the subband analysis filter bank 96 of the audio compression circuit 28 divides the input audio data into subband signals of 32 bands. To do. The subband signal is given to the linear quantizer 102, and the linear quantizer 102
102 reduces the code amount by allocating and quantizing bits with the allocated number of bits set for each band.

The auditory characteristic is used for the bit allocation of the linear quantizer 102. That is, a perceptible threshold value is obtained for each band, and the number of allocated bits is reduced as the perceptible range is narrower. Therefore, the audio data is also given to the fast Fourier transform circuit (hereinafter referred to as FFT) 97. The FFT 97 converts the input voice data into frequency components by a fast Fourier transform process and outputs the frequency components to the psychoacoustic model analysis circuit 100.

The scale factor extraction circuit 99 also calculates a scale factor for each subband signal from the subband analysis filter bank 96. The scale factor indicates a scaling factor for the normalized maximum amplitude. The calculated scale factor is output to the psychoacoustic model analysis circuit 100. The psychoacoustic model analysis circuit 100 creates a psychoacoustic model for determining the number of allocated bits in each band from the scale factor of each frequency component of the voice data, and outputs it to the dynamic bit allocation circuit 101. Dynamic bit allocation circuit
101 determines the number of bits to be allocated to each subband signal based on the psychoacoustic model and outputs the bit allocation information to the linear quantizer 102. This reduces the uneven distribution of signal energy in each subband, reduces the dynamic range, and makes it possible to allocate bits according to the energy of each subband.

The linear quantizer 102 receives the subband signal from the subband analysis filter bank 96, quantizes the subband signal with the number of bits based on the bit allocation information, and outputs the quantized signal to the bit compression circuit 103. Bit compression circuit 103
Bit-compresses the quantized output and outputs it to the bitstream creation circuit 105. In the present embodiment, the bit compression circuit 103 is so controlled that the voice code amount control circuit 111 controls the compression rate. If a high compression ratio is set,
The bit compression circuit 103 lowers the peak rates of the background sound and the consonant parts, for example.

On the other hand, the scale factor and bit allocation information are also supplied to the side information coding circuit 104. The side information encoding circuit 104 encodes the scale factor and bit allocation information as a header or auxiliary information and outputs it to the bitstream creation circuit 105. The bitstream creation circuit 105 creates an audio bitstream by multiplexing the output of the bit compression circuit 103 and the output of the side information coding circuit 104, and outputs it to the storage means 106 and the terminal 107. The audio bit stream output via the terminal 107 is stored in the circuit occupancy calculation circuit 153 for a predetermined time and a predetermined time, which will be described later, of the system controller 25 in order to control the code amount based on the total generated code amount. It is being supplied.

A time code indicating the reference time is given from the reference time generating circuit 81 to the terminal 82c. The voice time information creation circuit 108 creates an encoder voice time code based on this time code and outputs it to the storage means 106. The storage means 106 stores the audio bit stream supplied from the bit stream creating circuit 105, and reads it while associating the source audio time code and the encoder audio time code corresponding to the stored audio bit stream. The storage means 106
By adjusting the output timing,
The generated code amount of voice data and other data can be smoothed.

As described above, the audio data is processed with a predetermined number of audio samples (for example, 1536) as one audio frame. Therefore, in the audio timing management, the number of audio samples corresponding to the video sync signal position (Vsync) and the audio frame number of the audio are specified together with the encoder audio time code. These values are given to the voice time information generating circuit 108 and output to the multiplexer 30.

In this embodiment, the voice peak rate is analyzed by estimating the generated code amount. If the generated code amount can be estimated, the vowel, consonant, and background sound detection circuits 93 can be detected. You don't have to use it. For example, the FFT 97 in the voice compression circuit 28 can also roughly estimate the generated code amount, which is particularly effective in the method of reducing the generated code amount according to the frequency of the voice.

FIG. 5 shows a data encoder composed of a data peak rate analysis circuit 24 and a data compression circuit 29.
FIG. 12 is a block diagram showing a specific configuration of 120.

The other data input to the data peak rate analysis circuit 24 of the data encoder 120 is, for example, caption data, text data, video data for sub video, or the like. The data peak rate analysis circuit 24 comprises a data delay memory 122, a data content detection circuit 121, and a data code amount rough decision circuit 123.

The subtitle data does not always exist and is generated only at the timing corresponding to the dialogue. Therefore, the data content detection circuit 121 detects the presence or absence of the content of other input data, and outputs the detection result to the data code amount approximate determination circuit 123. Data code amount approximate determination circuit
123 roughly estimates the code amount of the encoded output in the data compression circuit 29 based on the detection result of the presence / absence of the content, and outputs the estimated value to the data code amount control circuit 126 and the system code amount distribution circuit 152 of the system controller 25. Output. The data delay memory 122 delays other data for a period required for the calculation of the approximate value of the data code amount and outputs it to the data compression circuit 29.

The data compressor 125 of the data compression circuit 29 is
The compression rate is controlled by the data code amount control circuit 126, and the input data is encoded and output to the storage means 127 and the terminal 129. The data bit stream output via the terminal 129 is supplied to the actual generated code amount for a predetermined time and the storage occupancy calculation circuit 153 for a predetermined time in order to control the code amount based on the total generated code amount. It has become so.

A time code indicating the reference time is given from the reference time generating circuit 81 to the terminal 82d. The data time information creation circuit 128 creates an encoder data time code based on this time code and outputs it to the storage means 127. The storage means 127 is a data compressor 125.
The output is stored and the read is performed while the source data time code and the encoder data time code corresponding to the stored data are associated with each other. In addition, storage means
By adjusting the output timing by 127, the generated code amount of the video data, the data data and other data can be smoothed.

In FIG. 1, the multiplexer 30 includes a video encoder 50, an audio encoder 91 and a data encoder.
Using the encoder time code corresponding to each of 120 coded outputs, multiplexing is performed while grasping the synchronization relationship of each coded output. For example, when each encoder time code added to each coded output is represented by the source video time code, multiplexing is performed for each coded output having the same time code value.

When the encoders 50, 91 and 120 operate separately, the system controller based on the operation unit 26 is used.
Under the control of 25, the multiplexer 30 performs a multiplexing process for achieving the synchronization relationship among the source video time code, the source audio time code, and the source data time code designated by the operation unit 26. In this case, the multiplexer
The 30 is adapted to establish a synchronization relationship by using the encoder time code obtained by the time code conversion / association processing of each encoder.

The multiplexing order of the multiplexer 30 is
Other data, audio data, video data in that order,
The multiplexed data output from the multiplexer 30 is 1 GO.
It is a unit of P (for example, 12 frames).

FIG. 6 is a block diagram showing a concrete configuration of the recording processing circuit 31 and the cutting device 32 in FIG.

The multiplexed data from the multiplexer 30 is supplied to the storage means 130. The storage means 130 smoothes the output rate of the multiplexed data and outputs it to the multiplexer 132. The storage capacity of the storage means 130 is set to be less than or equal to the storage capacity of the system buffer on the decoder side, which will be described later.

The multiplexed data from the multiplexer 30 is also supplied to the generated code amount pointer 131 per predetermined time.
The generated code amount pointer 131 for a predetermined time period creates a generated code amount pointer corresponding to the generated code amount per a predetermined time period. When one multiplexing unit in the multiplexer 30 is called a multiplex unit, the generated code amount pointer indicates, for example, the following values (1) to (7).

(1) A value indicating the total code amount of the multiplex unit.

(2) A value indicating the data code amount in the multiplex unit.

(3) A value indicating the voice code amount in the multiplex unit.

(4) A value indicating the video code amount in the multiplex unit.

(5) A value indicating the code amount for each picture of the video in the multiplex unit.

(6) A value indicating the code amount up to the n-th previous multiplex unit.

(7) A value indicating the code amount up to the n-th multiplexed unit.

The generated code amount pointer 131 for a predetermined time is the multiplexer 13 using the generated code amount pointer as auxiliary information.
Output to 2. The multiplexer 132 adds auxiliary information to the multiplexed data from the storage unit 130 to add the sector creation circuit 13
Output to 3.

The sector creation circuit 133 includes a multiplexer 13
The output of 2 is divided into codes of a predetermined number of bytes to form sectors. The output of the sector creation circuit 133 is supplied to an error correction coding circuit (hereinafter referred to as ECC) 135. ECC13
5 adds an error correction code to the input sector unit data and outputs it to the modulation circuit 136. The modulation circuit 136 is
Modulation suitable for recording input data, eg 8-14
The data is modulated and output to the recording equalizer 137. The recording equalizer 137 emphasizes a signal in a predetermined band of the input data and outputs the recording data to the cutting device 32.

The cutting device 32 is composed of an optical modulator 138 and a cutting unit 139. Light modulator 13
Reference numeral 8 optically modulates the recording data from the recording equalizer 137 and outputs it to the cutting unit 139. The cutting unit 139 emits a laser beam to the disc original plate 33 based on the output of the optical modulator 138 to perform cutting based on the recorded data.

On the other hand, the output of the multiplexer 132 is also supplied to the kick information creating circuit 134. As mentioned above, the output of multiplexer 132 is a variable rate. The added value of the video peak rate, the audio peak rate, and the data peak rate is set so as not to exceed the peak rate of recording on the disc original plate 33, and when data is transmitted at a rate lower than the peak rate, It can be reproduced by kicking the reproduction pickup. In this case, if the kick is performed by detecting the overflow of the system buffer on the decoder side, the kick becomes unstable.

Therefore, it is possible to record the kick information indicating the kick timing and the number of tracks of the kick at the time of recording. The kick information creating circuit 134 is utilized by utilizing that the recording pattern on the original disk 33 is uniquely determined according to the output code amount of the multiplexer 132.
Is based on the input of the multiplexer 132 input
Create kick information that allows the pickup kick to operate stably. The kick information creation circuit 134 outputs the created kick information to the sector creation circuit 133. Sector creation circuit 13
3 outputs the output of the multiplexer 132 with kick information added.

In this embodiment, since the generated code amount pointers are multiplexed, a stable kick can be made on the reproducing side without using kick information, as will be described later.

FIG. 7 is a block diagram showing a specific configuration of the system control device 25 in FIG.

The encoder system controller 151
The entire system is controlled by the control signal based on the user operation of the operation unit 26. Since the system has a variable rate, the designation information designated by the operation unit 26 includes peak rate and average rate information. The information of the average rate is determined by the recording capacity of the recording medium (disk) and the time of the source signal to be recorded. That is, since the recording capacity of the disk medium is fixed, when the recording time is set, the average code amount that can be recorded per unit time, that is, the average recording rate (average rate) is determined. The operation unit 26 also has a function of displaying the encoding result. It should be noted that the displayed encoding result is the amount of generated code and the quantization scale at the first encoding of the variable rate.

The system controller 25 totally controls the total code amount of video data, audio data and other data. As described above, the encoded outputs of video data, audio data and other data are variable rates, respectively. Since the transmission rate is a variable rate, as described above, the two types of rates, the peak rate and the average rate, are considered, and the total generated code amount is considered. The same applies when at least one coded output of video data, audio data, and other data has a variable rate.

That is, the system controller 25 suppresses the peak rate of the coded output to the maximum recording / reproducing rate or less.
Therefore, the system code amount distribution circuit 152, based on the outputs of the video peak rate analysis circuit 22, the audio peak rate analysis circuit 23, and the data peak rate analysis circuit 24, the video code amount control circuit 58 and the audio code amount control circuit 111. And the data code amount control circuit 126. As a result, the encoding is performed so that the sum of the video peak rate, the audio peak rate, and the data peak rate is less than or equal to the peak rate of the recording medium.

Further, the terminals 79, 80, 107 and 12 are connected to the actually generated code amount and storage means occupancy calculation circuit 153 for a predetermined time.
The encoded output for each data is also input via 9.
The predetermined time actual generation code amount and predetermined time storage means occupancy calculation circuit 153 calculates the code amount of the encoding output actually generated per predetermined time (actual generation code amount) to calculate the actual generation cumulative code amount calculation circuit 154. And the occupancy of the storage means 76, 77, 106, 127 per predetermined time is calculated and the multiplexer 155 is controlled. The actual generated cumulative code amount calculating circuit 154 is adapted to cumulatively add the code amounts per predetermined time to obtain the actual generated cumulative code amount and output it to the system code amount distribution circuit 152.

The system code amount distribution circuit 152 controls the re-encoding so that the actually generated cumulative code amount (total generated code amount) of the encoded output for all recording data corresponds to the capacity of the disk medium. ing.

Next, the operation of the embodiment thus constructed will be described with reference to FIG. FIG. 8 is a graph for explaining the control of the video code amount control circuit 58, in which the horizontal axis represents the video encoded output transmission rate and the vertical axis represents the quantization level.

Video data, audio data and other data from the studio equipment 21 are supplied to the video encoder 50, the audio encoder 91 and the data encoder 120, respectively.
In this example, the encoding is divided into two steps. At the time of encoding the first step, peak rate control is performed while estimating the peak rate in advance. Then, at the time of encoding the second step, the total compression code amount is limited based on the capacity of the recording medium.

That is, in the first step, first, the video peak rate analysis circuit 22 and the audio peak rate analysis circuit 23.
The data peak rate analysis circuit 24 detects the peak rate of the input data. In this case, for example, 1
The peak rate is analyzed for each GOP period. The reason why one GOP period is used is that the generated code amount greatly changes within the GOP.

Now, the number of frames N in one GOP period is 9
Therefore, it is assumed that bidirectional prediction is adopted. Further, the picture interval M between the I picture and the P picture (compressed frame between frames) is 3. The transmission order is B, B,
The order is I, B, B, P, B, B, P pictures. The B picture indicates a bidirectional predictive coding frame. In this case, generally, the code amount of the I picture is the largest and the code amount of the B picture is the smallest.
Therefore, the peak rate is calculated based on the I picture.

The video peak rate analysis circuit 22 detects the activity and the scene change of the input video data for one GOP period and outputs it to the system code amount distribution circuit 152 and the video code amount control circuit 58. The video data is delayed by 1 GOP period by the frame memory 54 and supplied to the video compression circuit 27. The motion detection circuit 61 of the video compression circuit 27 detects the motion vector and outputs it to the system code amount distribution circuit 152 and the video code amount control circuit 58.

Further, the voice peak rate analysis circuit 23 obtains a rough estimation of the voice code amount based on the detection result of the vowel, consonant and background sound, and outputs it to the system code amount distribution circuit 152 and the voice code amount control circuit 111. The data peak rate analysis circuit 24 obtains an approximation of the data code amount based on the detection result of the data content, and outputs it to the system code amount distribution circuit 152 and the data code amount control circuit 126.

The video code amount control circuit 58, the audio code amount control circuit 111, and the data code amount control circuit 126 obtain an approximate value of the peak rate when each data is encoded based on the peak rate analysis result of each data. . Then, the video code amount control circuit 58, the audio code amount control circuit 111, and the data code amount control circuit 126 are controlled by the system code amount distribution circuit 152, and the sum of the approximate values of the peak rates of each data is recorded / reproduced. Control not to exceed. The video code amount control circuit 58 controls the quantization circuit 64, the audio code amount control circuit 111 controls the bit compression circuit 103, and the data code amount control circuit 126 controls the data compressor 125.

For example, the video code amount control circuit 58 sets the quantization level according to the calculated video peak rate of the video data. In this case, as shown in FIGS. 2A and 2B, when the calculated video peak rate becomes larger than a predetermined threshold value, the video code amount control circuit 58 performs quantum quantization stepwise according to the peak rate. The conversion step is to be enlarged. As a result, when the calculated video peak rate is relatively high, the compression rate of the video data becomes high, and the video peak rate can be reduced. 2B and 2C show examples in which different thresholds are set.

In the video compression circuit 27, the audio compression circuit 28 and the data compression circuit 29, the peak rate of the encoded output is limited by the video code amount control circuit 58, the audio code amount control circuit 111 and the data code amount control circuit 126, respectively. Then, the input data is encoded. In the video compression circuit 27, the variable length coding output from the variable length coding circuit 65 is a multiplexer.
Overhead data is added by 73 and storage means 77
Is supplied to. The storage means 77 also stores the encoder video time code from the video time information creating circuit 84 at the same time.

Similarly, the output from the bit stream creation circuit 105 of the audio compression circuit 28 is supplied to the storage means 106,
It is stored together with the encoder voice time code from the voice time information generating circuit 108. The encoded output from the data compressor 125 of the data compression circuit 29 is supplied to the storage means 127 and stored together with the encoder data time code from the data time information creation circuit 128.

Next, re-encoding processing is performed in the second step. At the time of encoding in the first step, the video compression circuit 27
The output of the multiplexer 73, the output of the bit stream creating circuit 105 of the audio compression circuit 28, and the output of the data compressor 125 of the data compression circuit 29 are output through the terminals 79, 107 and 129 respectively for a predetermined time and a predetermined amount of generated code. It is supplied to the time storage means occupancy calculation circuit 153. The actual generated code amount for a predetermined time and the predetermined time storage means occupancy calculation circuit 153 sequentially calculate the actual generated code amount for each predetermined time, and the actual generated cumulative code amount calculation circuit 154 accumulates them to obtain the current encoding from the start of encoding. The actual accumulated code amount up to the frame is calculated,
It is supplied to the system code amount distribution circuit 152.

The system code amount distribution circuit 152 detects whether or not the actual cumulative generated code amount (total generated code amount) for all recording data is larger than the recording capacity of the disk medium. The system code amount distribution circuit 152 also supplies information on the generated code amount and the total generated code amount per predetermined time to the operation unit 26, and the operation unit 26 can confirm these actual generated code amounts. If the total generated code amount exceeds the storage capacity of the disk medium, the user
Operate 26 to specify the ratio of reducing the generated code amount and the source time code to be reduced. Even when the total generated code amount is less than or equal to the recording capacity, if it is desired to improve the quality of the video data, audio data and other data after restoration, the ratio of increasing the generated code amount and the source time code to be increased. Is specified.

Information based on the operation of the operation unit 26 is given to the encoder system controller 151 and changed so that the time code indicating the re-encoding position becomes the boundary position between GOPs. Encoder system controller 151
The start time code and the end time code of the re-encoding from are supplied to the studio equipment 21 and also to the editing processing means 78 via the terminal 85. Further, the reduction ratio or the increase ratio is supplied from the encoder system controller 151 to the system code amount distribution circuit 152.

The studio equipment 21 sequentially outputs only the data corresponding to the start time code and the end time code to the video encoder 50, the audio encoder 91 and the data encoder 120. On the other hand, the system code amount distribution circuit 152 determines the compression rate of each data at the time of re-encoding based on the reduction ratio or the increase / decrease ratio, and the video code amount control circuit 58, the audio code amount control circuit 111, and the data code amount control. Controls circuit 126.
As a result, the compression rates of the video compression circuit 27, the audio compression circuit 28, and the data compression circuit 29 are controlled, and the data corresponding to the designated time code is re-encoded at the set compression rate. The storage means 76, 77, 106, 127 update the coded data of the first step to recoded data and store the coded data in the first step while referring to the time code.

When the re-encoding processing does not require re-compression by the compression circuits 27 to 29 and only the editing / processing by the editing / processing means 78 is required, the editing / processing means 78
The data corresponding to the start time code and the end time code is read from the storage means 77, and after given editing processing, it is given to the storage means 77 to update the data.

As described above, in the re-encoding process of the second step, since only part of the data indicated by the time code is re-encoded, the time required for the process of the second step is the same as that of the first step. Α times (α is 0 ≦ α
≤1). Therefore, in the present embodiment, ignoring the 1 GOP period necessary for calculating the peak rate,
The variable rate coding process can be performed in a period approximately (1 + α) times the recording time of the source data.

Next, the peak rate control and buffer management of the first step described above with reference to FIGS. 9 to 11 will be described in more detail. FIG. 9 is a block diagram showing in simplified form the recording disc production system of FIG. 1 and a variable rate decompression device (see FIG. 16) described later. FIG.
Is a graph showing the estimated value of the analyzed peak rate with the code amount on the vertical axis, and FIG. 11 shows the peak code calculation period (t0 to t1) on the horizontal axis and the generated code amount on the vertical axis. 3 is a graph for explaining various rates and buffer states.

In the peak rate analysis circuits 22 to 24 of FIG. 1, it is assumed that the peak rate is calculated in a predetermined period t1 to t0 (for example, 1 GOP period (9 frame periods)). The code amounts in a predetermined time range estimated based on the analysis results (approximate values of the code amounts) of the peak rate analysis circuits 22 to 24 are respectively Vest, Aest, and Dest.
The code amounts Vest, Aest, Dest correspond to the video peak rate, the audio peak rate, and the data peak rate based on the analysis result. Period t1 -t
The code amount of the encoded output of each compression circuit 27 to 29 at 0,
That is, the input code amounts of the storage means 76, 106 and 127 (hereinafter, also referred to as encoder buffers) are set to V, A and D, respectively.
Further, the code amount in the period t1 -t0 of each output after being smoothed by the storage means 76, 106, 127 is V ', A',
D '. The capacities of the storage means 76, 106, 127 are BS1 ', BS2', BS3 ', respectively, and the occupation amounts of the storage means 76, 106, 127 at a predetermined time t are F1 respectively.
(T) ', F2 (t)', F3 (t) '.

The code amount of the period t1 to t0 corresponding to the maximum rate allowed for the output of the multiplexer 30 based on the limit value of the disk peak rate is Speak. The value of Speak is a fixed value determined based on the disc plate and the player. System code amount distribution circuit 15
2 is a compression circuit 27 based on this Peak and the capacity (remaining capacity) available in the storage means 76, 106, 127.
To 29 output code amounts (output rates) are determined.

FIG. 10 shows the limitation of the total code amount of each compression circuit which is allowed per predetermined peak rate calculation period. In FIG. 10A, the horizontal axis is assigned to other data, audio data, and video data, and the vertical axis represents the sum of rates. That is, as shown in FIG. 10, the limit value P of the total code amount is given by the sum of Speak and the remaining capacity of each encoder buffer at the start timing of the peak rate calculation period, and the following expression (1) is established.

P = Speak + (BS1'-F1 '(t0)) + (BS2'-F2' (t0)) + (BS3'-F3 '(t0)) (1) The remaining capacity of each encoder buffer Has been determined at the time when the encoding is completed up to time t0.

Therefore, the system code amount distribution circuit 152
Each of the compression circuits 27 to 29 is controlled by controlling the video code amount control circuit 58, the audio code amount control circuit 111, and the data code amount control circuit 126.
The sum of the output code amounts at the time t1 to t0 is suppressed within the limit value P.

Now, as shown in FIG. 10, the period t1 based on the analysis results of the video peak rate analysis circuit 22, the audio peak rate analysis circuit 23 and the data peak rate analysis circuit 24.
It is assumed that the sum K of the estimated values Vest, Aest, and Dest of each code amount at -t0 is larger than the limit value P. In this case, the video code amount control circuit 58, the audio code amount control circuit 111, and the data code amount control circuit 126 set the compression rates of the compression circuits 27 to 29 to be relatively high, and as shown in FIG. The sum R of the generated code amounts V, A, and D of the actual encoded output for the data is set to be the limit value P or less.

FIG. 11 shows a case in which the remaining capacities of the respective storage means 76, 106, 127 and the output code amounts V ', A', D'are set appropriately, and FIGS. 11 (b) to 11 (d) are shown. This is a case where the output code amount is V1 ', A1', D1 '.
In (f) to (h), the output code amount is V2 ', A2', D2.
′ Is the case.

FIG. 11A shows the generated code amounts V, A and D of the actual encoded output. FIG. 11A shows that the generated code amount becomes D + A + V from t0 to t1. In addition, the straight line 171, in FIG.
The inclinations of 172 and 173 indicate the generation rates of the encoded outputs of the video data, the audio data and the other data, respectively. Note that FIG. 11A shows an example in which the generation rate of the encoded output of the video data, the audio data, and other data is constant, but if the rate difference is absorbed by the encoder buffer, each encoded output is The generation rate of may change.

FIG. 11B shows the peak rate of video data and the state of the storage means 76 (video buffer). A straight line 171 in FIG. 11B indicates the video peak rate. The remaining capacity of the storage means 76 at time t0 is shown in FIG.
As shown in FIG. 1 (b), it is BS1'-F1 (t0) '. A straight line 171 is a straight line which is inclined with an initial value as an occupancy amount F1 (t0) 'with an inclination based on the image peak rate. Also, the alternate long and short dash line 174 shows the output of the storage means 76, and shows that the code amount V1 'has been output during the period t0 to t1. The slope of the one-dot chain line 174 shows the output rate. Also, the alternate long and short dash line 175 indicates the code amount that can be absorbed by the storage means 76, and the output of the video compression circuit 27 is limited to the generated amount of code that does not exceed the alternate long and short dash line 175. Therefore, the buffer occupancy at time t1 is F1 (t1) '≤BS
1 '.

FIG. 11C shows the peak rate of audio data and the state of the storage means 106 (audio buffer). A straight line 176 in FIG. 11C indicates the voice peak rate. The remaining capacity of the storage means 106 at time t0 is BS2'-F2 (t0) ', as shown in FIG. 11 (c). A straight line 176 is a straight line which is inclined with an initial value as an occupancy F2 (t0) 'with a slope based on the voice peak rate.
Further, the alternate long and short dash line 177 shows the output of the storage means 106, and shows that the code amount A1 'is output during the period t0 to t1. The slope of the one-dot chain line 177 shows the output rate. Also, the alternate long and short dash line 178 indicates the code amount that can be absorbed by the storage means 106, and the output of the voice compression circuit 28 is limited to the generated amount of code that does not exceed the alternate long and short dash line 178. Therefore, the buffer occupancy at time t1 is F2 (t1
) '≤BS2'.

FIG. 11D shows the peak rate of other data and the state of the storage means 127 (data buffer). A straight line 179 in FIG. 11D shows the data peak rate. The remaining capacity of the storage means 127 at time t0 is BS3'-F3 (t as shown in FIG. 11 (d).
0) ′. The straight line 179 shows the initial value as the occupancy F3 (t
0) 'is a straight line inclined with a slope based on the data peak rate. Further, the alternate long and short dash line 180 indicates the output of the storage means 127, and the code amount D1 'in the period t0 to t1.
Is output. The slope of the alternate long and short dash line 180 indicates the output rate. The alternate long and short dash line 181 is a storage means.
The code amount that can be absorbed by 127 is shown, and the output of the data compression circuit 29 is limited to the generated code amount that does not exceed the one-dot chain line 181. Therefore, the buffer occupancy at time t1 is F3 (t1) '≤BS3'.

11F to 11H are respectively shown in FIG.
Corresponding to (b) to (d), the buffer occupancy F1
An example in which the distributions of (t0) ', F2 (t0)', F3 (t0) 'and the output code amounts V', A ', D'from each storage means are changed to V2', A2 ', D2'. Shows. In addition,
The sum of the output code amounts V1 ', A1', D1 'is the limit value Spe.
It is set to ak.

Also in this example, the code amount of the coded output generated by the compression processing in each of the compression circuits 27 to 29 is the same as in the case of FIG. 11A, and the peak rates of these coded outputs are linear. It is represented by 171, 176 and 179. The outputs of the storage means 76, 106 and 127 are represented by straight lines 174 ', 177' and 180 ', respectively.
The codes that can be absorbed by 6 and 127 are straight lines 175 ′ and 178, respectively.
It is represented by ', 181'. In this example, the buffer occupancy F1 (t1) '= BS1 at time t1
', F2 (t1)' = BS2 ', F3 (t1)' = B
S3 '.

Storage means in the case of FIGS. 11B to 11D
The sum O of the output code amount of 76, 106, 127 is V1 '+ A1'
+ D1 ', and the sum O'of the output code amounts of the storage means 76, 106, 127 in the case of FIGS. 11 (f) to (h) is V2' +.
A2 '+ D2'. FIG. 11E shows these output code amounts O and O '. Output code quantity O is Peak
Is the same value as, and indicates the upper limit.

Output code amounts V ', A', D'of storage means 76, 106, 127 and buffer occupancy F at time t1.
The conditions of 1 (t1) ', F2 (t1)' and F3 (t1) 'can be shown below.

(I) Buffer capacity limitation F1 (t1) '≤BS1' F2 (t1) '≤BS2' F3 (t1) '≤BS3' (II) Encoder buffer output peak rate limitation V '+ A' + D'≤ Speak Also, the input rate V, A, D of each encoder buffer
And the buffer occupancy F1 (t0) 'at time t0,
The relationship with F2 (t0) 'and F3 (t0)' is as follows.

(III) Restriction on buffer use V≤V '+ BS1'-F1 (t0)' A≤A '+ BS2'-F2 (t0)' D≤D '+ BS3'-F3 (t0)' These conditions ( From (II) and (III), V + A + D≤Speak + (BS1'-F1 (t0
) ') + (BS2'-F2 (t0)') + (BS3 '
-F3 (t0) ') is derived. This equation matches the above equation (1).

FIG. 12 is a block diagram showing a system code amount distribution circuit and a video code amount control circuit adopted in a variable rate compression apparatus according to another embodiment of the present invention. Other configurations are the same as those of the embodiments of FIGS. 1 to 7, and the configurations of the audio code amount control circuit and the data code amount control circuit are similar to the configuration of the video code amount control circuit. Omit it. Further, FIG. 13 is a graph for explaining the control of the quantization level based on the average rate and the actually generated cumulative code amount.

In the embodiment of FIG. 1, only the peak rate control is performed in the first step, and the total code amount control is performed in the second step.
I was going in step. In this embodiment, the total code amount is controlled also in the first step.

As described above, the average rate is determined based on the recording capacity and the recording data amount of the disc medium.
In this embodiment, the accumulated code amount is detected at a predetermined timing, for example, for each scene, and the generation rate of the encoded output is controlled so that the difference from the code amount based on the average rate is within a predetermined value. It has become.

The system code amount distribution circuit 191 has a video average rate determination circuit 192, an audio average rate determination circuit and a data average rate determination circuit (not shown), and a video peak rate value determination circuit 193 (not shown). The audio peak rate value determining circuit and the data peak rate value determining circuit are included. Further, the system code amount distribution circuit 19
1 has a video rate difference value calculation circuit 198, an audio rate difference value calculation circuit, and a data rate difference value calculation circuit (not shown).

The video average rate determination circuit 192 has terminals 194,
The information about the disk capacity and the code amount distribution information for video, audio and other data are given via 195. The image average rate determination circuit 192 determines the average rate assigned to the encoding of the image data based on the input information and outputs it to the image average rate difference value calculation circuit 198. The video average rate difference value calculation circuit 198 receives the information of the actual generated cumulative code amount from the actual generated cumulative code amount calculation circuit 154 (see FIG. 7) via the terminal 197, and performs the actual video coding at the predetermined time t. A difference between the output rate and the determined video average rate, that is, a rate based on (actually generated cumulative code amount per predetermined time t−average rate × t) is obtained. The output of the video average rate difference value calculation circuit 198 is the video code amount control circuit.
It is supplied to the quantization level increase / decrease value determination circuit 202 of 201.

The video peak rate value determination circuit 193 has a terminal 19
The disc peak rate is given via 6 to determine the video peak rate allowed for encoding the video data and output it to the comparison circuit 203 of the video code amount control circuit 201. The video peak rate value determination circuit 193 may specify each peak rate according to, for example, the ratio of the average rate of each encoded output. For example, video average rate 4M
bps (bit / sec), audio average rate 2 Mbps, data average rate 2 Mbps, and disk peak rate 16 Mbps, set video peak rate to 8 Mbps, audio peak rate to 4 Mbps, and data peak rate to 4 Mbps To do.

The video peak rate approximating circuit 204 of the video code amount control circuit 201 is supplied with an activity, a scene change flag and a motion vector through terminals 205 to 207, respectively, and a standard quantization level determining circuit described later.
The standard quantization level is also given by 212. The video peak rate estimating circuit 204 estimates the code amount Vest when the video data is encoded using the standard quantization level based on the activity, the scene change flag and the motion vector, and calculates the comparing circuit 203 and the corrected video peak rate. Output to circuit 208. Corrected video peak rate calculation circuit 208
Is supplied with the actual generated code amount of one timing before via the terminal 209. The corrected video peak rate calculation circuit 208 corrects the approximate value of the video peak rate using the actually generated code amount and outputs it to the comparison circuit 210.

The comparator circuit 203 is given the occupation amount (F1 (t0) ') of the storage means 76 (video buffer) via the terminal 215, and the estimated code amount Ves of the video encoded output is given.
It is determined whether or not t is larger than the sum of the determined video peak rate and the remaining capacity (BS1'-F1 (t0) ') of the storage means 76. Similarly, the comparison circuit 210 determines whether the estimated value of the corrected code amount is larger than the sum of the determined video peak rate and the remaining capacity of the storage unit 76. The comparison result of the comparison circuits 203 and 210 is supplied to the video quantization level determination circuit 211. Video quantization level decision circuit
211 peak rate limited video quantization level determination circuit 213
Is the Ves estimated by the comparison result of the comparison circuit 203.
When it is shown that t is smaller, a signal for setting the same quantization level as the current quantization level (standard quantization level) is output via the terminal 214. vice versa,
When the comparison result of the comparison circuit 203 indicates that the estimated Vest is larger, the peak rate control video quantization level determination circuit 213 outputs the signal for coarsening the current quantization level to the terminal 214. It is designed to be output via. As a result, the quantization level control shown in FIG. 8 can be performed. Further, the peak rate limited video quantization level determination circuit 213 enables more accurate peak rate control by setting the quantization level also using the output of the comparison circuit 210.

On the other hand, also in the first step, the output of the video average rate difference value calculation circuit 198 is used to control the total code amount. As described above, the average rate is a value obtained by dividing the total disk capacity by the maximum recording time. Therefore, by making the output rate of the encoded output for each data averagely match the average rate, the total generated code amount can be made to correspond to the disk capacity. Therefore, the video, audio and data code amount control circuit is controlled so that the difference between the cumulative code amount based on the average rate and the actual generated cumulative code amount does not become larger than a predetermined value.

That is, the image average rate difference value calculation circuit 198
Is supplied to the quantization level increase / decrease value determination circuit 202 of the video code amount control circuit 201 as a cumulative difference value. The quantization level increase / decrease value determination circuit 202 is composed of, for example, a ROM, and is also given a scene change flag via a terminal 216 to output the quantization level increase / decrease value corresponding to the cumulative difference value for each scene. That is, the quantization level increase / decrease value determination circuit 202 outputs the quantization level increase / decrease value for roughening the quantization level according to the positive cumulative difference value, and finely adjusts the quantization level according to the negative cumulative difference value. The increase / decrease value of the quantization level for outputting is output. Quantization level increase / decrease value determination circuit
The output of 202 is given to the standard quantization level determination circuit 212 of the video quantization level determination circuit 211.

The standard quantization level determination circuit 212 increases or decreases the quantization level at a predetermined time based on the quantization level increase / decrease value and outputs it as the standard quantization level to the peak rate limited video quantization level determination circuit 213. The peak rate limited video quantization level determination circuit 213 outputs a signal for setting the quantization level based on the input standard quantization level via the terminal 214.

In this way, the quantization level control shown in FIG. 13 is performed. In FIG. 13, the quantization level becomes coarser as the actually generated cumulative code amount increases. As a result, the actual generated cumulative code amount is brought closer to the cumulative code amount based on the average rate so that the total code amount of the recording data corresponds to the disk capacity.

Next, the operation of the embodiment thus constructed will be described with reference to FIG. FIG. 14 is a graph for explaining the total code amount control, where the horizontal axis represents the time in scene units and the vertical axis represents the cumulative code amount and the actually generated cumulative code amount based on the average rate.

The solid line A in FIG. 14 shows the cumulative code amount based on the average rate. Also in this embodiment, the encoding is performed twice, that is, the first step encoding process and the second step re-encoding process. Similar to the embodiment of FIG. 1, the encoding process for video data, audio data and other data is the same, so only the encoding process for video data will be described.

The video data input to the video encoder 50 (see FIG. 1) is set to 1 in the video peak rate analysis circuit 22.
The activity and the scene change in the GOP period are detected and given to the system code amount distribution circuit 191 and the video code amount control circuit 201 of FIG. On the other hand, the video average rate determination circuit 192 of the system code amount distribution circuit 191 receives information about the disk capacity and the like, and the video average rate determination circuit 192 encodes video data based on the input information. Determine the average rate assigned. Further, the video peak rate value determination circuit 193 determines the video peak rate allowed for encoding the video data.

The motion vector is also given to the video peak rate estimating circuit 204 of the video code amount control circuit 201, and the generated code amount Vest when the video data is encoded using the standard quantization level is estimated. This approximate value is the comparison circuit
The comparison circuit 203, which is supplied to 203, determines whether the estimated value is smaller than the sum of the determined code amount based on the video peak rate and the remaining capacity of the video buffer. Comparison circuit 203
Output is peak rate limited video quantization level decision circuit 21
1 and the quantization level is limited according to FIG. As a result, a video peak rate that satisfies the disk peak rate limitation is assigned to the video data.

The video data from the video peak rate analysis circuit 22 is coded in the video compression circuit 27 using the quantization level based on FIG. Coded output is storage means
76 (video buffer) and outputs the actual generated code amount for a predetermined time and storage unit occupancy calculation circuit 15 for a predetermined time.
3 (see FIG. 7) and further to the actually generated cumulative code amount calculation circuit 154. In this way, the actual generated code amount and actual generated cumulative code amount of the actual video data are obtained.

Curve B in FIG. 14 shows the actual generated cumulative code amount. Now, as shown in scene 1 of FIG. 14, it is assumed that the actually generated cumulative code amount is larger than the cumulative code amount based on the average rate. Video average rate difference value calculation circuit 198
Is a cumulative difference between the actual generated cumulative code amount and the average rate from the average rate determination circuit 192, and the video code amount control circuit
It outputs to the quantization level increase / decrease value determination circuit 202 of 201. The quantization level increase / decrease value determination circuit 202 determines the quantization level increase / decrease value based on the cumulative difference value. The broken line in FIG. 4 shows the correspondence between the cumulative difference value and the quantization level increase / decrease value. For example, at the timing t1, the cumulative difference value has become the value corresponding to the quantization level increase / decrease value 1. .

The alternate long and short dash line after the timing t1 shows the change in the code amount in the case where the peak rate control is not performed. In practice, the quantization level shown in FIG. 8 is obtained based on the outputs of the comparison circuits 203 and 210. Due to the control, the cumulative code amount is shown by the solid line B.

The quantization level increase / decrease value determination circuit 202 has a terminal 21
Depending on the scene change flag input via 6,
At the scene switching timing t2, the quantization level increase / decrease value "2" is output. As a result, the standard quantization level determination circuit 212 controls the quantization level to be coarse,
The peak rate limited video quantization level determination circuit 213 sets a coarser quantization level than the standard quantization level.
In this way, the increase amount of the cumulative code amount of the scene 2 becomes smaller than the increase amount of the cumulative code amount based on the average rate, and the actual generated cumulative code amount is prevented from becoming significantly larger than the cumulative code amount based on the average rate. It

Thereafter, similar operations are repeated, and the difference between the actual generated cumulative code amount and the cumulative code amount based on the average rate is maintained at a relatively small value.

In the next second step, the same processing as in the first step is performed. Now, assume that scene 4 is re-encoded. The straight line E in FIG. 14 indicates the cumulative code amount based on the average rate for the scene 4, and the alternate long and short dash line C indicates the first
The cumulative code amount of the scene 4 in the step is shown, and the solid curve D shows the cumulative code amount by the re-encoding.

In the encoding of scene 4 in the first step, a relatively large generated code amount is generated. Therefore, in order to reduce the code amount, scene 4 is re-encoded by setting a relatively coarse quantization level. In this way, the total code amount of the recording data can be made to correspond to the disc capacity.

As described above, in this embodiment, not only the peak rate control is performed in the first step, but also the total code amount control based on the average rate is performed. Therefore, the total code amount of the stored data can be made to substantially correspond to the disc capacity even in the first step alone, so that the time required for producing the disc can be further shortened.

In the present embodiment, the quantization level is changed according to the cumulative difference value for each scene change, but the quantization level may be changed for each GOP, for example. Further, the quantization level may be changed when the cumulative difference value exceeds a predetermined threshold value (for example, the quantization level increase / decrease value of 4 in FIG. 14). Furthermore, prior to encoding, priorities are assigned to each scene, the quantization level is changed for each scene for a high priority scene, and the quantization level is changed for each GOP for a low priority scene. May be.

In the present embodiment, the generated code amount is controlled using a constant average rate. However, for example, the average rate is corrected for each scene according to the priority order, and the corrected average rate is used. The code amount may be controlled. In this case, the straight line A in FIG. 14 is a polygonal line whose inclination changes for each scene. Further, the quantization level increase / decrease value shown by the broken line also becomes a polygonal line parallel to this polygonal line. In this case, the position of the scene is designated by using the time code.

In each of the above embodiments, the 1 GOP period is used as the peak rate analysis period, but it may be expanded to n × i frame periods (n is the number of 1 GOP frames). FIG. 15 is an explanatory diagram showing the relationship between the output rate and the buffer capacity when i is set to 3. Note that FIG.
Then, one GOP period is set to T0.

In this case, the frame memories 51 and 54 (see FIG. 3), the audio delay memory 92 (see FIG. 4) and the data delay memory 122 (see FIG. 5) respectively store data for n × i frame periods. Set to the capacity possible. Also, storage means
As shown in FIG. 15, the capacity of 76 (FIG. 3) is the product of the instantaneous maximum rate rs1 of the output of the multiplexer 73 and the n.times.i frame time (iT0). Similarly, the storage means 106 (see FIG. 4), which is a voice encoder buffer, is set to a capacity obtained by multiplying the maximum voice rate by the time iT0, and the storage means 127 (see FIG. 5), which is a data encoder buffer, stores the data. The capacity is set by multiplying the maximum rate and the time iT0.

In this case, each storage means 76, 106, 127
It suffices to control so that overflow or underflow does not occur in 1), and the short-term transmission rate rs0, which is the instantaneous maximum rate per GOP period, is equal to the maximum transmission rate rs1 as shown in FIGS. i (=
3) Double.

As described above, in this case, the peak rate control may be performed so that the maximum rate is not exceeded for n × i frames. Obviously, this control can be configured by a circuit similar to that shown in FIG.

By the way, in each of the above-mentioned embodiments, the data rates to be assigned to the video data, the audio data and other data have been calculated in advance. As a method of allocating the data rate, an approximate value Ves of the code amount obtained by the peak rate analysis circuits 22 to 24
There is a method of using t, Aest, Dest, and weighting these approximate values for each of video, audio, and other data. Peak rate analysis circuit 22 to 24
Is applied to the compression circuits 27 to 29 after delaying the input data for a predetermined period, and before the compression processing of the compression circuits 27 to 29,
It is possible to judge whether or not the addition result of the approximate values Vest, Aest, Dest of the code amount exceeds the code amount Speak based on the maximum rate allowed by the multiplexer 30.

If the sum of estimated values Vest + Aest + D
When est is larger than the code amount Speak, the input code amount V of the encoder buffer by the actual encoding,
The sum of A and D is controlled to be equal to or less than the code amount Speak. In this case, as described above, each data is weighted.

Now, in the case of rate control such that V + A + D≤Speak, the weighting for video data is WV and the weighting for audio data is WA.
And the weighting for other data is WD. Then, the input code amounts V, A, and D of the encoder buffer are given by the following equations (2) to (4), respectively.

V = WV × Vest (2) A = WA × Aest (3) D = WD × Dest (4) Since the weighting value may vary depending on time (t), The weighting is set to WV (t), the weighting to audio data is WA (t), and the weighting to other data is WD (t), and the weighting is set for each time. The time code is used to specify the time.

By performing rate control using weighting, the amount of effective information transmitted can be increased. For example, in the case of recording a concert program, the weighting WA (t) for the audio data is increased and the weighting WV (t) for the video is decreased in the part where the music sounds. Thereby, the sound quality can be improved. In the explanation of a concert or the like using a panel, the weighting WA (t) for video data is increased and the weighting WA (t) for audio data is decreased to improve the image quality.

As described above, the weighting process is performed based on the analysis results of the peak rate analysis circuits 22 to 24. By this weighting process, the allocation of the rate to each data is determined, the quantization level based on the allocated rate is set, and each data is encoded. The encoded output of each data is sent to the multiplexer 30 via the encoder buffer.
Supply to. In this case, the occupancy of each encoder buffer is detected, and the data stored in the buffer with a high usage rate is preferentially supplied to the multiplexer 30. In this way, the encoded data is multiplexed and output from the multiplexer 30.

FIG. 16 is a block diagram showing a variable rate expansion apparatus according to an embodiment of the present invention. This embodiment reproduces a disc recorded at a variable rate in the recording disc production system of each of the above embodiments.

The variable rate expansion device 221 includes a player preprocessing unit 222, a demultiplexer 163, a video buffer 167, an audio buffer 168, a data buffer 169, and a video decoder 22.
7, audio decoder 228 and data decoder 229. Video buffer 167, audio buffer 168
A data buffer 169 (hereinafter, also referred to as a decoder buffer) is provided to smooth data reproduced at a variable rate. For the same reason, the player preprocessing unit
A decoder system buffer 162 is also provided in 222.

The player preprocessing unit 222 has a spindle motor 231 for rotating the disc 230. The disc 230 is recorded by the disc production system of the embodiment of FIG. 1, for example. The spindle motor 231 rotates the disk 230 at a predetermined rotation speed.
The pickup 161 reproduces the data written on the disk 230 and outputs it to the amplifier 233. Pickup control circuit
234 is controlled by a kick track number determination circuit 237, which will be described later, to control the movement of the pickup 161 in the radial direction of the disk 230.

The amplifier 233 amplifies the weak reproduction signal from the pickup 161 and supplies it to the equalizer 235. The equalizer 235 changes the frequency characteristic of the reproduced signal by performing waveform equalization. The data slicer 236 performs waveform shaping by slicing the output of the equalizer 235 at a predetermined level and outputs reproduction data to the demodulation circuit 238 and the PLL (phase locked loop circuit) 239. The PLL 239 reproduces a clock from the reproduced signal whose waveform has been shaped and outputs it to the demodulation circuit 238. The demodulation circuit 238 demodulates the reproduced signal using the reproduced clock. Thereby, for example, the modulation circuit of FIG.
It is designed to recover the data before 136 modulation processing.

The demodulated data from the demodulation circuit 238 is supplied to the synchronization detection circuit 241 and the error correction circuit (hereinafter referred to as ECC) 242 of the sector detection circuit 240. ECC242 is
The demodulated data is error-corrected and output. The error correction result of the ECC 242 is output from the output terminal 244 as an error flag. The synchronization detection circuit 241 extracts the synchronization signal included in the demodulated data. Further, the sector number detection circuit 243 detects the sector number included in the demodulated data.

The demodulated data error-corrected by the ECC 242 is supplied to the decoder system buffer 162 and the system buffer controller 248. The system buffer controller 248 controls the decoder system buffer 162 by extracting buffer control information from the demodulated data.
The buffer control information is, for example, MPEG.
In two standards, SCR (System Clock Reference), Mu
x Rate (Multiplexer Rate), DTS (Decoding
Time Stamp) and PTS (presentation Time Stamp). The decoder system buffer 162 is controlled by the system buffer controller 248 to buffer the output of the ECC 242 and output it to the demultiplexer 163. The overflow detection circuit 247 detects the overflow of the decoder system buffer 162 based on the output of the system buffer controller 248 and outputs a detection signal to the kick track number determination circuit 237.

In this embodiment, the sector detection circuit 240
The output of ECC242 is pointer detection (unit length detection)
It is also supplied to the circuit 245. The pointer detection circuit 245 detects the generated code amount pointer added for each predetermined generated code amount at the time of recording to determine the kick track number determination circuit.
It is designed to output to 237. If the kick information is recorded during recording, the kick information reproduction circuit
246 reproduces the recorded kick information and outputs it to the kick track number determination circuit 237.

The kick track number determination circuit 237 is connected to the terminal 24.
The error flag is entered via 9
The rotational speed information of 230 is also input. The kick track number determination circuit 237 controls the pickup control circuit 234 by calculating the buffer occupancy value, the pickup kick timing, and the kick track number based on the input information. . That is, the disc
Since the linear velocity of 230 is constant, it is necessary to kick the pickup 161 in order to properly reproduce the variable rate recording data. The kick track number determination circuit 237 outputs the information of the kick timing and the kick track number to the pickup control circuit 234 so that the recorded data of the variable rate is normally reproduced.

The output of the decoder system buffer 162 of the player preprocessor 222 is supplied to the demultiplexer 163. The demultiplexer 163 separates the input demodulated data into encoded bit streams of video data, audio data or other data, and outputs them to the video buffer 167, audio buffer 168 or data buffer 169, respectively. Video buffer 167, audio buffer 168 or data buffer 16
Reference numeral 9 denotes a video decoder 227, an audio decoder 228, or a data decoder which holds the input data at the coding rate.
It is designed to output to 229.

FIG. 17 is a block diagram showing a specific structure of the video decoder shown in FIG.

The video bit stream from the demultiplexer 163 is supplied to the rate buffer 252 and the overhead data detection circuit 253 via the input terminal 251. The overhead data detection circuit 253 detects the overhead data inserted at the time of recording, and through the terminal 254, the rate buffer 252, the variable length decoding circuit 256, the inverse quantization circuit 258, the intra-frame / inter-frame switching circuit 270, the motion Compensation circuit 26
7 and the frame delay circuit 266. The rate buffer 252 is composed of a FIFO, and based on the overhead data, demodulates the data at the decoding rate at the terminal 25.
Output from 5 to variable length decoding circuit 256. The rate buffer 252 can also be used as the video buffer 167 (see FIG. 16).

The variable length decoding circuit 256 performs the variable length decoding process and restores the data before the variable length coding process on the recording side.
The variable length decoded output is output to the inverse quantization circuit 258 via the terminal 257.
Is supplied to. The inverse quantization circuit 258, to which the quantization level is applied, performs inverse quantization on the input data to restore the data before quantization, and outputs it to the inverse DCT circuit 259. Reverse DC
The T circuit 259 outputs the inverse quantized output to the DC by the inverse DCT processing.
The data before T processing is restored and output to the adder 260.

The terminal 271 is connected to the intra-frame / inter-frame switching circuit 270.
Overhead data indicating whether the data is an intra-frame compressed frame data or an inter-frame compressed frame data is input via. In-frame / inter-frame switching circuit 270
Outputs a control signal for turning off the switch 269 when it is shown that the data is an intra-frame compressed frame, and when it is shown that the data is an inter-frame compressed frame, The control signal for turning on the switch 269 is output. The adder 260 switches the switch 269 when the data of the inter-frame compressed frame is input.
The output of the motion compensation circuit 267 is supplied via the switch 261 and the inverse DCT output of the inter-frame compressed frame and the output of the motion compensation circuit 267 are added.
It is designed to output to 264. Also, adder 260
The inverse DCT output of the intra-frame compressed frame is directly passed through the switch 261 to the deblocking circuit 26.
It is designed to output to 4.

The output of the adder 260 is the switch 261 and the terminal
It is also supplied to the frame delay circuit 266 via 265. The frame delay circuit 266 is a memory that holds the reference image of the inter-frame compressed frame, and holds the restored image data up to the previous frame used as the reference image and holds the motion compensation circuit 26.
Output to 7. The motion compensation circuit 267 receives the overhead data indicating the motion vector via the terminal 268, corrects the blocking position of the reference image of the frame delay circuit 266 based on the motion vector, and then performs the motion-compensated reference image block data. Is output to the adder 260 via the switch 269.

By the way, according to the MPEG2 standard, data of a macro block that does not need to be transmitted, such as an inter-frame compressed frame for a still image, is skipped and only the skip number of data is transmitted. Overhead data indicating the number of skips is given to the skip control circuit 262 via the terminal 263, and the switch 261 is turned off at the time of skipping.

The deblocking circuit 264 restores the data in m × n pixel block units to the data in the scanning order based on the overhead data input via the terminal 274, and outputs the luminance signal Y from the terminal 275. Color difference signals U and V are output from terminals 276 and 277, respectively. A memory is required to rearrange the data in the scan order, and the deblocking circuit 264 uses the memory of the frame delay circuit 266 to deblock the data. Therefore, the data stored in the frame delay circuit 266 is also supplied to the deblocking circuit 264 via the switch 272 controlled by the overhead data from the terminal 273.

In the video decoder configured as described above, the video bit stream input via the terminal 251 is subjected to the variable length decoding circuit 256 via the rate buffer 252.
Is supplied to. The video bit stream is subjected to variable length decoding in the variable length decoding circuit 256 and inversely quantized in the inverse quantization circuit 258. Further, the inverse DCT circuit 259 performs inverse DCT processing on the inverse quantized output to restore the data before the DCT processing.

When the input bit stream is the data of the intra-frame compressed frame, the switch 269 is off, and the adder 260 outputs the output of the inverse DCT circuit 259 as it is via the switch 261 to the deblocking circuit 264. Output to. The deblocking circuit 264 rearranges the input data in raster order and outputs the luminance signal Y and the color difference signals U and V from terminals 275 to 277, respectively.

On the other hand, when the input bit stream is the data of the inter-frame compressed frame, the inverse DCT
Since the output of the circuit 259 is the prediction error, it is reproduced using the restored image data up to the previous frame. Frame delay circuit
Reference numeral 266 stores the reference image data when the restored image data up to the previous frame is given via the terminal 265. The motion compensation circuit 267 corrects the blocking position of the reference image data based on the motion vector, and outputs the motion-compensated reference image block data. The adder 260 adds the reference image block data from the switch 269 and the output of the inverse DCT circuit 259 to restore the image and outputs it to the deblocking circuit 264. The deblocking circuit 264 rearranges the input data in raster order, and the luminance signal Y and the color difference signals U and V are arranged.
Are output from terminals 275 to 277, respectively.

FIG. 18 is a block diagram showing a specific structure of the audio decoder 228 in FIG.

The audio bitstream from the audio buffer is supplied to the bitstream decomposition and error detection circuit 281. The bitstream decomposition and error detection circuit 281 is
The dequantization circuit 283 decomposes the input bitstream into compressed audio data and encoded data of side information, respectively.
And side information decoding circuit 282. The side information decoding circuit 282 restores the side information by a decoding process and outputs the bit allocation information and the scale factor to the inverse quantization circuit 283.

The dequantization circuit 283 uses the bit allocation information and the scale factor to dequantize the compressed voice data to restore the data before the quantization process, and outputs it to the subband synthesis filter bank 284. The subband synthesis filter bank 284 is configured to synthesize the divided subband signals from the inverse quantization circuit 283 to restore the voice data and output the voice data.

As described above, the audio data is restored from the audio bitstream by the audio decoder 228.

In FIG. 16, the data decoder 229 decodes the data input via the data buffer 169 to restore the original data and output it.

Next, the operation of the embodiment thus constructed will be described with reference to FIGS. 19 to 21.

Using the spindle motor 231, the disk 23
Rotate the 0 and use the pickup 161 to
Read the data recorded on the upper track. The playback signal from the pickup 161 is amplified by the amplifier 233,
The waveform is equalized by the equalizer 235 and output as reproduction data from the data slicer 236. The PLL 239 reproduces a clock from the reproduced data and gives it to the demodulation circuit 238, and the demodulation circuit 238 demodulates the reproduced data using the reproduced clock. As a result, the data before the modulation process at the time of recording is restored.

The sector detection circuit 240 detects the sync signal and sector number of the demodulated data, corrects the error, and outputs the demodulated data. The demodulated data from the ECC 242 of the sector detection circuit 240 is supplied to the decoder system buffer 162,
It is output to the demultiplexer 163 under the control of the system buffer controller 248.

In the present embodiment, the output of the ECC 252 is also supplied to the pointer detection circuit 245. The pointer detection circuit 245 detects the code amount pointer from the demodulated data and supplies it to the kick track number determination circuit 237. Further, a detection signal indicating an overflow of the decoder system buffer 162 is also input from the overflow detection circuit 247 to the kick track number determination circuit 237.

FIG. 19 is a graph for explaining kick control in which the horizontal axis represents time and the vertical axis represents cumulative code amount.

At the time of recording, it is assumed that all the recording data are recorded in the disk 230 at the full capacity. Since the recording data is recorded at a variable rate, the recording capacity is different for each predetermined set time. FIG. 19 shows a change in the cumulative code amount at a predetermined set time T, and it is shown that the total recording capacity at the predetermined set time T is M. The polygonal line A shows the cumulative code amount of the recording data at the set time T, which coincides with the output cumulative code amount of the recording side multiplexer 30 (see FIG. 1) and the input cumulative code amount of the reproducing side demultiplexer 163. . The polygonal line B is a line parallel to the polygonal line A and is shifted by the capacity of the decoder system buffer 162. That is, the accumulated code amount that can be absorbed by the decoder system buffer 162 is shown.

The slanting broken line C in FIG. 19 indicates the disc peak rate in the slope, and the interval in the time axis direction is the disc 230.
The time μ required for one rotation is shown, and the timing of the broken line C is the timing at which the pickup 161 is on-track. Further, the position of each broken line C in the vertical axis direction corresponds to the position of the pickup 161 in the radial direction of the disk 230. Even if the pickup 161 is kicked during reproduction, a series of data can be continuously output by returning the pickup 161 to the original position after a time (rotation waiting time) that is an integral multiple of the time μ.

The number of rotations of the disk 230 is set so that the linear velocity is constant, and the pickup 161 always reproduces data at a constant peak rate. Therefore, it is possible to reproduce the data recorded at the variable rate by detecting the full state of the buffer holding the reproduction data, stopping the reading, and reading the signal in burst. When this reading is stopped, the pickup 161 is kicked.

Now, it is assumed that the pickup 161 starts reproduction at time t1 in FIG. Pickup 16
Since 1 reproduces the data at the peak rate, the reproduced accumulated code amount increases at the same slope as the broken line C, as indicated by the thick line D in FIG. On the other hand, the demodulated data based on the reproduced signal is sequentially output from the decoder system buffer 162 at time t2 in FIG. As shown in FIG. 19, since the recording data rate is lower than the peak rate, when the pickup 161 continuously reproduces data,
The decoder system buffer 162 overflows at time t3. Therefore, the pickup 161 is kicked for a predetermined rotation waiting time (2 μ in FIG. 19) from the time before the time t3.

In this embodiment, this pickup 16
A stable kick is possible by controlling the kick of 1 based on the code amount pointer. For example, when video data, audio data, and other data are all recorded at a variable rate, the recording rate of video data, audio data, and other data may be the peak rate, which is extremely high. The peak rate needs to be set. That is, in order to increase the peak rate, it is necessary to increase the relative speed between the pickup 161 and the track on the disk 230. That is, the rotation speed of the disk shaft is increased, and the rotation waiting time μ is extremely shortened. To do so, it is necessary to shorten the time required to perform on-track after performing a kick, and the mechanical limitation becomes large.

When kicking, the disc 23 is driven at a constant speed.
To stop the pickup 161 moving in the radial direction of 0 and return it to the next on-track,
Rock 161 several times in the radial direction. Therefore, the kick requires a predetermined operation time. However, as mentioned above, since it is necessary to set the rotational speed of the disk to be relatively high,
There is a problem that the rotation waiting time becomes short and the kick becomes difficult.

Therefore, in this embodiment, the degree of occupancy of the decoder system buffer 162 is calculated by using the code amount pointer to obtain the margin of the kick, and a stable kick is possible. FIG. 20 is a flow chart for explaining such a disc pickup operation.

That is, when the reproducing process is started, the pickup 161 is moved in step S1 of FIG. The pickup control circuit 234 moves the pickup 161 to the start position of the disc 230. In the next step S2, the pickup control circuit 23
4 achieves tracking by swinging the pickup 161 several times in the disk radial direction. When the on-track processing is completed, reproduction is started in the next step S3 and the demodulated data is written in the decoder system buffer 162 (step S4).

On the other hand, the pointer detection circuit 245 detects the code amount pointer in step S5. In FIG. 19, the code amount pointer is indicated by the black circles on the broken line A and the thick line D. In the recording processing circuit 31 shown in FIG. 6, the pointer indicating the generated code amount per predetermined time is recorded as the code amount pointer, but the time information indicating the input timing to the multiplexer 132 may be recorded as the pointer. .

The code amount pointer is also written in the decoder system buffer 162. System buffer controller
248 confirms the initial value of the decoder system buffer 162 in step S6, and reads the data accumulated by the code amount indicated by the pointer (step S7). FIG.
Indicates the pointer detection timing by P1, P2, ..., And the output timing of the decoder system buffer 162 is indicated by D1, D2 ,. In the next step S8, the amount of data stored in the decoder system buffer 162 is detected, and in step S9 it is detected whether the decoder system buffer 162 overflows.
As described above, since the decoder system buffer 162 overflows at the timing of time t3, this time t3 is exceeded.
The reproduction is stopped before 3, and the writing to the decoder system buffer 162 is stopped (step S10).

On the other hand, the pointer detection circuit 245 outputs the detected code amount pointer to the kick track number determination circuit 237 for kick processing. Kick track number determination circuit
In step S11, the 237 calculates the kick timing margin for the next kick from the detected code amount pointer. When the pickup 161 is kicked to the next reproduction state, it is necessary to prevent the decoder system buffer 162 from overflowing or underflowing. As shown in FIG.
On track may be made to any one of 1, C2 and C3. Therefore, in this case, there is a maximum kick timing margin of about 3μ.

As described above, in this case, there are three possible on-track timings after the kick. The kick track number determination circuit 237 determines the kick position (kick track number) in step S12. FIG. 21 is an explanatory diagram showing the relationship between the kick margin and the tracking stability.

For example, when the kick is made at the timing of time t4 in FIG. 19, the on-track may be made at the timings of broken lines C4, C5, C6. That is, in this case, the time available for kicking is about 1 μ, 2 μ, and 3 μ. FIG. 21 shows the tracking stability in these cases. Dashed line C4 with short usable time for kick
When on-tracking is performed at the timing of, the kick becomes unstable and tracking is not always performed well. On the contrary, the broken line C6 has a long usable time for kicking.
When the on-track is performed at the timing of, stable tracking is possible.

The kick track number determination circuit 237 determines the kick track number in consideration of the tracking stability.
In the case of FIG. 19, the kick track number determination circuit 237 outputs a signal for on-tracking at the timing of the broken line C2. In the next step S13, the pickup control circuit 234 moves the pickup 161 to perform kick processing. When the kick ends, the pickup control circuit 234 returns the processing to step S2 and turns on the pickup 161 at the timing of the broken line C2.

Thereafter, the same operation is repeated, and the pickup 161 is kicked based on the detected pointer, so that the code amount of the reproduced data is changed to the decoder system buffer.
Playback is performed while suppressing the code amount that can be absorbed by 162. The output of the decoder system buffer 162 is the demultiplexer 1
Supplied to 63.

The demultiplexer 163 separates the output of the decoder system buffer 162 into a video coded output, a voice coded output and a data coded output, and outputs them to the video buffer 16 respectively.
7, through the audio buffer 168 and the data buffer 169 to supply to the video decoder 227, the audio decoder 228 and the data decoder 229. The video coded output, the audio coded output and the data coded output are decoded by the video decoder 227, the audio decoder 228 and the data decoder 229, respectively, and the video data, the audio data and other data are restored.

As described above, the present embodiment has the advantage that the kick of the pickup can be stabilized even when the number of rotations of the disc is set high. .

Next, the rate control will be described with reference to FIGS. 9 and 22 and 23 showing the recording disk production system and the variable rate expansion device. FIG.
23 and FIG. 23 show time on the horizontal axis and the cumulative generated code amount on the vertical axis, and FIG. 22 shows the storage means 76, 106 on the recording side.
, 127 and the input / output of the multiplexer 30, and FIG. 23 shows the encoder system buffer 162 and the demultiplexer 16
3 inputs and outputs are shown.

FIGS. 22 (a) to 22 (c) respectively show the cumulative generated code amount of the data coded output, the voice coded output and the video coded output which are inputted to the storage means 127, 106 and 76 of FIG. 22 (d) shows the output accumulated code amount of the multiplexer 30 of FIG.

FIG. 22 (a) shows the accumulated generated code amount of the data encoded output, that is, the accumulated generated code amount of the input of the storage means 127 (data encoder buffer) by the polygonal line 301. An alternate long and short dash line 302 parallel to the polygonal line 301 indicates the code amount that can be stored in the storage means 127. The capacity of the storage means 127 is BS3 '. Line 303 is a storage means
It shows the cumulative amount of generated codes of the output from 127. Broken line
The storage means 127 outputs the accumulated data encoded output only in the thick line portion of 303, and at other timings, the data encoded output is not output and the accumulated code amount does not change. Further, the code amounts of the data output from the storage means 127 in the thick line portion are d1, d2, d3, ....

FIG. 22 (b) shows, by a polygonal line 311, the accumulated generated code amount of the speech encoded output, that is, the accumulated generated code amount of the input of the storage means 106 (speech encoder buffer). The alternate long and short dash line 312 parallel to the polygonal line 311 indicates the storage means 10.
6 shows the storable code amount. The storage means 10
The capacity of 6 is BS2 '. The polygonal line 313 is the storage means 106.
5 shows the cumulative amount of generated codes of the output from. Line 313
The storage means 106 outputs the accumulated voice coded output only in the thick line portion of, and the voice coded output is not output at other timings, and the accumulated code amount does not change. Further, the code amounts of the data output from the storage means 106 in the thick line portion are a1, a2, a3, ....

FIG. 22 (c) shows, by a polygonal line 321, the cumulative generated code amount of the video encoded output, that is, the cumulative generated code amount of the input of the storage means 76 (the video encoder buffer). An alternate long and short dash line 323 parallel to the polygonal line 321 indicates the code amount that can be stored in the storage means 76. The storage means 76 has a capacity of BS1 '. A polygonal line 323 shows the cumulative generated code amount of the output from the storage means 76. Only in the thick line portion of the broken line 323, the storage means 76 outputs the accumulated video coded output, and at other timings, the video coded output is not output and the accumulated code amount does not change. Further, the code amount of the data output by the storage means 76 in the bold line portion is v1,
v2, v3, ...

FIG. 22D shows the accumulated generated code amount of the output of the multiplexer 30 by the broken line 331. The multiplexer 30 time-divisionally multiplexes the outputs of the storage means 127, 106, 76, and d1, a1, v1, d2, a in the figure.
2, v2, ... Show the output code amounts of the storage means 127, 106, 76.

FIG. 23A shows the accumulated generated code amount of the input of the demultiplexer 163 by the broken line 341.
23B to 23D respectively show the data buffer 16 of FIG.
9, the cumulative generated code amount of the inputs of the audio buffer 168 and the video buffer 167 is shown.

The demultiplexer 163 shown in FIG. 23 (a).
The code amount d1, a1, v1, d2 of the data input to
a2, v2, ... Are the same as the code amount of the polygonal line 331 in FIG. The demultiplexer 163 separates the input data into other data, audio data and video data, and supplies them to the data buffer 169, audio buffer 168 and video buffer 167, respectively. The accumulated generated code amounts of the inputs of the data buffer 169, the audio buffer 168, and the video buffer 167 are polygonal lines 351, 361, and 371 of FIGS. 23B to 23C, respectively.
Shown by These polygonal lines 351, 361, 371 showing the input accumulated generated code amounts of the respective buffers 169 to 167.
22 has the same shape as the polygonal lines 303 3, 303 and 323 of FIGS. 22A to 22C showing the output accumulated code amount of the encoder buffer.

An alternate long and short dash line 352 parallel to the polygonal line 351 in FIG. 23B shows the code amount that can be stored in the data buffer 169. The capacity of the data buffer 169 is BS3. A polygonal line 353 represents the cumulative amount of generated codes of the output from the data buffer 169. This polygonal line 353 showing the output cumulatively generated code amount has the same shape as the polygonal line 301 showing the input cumulatively generated code amount of the recording side storage means 127. This allows the data decoder 229 (see FIG. 16) to decode other data in real time.

An alternate long and short dash line 362 parallel to the polygonal line 361 in FIG. 23C shows the code amount that can be stored in the audio buffer 168. The capacity of the audio buffer 168 is BS2.
A polygonal line 363 shows the cumulative amount of generated codes of the output from the voice buffer 168. The polygonal line 363 indicating the output cumulatively generated code amount has the same shape as the polygonal line 311 indicating the input cumulatively generated code amount of the recording side storage means 106. This allows the audio decoder 228 to decode the audio data in real time.

An alternate long and short dash line 372 parallel to the polygonal line 371 in FIG. 23D shows the code amount that can be stored in the video buffer 167. The capacity of the video buffer 167 is BS1.
A polygonal line 373 represents the cumulative amount of generated codes of the output from the video buffer 167. The polygonal line 373 indicating the output cumulatively generated code amount has the same shape as the polygonal line 321 indicating the input cumulatively generated code amount of the recording side storage means 76. This allows the video decoder 227 to decode the video data in real time.

By the way, when recording and reproducing at a variable rate, it is necessary to make the buffer capacity on the decoder side larger than the buffer capacity on the encoder side by the amount that absorbs the maximum rate margin of the variable rate. That is, the capacity of the decoder buffer BS1, BS2, BS3 (BSn)
And the encoder buffer capacities BS1 ', BS2', B
By comparing with S3 '(BSn'), the following expression (5) is established.

BSn ′ <BSn (5) Further, it is necessary that overflow or underflow does not occur in each encoder buffer and each decoder buffer. That is, in FIG. 22, the polygonal line 303 is present between the polygonal lines 301 and 302, and the polygonal line 313 is the polygonal line 311 and
It must be between the lines 312 and the line 323 must be between the lines 321 and 322. In addition, in FIG. 23, the polygonal line 353 exists between the polygonal lines 351 and 352, and the polygonal line 363
Exists between the polygonal lines 361 and 362, and the polygonal line 373 exists.
It must be between 371 and 372.

[0237]

As described above, according to the present invention, the processing time can be remarkably shortened and a stable kick can be achieved during reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a recording disk production system in which a variable rate compression device according to an embodiment of the present invention is incorporated.

FIG. 2 is a block diagram showing a specific configuration of studio equipment 21 in FIG.

FIG. 3 is a video peak rate analysis circuit 22 and a video compression circuit.
27 is a block diagram showing a video encoder 50 constituted by 27. FIG.

FIG. 4 is a voice peak rate analysis circuit 23 and a voice compression circuit.
28 is a block diagram showing a specific configuration of a voice encoder 91 configured by 28. FIG.

FIG. 5 is a block diagram showing a specific configuration of a data encoder 120 including a data peak rate analysis circuit 24 and a data compression circuit 29.

FIG. 6 is a recording processing circuit 31 and a cutting device in FIG.
The block diagram which shows the concrete structure of 32.

7 is a block diagram showing a specific configuration of a system controller 25 in FIG.

FIG. 8 is a graph for explaining the operation of the embodiment.

FIG. 9 is a block diagram showing a recording disk production system and a variable rate expansion device in a simplified manner.

FIG. 10 is a graph showing the estimated value of the analyzed peak rate, with the code amount on the vertical axis.

[FIG. 11] Peak rate calculation period (t0 to t1) on the horizontal axis
A graph for explaining various rates and buffer states by taking the generated code amount on the vertical axis.

FIG. 12 is a block diagram showing a system code amount distribution circuit and a video code amount control circuit used in a variable rate compression apparatus according to another embodiment of the present invention.

FIG. 13 is a graph for explaining the control of the quantization level based on the average rate and the actual generated cumulative code amount.

FIG. 14 is a graph for explaining the operation of the embodiment of FIG.

FIG. 15 is an explanatory diagram showing a relationship between an output rate and a buffer capacity.

FIG. 16 is a block diagram showing a variable rate decompression device according to an embodiment of the present invention.

17 is a block diagram showing a specific configuration of the video decoder shown in FIG.

18 is a block diagram showing a specific configuration of the audio decoder 228 in FIG.

FIG. 19 is a graph for explaining kick control in which the horizontal axis represents time and the vertical axis represents cumulative code amount.

FIG. 20 is a flowchart for explaining a disc pickup operation.

FIG. 21 is an explanatory diagram showing the relationship between kick margin and tracking stability.

FIG. 22 is a graph for explaining rate control.

FIG. 23 is a graph for explaining rate control.

FIG. 24 is a block diagram showing a compression device in a conventional example.

[Explanation of symbols]

22 ... Video peak rate analysis circuit, 23 ... Audio peak rate analysis circuit, 24 ... Data peak rate analysis circuit, 25 ... System control device, 27 ... Video compression circuit, 28 ... Audio compression circuit,
29 ... Data compression circuit, 30 ... Multiplexer, 50 ... Video encoder, 91 ... Audio encoder, 120 ... Data encoder

Claims (21)

[Claims] 1. A coding means for coding input data to output at a variable rate, and the code by approximating a code amount when the input data is coded by the coding means every predetermined period. Rate analysis means for analyzing the output rate of the encoding means before the encoding processing and outputting it as an approximate rate; and if the estimated rate exceeds the peak rate allowed for the output of the encoding means, the encoding And a peak rate control means for suppressing the output rate of the encoded output to a peak rate or less by increasing the compression rate of the means. 2. The variable rate compression device according to claim 1, wherein the input data is at least one kind of data of video data, audio data, and other data. 3. The variable rate compression apparatus according to claim 1, wherein the rate analyzing unit sets a period that is an integral multiple of 1 GOP period as the predetermined period. 4. The variable rate compression apparatus according to claim 1, wherein the encoding means has a buffer capable of smoothing a capacity corresponding to the predetermined period. 5. The rate analyzing means, when the input data is video data, obtains the approximate rate based on at least one of an activity, a scene change and a motion vector of the video data. The variable rate compression device according to claim 1, wherein the variable rate compression device is a variable rate compression device. 6. The rate analyzing means, when the input data is voice data, vowels of the voice data,
The variable rate compression device according to claim 1, wherein the approximate rate is obtained based on a consonant and a background sound. 7. The variable according to claim 1, wherein, when the input data is other data, the rate analyzing unit obtains the approximate rate based on the content of the input data. Rate compression device. 8. The peak rate control means allows the estimated rate to the output of the encoding means by comparing the accumulated generated code quantity of the output of the encoding means with the accumulated generated code quantity based on the estimated rate. The variable rate compression device according to claim 1, wherein it is determined whether or not the peak rate is exceeded. 9. Coding means for coding input data and outputting it at a variable rate, and output of the coding means by approximating a code amount when the input data is coded by the coding means. Rate analyzing means for analyzing the rate before the encoding processing and outputting it as an approximate rate; and a compression rate of the encoding means when the approximate rate exceeds a peak rate allowed for the output of the encoding means. A peak rate control unit for increasing the output rate of the encoded output to a peak rate or less, a storage unit for storing the output of the encoding unit, and the input data or the data stored in the storage unit. And a re-encoding means for re-encoding a part and outputting the re-encoded part. 10. The re-encoding unit performs re-encoding when the total code amount of the output of the encoding unit exceeds a predetermined set code amount so that the total code amount is less than or equal to the predetermined set code amount. The variable rate compression device according to claim 9, wherein the variable rate compression device is suppressed. 11. Coding means for coding input data and outputting it at a variable rate, and output of the coding means by approximating a code amount when the input data is coded by the coding means. Rate analyzing means for analyzing the rate before the encoding processing and outputting it as an approximate rate; and a compression rate of the encoding means when the approximate rate exceeds a peak rate allowed for the output of the encoding means. The peak rate control means for increasing the output rate of the encoded output to a peak rate or less, and the average rate based on the output rate of the encoding means and the allowable total code amount allowed for the output of the encoding means. And an average rate control means for changing the compression rate of the encoding means based on the difference between the above and the total code amount of the output of the encoding means to correspond to the allowable total code amount. A variable rate compression device characterized in that 12. The average rate control means changes the compression rate based on the difference between the cumulative generated code amount of the output of the coding means and the cumulative generated code amount based on the average rate. The variable rate compression device according to claim 11. 13. Coding means for coding input data to output at a variable rate, and output of the coding means by approximating a code amount when the input data is coded in the coding means. Rate analyzing means for analyzing the rate before the encoding processing and outputting it as an approximate rate; and a compression rate of the encoding means when the approximate rate exceeds a peak rate allowed for the output of the encoding means. The peak rate control means for increasing the output rate of the encoded output to a peak rate or less, and the average rate based on the output rate of the encoding means and the allowable total code amount allowed for the output of the encoding means. An average rate control means for changing the compression rate of the encoding means based on the difference between the above and the total code amount of the output of the encoding means to correspond to the allowable total code amount; Variable rate compression, comprising: storage means for storing the output of the encoding means; and re-encoding means for re-encoding and outputting a part of the input data or the data stored in the storage means. apparatus. 14. Encoding means for respectively encoding a plurality of types of data, multiplexing means for multiplexing encoded outputs of the plurality of types of data from the encoding means and outputting at a variable rate, A code amount approximating means for approximating the code amount when each type of data is encoded by the encoding means and outputting each approximate value, and a sum of the approximate value for each predetermined period is output to the multiplexer. If the allowable maximum code amount per the predetermined period is exceeded, by controlling each compression rate for the plurality of types of data based on the type of the data, the encoded output of the predetermined period A variable rate compression device, comprising: a generated code amount suppressing means for suppressing a sum of output code amounts to be equal to or less than the allowable maximum code amount. 15. The variable rate compression device according to claim 14, wherein the generated code amount suppressing means controls the compression rate by weighting according to the type of the data. 16. The variable rate compression device according to claim 14, wherein the generated code amount suppressing means controls the compression rate by weighting based on the value of the plurality of types of data. 17. Coding means for coding input data and outputting it at a variable rate, and pointer adding means for adding a pointer to the output of this coded output to indicate the amount of generated code for each predetermined time and outputting it. A variable rate compression apparatus comprising: 18. Encoding means for encoding input data and outputting at a variable rate, and kick information of a pickup for reproducing the disc medium when the output of the encoded output is recorded on the disc medium. A variable rate compression device, comprising: kick information adding means for adding the kick information created based on the output rate of the encoding means to the output of the encoding means for output. 19. A reproducing means for reproducing by a pickup a disk on which a coded output to which a pointer indicating a code amount for every predetermined time is added is recorded at a variable rate, and a decoder for holding and outputting the output of the reproducing means. A buffer, pointer detection means for detecting the pointer from the reproduction signal of the reproduction means, and kicking of the pickup based on the pointer detected by the pointer detection means, thereby encoding the encoded output recorded on the disc. A variable rate decompression device comprising: pickup control means capable of reproducing at a reproduction rate corresponding to a recording rate. 20. The pickup control means, based on the occupancy of the decoder buffer and the pointer,
20. The variable rate expansion device according to claim 19, wherein the kick timing and the number of kick tracks of the pickup are determined. 21. The variable rate decompression apparatus according to claim 19, wherein the decoder buffer is set to have a capacity larger than a capacity of an encoder buffer used when recording the encoded output.