JPH08236766A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Objective] In a method of manufacturing a MOSFET having a channel portion on the side surface of a groove, firstly, to obtain a manufacturing method which does not introduce defects or contaminants into the channel portion, and secondly, It is to obtain a manufacturing method that can make the shape uniform. [Structure] An n ⁻ type epitaxial layer 2 having a low impurity concentration is formed on one main surface side of an n ⁺ type semiconductor substrate 1, and a predetermined region thereof is subjected to chemical dry etching with this surface as a main surface. A region including the surface generated by the chemical dry etching is selectively oxidized to form a selective oxide film having a predetermined thickness. After that, p-type and n-type impurities are doubly diffused from the main surface, and the channel length is defined by this doubly diffused, and at the same time, a base layer and a source layer are formed. Further, the n ⁺ type semiconductor substrate 1 is used as a drain layer. After this double diffusion, the gate electrode is formed through the gate oxide film and the source,
A drain electrode is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used as a power semiconductor element, that is, a vertical MOSFET (M
(etal Oxide Semiconductor Field Effect Transistor)
And IGBT (Insulated Gate Bipolar Transistor)
It is suitable to adopt the manufacturing method (1) as a single unit or a MOSIC or the like incorporating a power semiconductor element.

[0002]

2. Description of the Related Art Vertical power MOSFETs have been used in many industrial fields in recent years because they have many characteristics such as excellent frequency characteristics, fast switching speed, and low power consumption. For example, in the May 19, 1986 issue of Nikkei Electronics, published by Nikkei McGraw-Hill, pp.165-188, it is stated that the focus of power MOSFET development is shifting to low withstand voltage products and high withstand voltage products. There is. Further, this document describes that the on-resistance of a power MOSFET chip having a withstand voltage of 100 V or less is reduced to the level of 10 mΩ, which is because microfabrication of LSI is used for manufacturing the power MOSFET. It is stated that the channel width per unit area can be increased by devising the shape of the cell. Further, in this document, a vertical type power MOSFET using a DMOS type (double diffusion type) cell which is the mainstream is mainly mentioned. The reason is that the DMOS type is manufactured by a planar process which is characterized in that the flat main surface of a silicon wafer is used as it is for the channel portion, and therefore has a manufacturing advantage that the yield is high and the cost is low. .

On the other hand, with the spread of vertical power MOSFETs, there is a demand for further reduction in loss and cost.
Reducing the on-resistance by microfabrication and devising the cell shape has reached its limit. For example, according to Japanese Patent Laid-Open No. 63-266882, the DMOS type has a minimum point at which the on-resistance does not decrease further even if the size of the unit cell is reduced by microfabrication, and the main cause is the on-resistance component. It has been found to be an increase in JFET resistance. Further, in the DMOS type, as shown in Japanese Patent Application Laid-Open No. 2-86136, under the current microfabrication technology, the size of the unit cell where the on-resistance has a minimum point is around 15 μm.

Various structures have been proposed to overcome this limitation. A feature common to them is a structure in which a groove is formed on the device surface and a channel portion is formed on the side surface of the groove. This structure can greatly reduce the JFET resistance. Further, in the structure in which the channel portion is formed on the side surface of the groove, the increase in JFET resistance can be ignored even if the unit cell size is reduced, and therefore, as described in JP-A-63-266882. There is no limit that the on-resistance takes a minimum point with respect to the reduction of the unit cell size, and it can be reduced to 15 μm or less to the limit of fine processing.

As a conventional manufacturing method of the structure in which the channel portion is formed on the side surface of the groove as described above, for example, Japanese Patent Laid-Open No. 61-19966.
As disclosed in Japanese Patent Publication No. 6, there is one in which a groove is formed by RIE and a channel portion is formed on the side surface of the groove. here,
RIE is a physical etching with excellent process controllability. That is, in RIE, when electrodes are arranged above and below a semiconductor device placed in a gas atmosphere and high-frequency power is applied between the electrodes, the gas is ionized into electrons and ions. Cathode drop occurs in the upper part of the semiconductor device due to a large difference in mobility of electrons and ions between the electrodes. Then, an electric field is generated by this cathode fall, and the electric field accelerates toward the ion semiconductor device, physically collides with the surface to be etched, and the energy is used to etch the semiconductor device. Since RIE accelerates the ionized gas, the absolute value on the semiconductor device is 10 V to
High frequency power is applied between the electrodes so that a cathode drop of about 500 V occurs. In RIE, since ionized gas is accelerated in a certain direction, it has a characteristic that it has very excellent anisotropy and side etching is unlikely to occur. However, in RIE, a gas that is physically ionized collides with a semiconductor device, so that lattice defects are inevitably generated on the etched surface, and surface recombination occurs, which lowers the mobility and consequently the on-resistance. There is a problem that is increased.

As a manufacturing method in which lattice defects are less likely to occur, there is a manufacturing method using wet etching as disclosed in, for example, International Publication WO93 / 03502 and Japanese Patent Laid-Open No. 62-12167. FIG. 23 shows a MOSF disclosed in WO93 / 03502.
24 to 35 are sectional views of the ET, and FIGS. 24 to 35 are sectional views showing the manufacturing process of the MOSFET in the publication. The manufacturing process will be briefly described below.

First, as shown in FIG. 24, a wafer 21 having an n ⁻ type epitaxial layer 2 grown on a main surface of a semiconductor substrate 1 made of n ⁺ type silicon is prepared. The semiconductor substrate 1 has an impurity concentration of about 10 ²⁰ cm ^-3 . The epitaxial layer 2 has a thickness of 7 μm.
At about m, the impurity concentration is about 10 ¹⁶ cm ^-3 . The main surface of the wafer 21 is thermally oxidized to a thickness of 60n.
A field oxide film 60 having a thickness of about m is formed, a resist film 61 is then deposited, and the resist film 61 is formed by a known photolithography process into a pattern having an opening at the center of a cell formation planned position.
Pattern. Then, boron (B ⁺ ) is ion-implanted using the resist film 61 as a mask.

After stripping the resist, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 finally becomes a part of the p-type base layer 16 described later, and when a high voltage is applied between the drain and the source, the p-type diffusion layer 62 stably breaks down at the bottom. Raising it fulfills the purpose of improving surge resistance.

Next, as shown in FIG. 25, a silicon nitride film 63 is deposited on the main surface of the wafer 21 to a thickness of about 200 nm, and the silicon nitride film 63 is patterned to have a pitch width (dimension of the unit cell 15) a. A grid-like opening pattern for opening is formed. The opening pattern is masked so that the p-type diffusion layer 62 described above is located at the center of the pitch interval.

Next, as shown in FIG. 26, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and the n ^-- type epitaxial layer 2 is continuously formed to a depth of 1.
A groove 64 is formed by wet etching for about 5 μm.
Next, as shown in FIG. 27, the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask. This is LOCOS
This is a well-known oxidation method known as the (Local Oxidation of Silicon) method.
The COS oxide film 65 is formed, and at the same time, the U groove 50 is formed on the surface of the n ⁻ type epitaxial layer 2 which is eaten by the LOCOS oxide film 65, and the shape of the groove 50 is determined.

Next, as shown in FIG. 28, boron is ion-implanted to form the p-type base layer 16 through the thin field oxide film 60 using the LOCOS oxide film 65 as a mask. At this time, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position,
The region to be ion-implanted is precisely defined. Next, FIG.
As shown in FIG. 9, heat is diffused to a junction depth of about 3 μm.
By this thermal diffusion, the p-type diffusion layer 62 previously formed in the step shown in FIG. 25 and the boron diffusion layer implanted in the step shown in FIG. 28 are integrated to form one p-type base layer 16. Further, both end faces of the region of the p-type base layer 16 are defined by the positions of the side walls of the U groove 50 in a self-aligned manner.

Next, as shown in FIG. 30, patterning is performed with a pattern left in the central portion of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a grid pattern. Using both the resist film 66 and the LOCOS oxide film 65 as a mask, phosphorus is ion-implanted through the thin field oxide film 60 to form the n ⁺ -type source layer 4. In this case as well, similar to the case where boron is ion-implanted in the step shown in FIG. 28, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 becomes a self-aligned position, and the ion-implanted region is accurately defined.

Next, as shown in FIG. 31, a junction depth of 0.
Heat diffusion is performed for 5 to 1 μm to form the n ⁺ type source layer 4, and at the same time, the channel 5 is set. In this thermal diffusion, the end surface in contact with the U groove 50 in the region of the n ⁺ type source layer 4 has a U groove 50.
Is defined in a self-aligned manner at the position of the side wall. 28
~ The junction depth of the p-type base layer 16 and its shape are determined by the process of FIG.

Next, as shown in FIG. 32, the LOCOS oxide film 65 is removed by wet etching to remove the U groove 50.
The inner wall 51 of the is exposed, and then thermal oxidation is performed to a thickness of 60 n.
A gate oxide film 8 of about m is formed. Next, as shown in FIG. 33, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of wafer 21.

Next, as shown in FIG. 34, boron is ion-implanted through the oxide film 67 using the patterned resist film 68 as a mask to form the p ⁺ -type base contact layer 17. Next, as shown in FIG. 35, a junction depth of about 0.5 μm is thermally diffused to form ap ⁺ type base contact layer 17.

Then, as shown in FIG.
BPSG (BoronPhosphate Silicate) on the main surface of Ha 21
Interlayer insulating film 18 made of glass) is formed on a part of it
Make contact holes p⁺Mold base contact layer 17
And n⁺The mold source layer 4 is exposed. In addition,
The source electrode 19 made of a film is formed, and the contact
P through the hole⁺Type base contact layer 17 and n⁺Type saw
And ohmic contact with the layer 4. In addition,
Silicon nitride for plasma film protection by plasma CVD
Forming a passivation film (not shown) of
In addition, a Ti / Ni / Au three-layer film is formed on the back surface of the wafer 21.
A drain electrode 20 composed of ⁺Type semiconductor substrate
Make ohmic contact with 1.

[0017]

However, the above-mentioned WO93 is used.
Since the manufacturing method disclosed in Japanese Patent Laid-Open No. 03502 or JP-A-62-12167 uses wet etching, which is isotropic etching, so-called side etching for etching to a desired width or more occurs, and Due to the unevenness, it is not possible to form a groove having a uniform and stable depth in the wafer surface, and there is a problem that the controllability of the process is poor.

Further, since the shape of the groove in the wafer surface is not uniform, there is a problem in that the electric characteristics of the FET vary widely. It is considered that the non-uniformity of the groove shape is due to the variation of the groove shape in the wafer surface in the etching process performed before the LOCOS oxidation. Channel groove, LOCOS
Although it may be possible to form only by oxidation, the introduction of defects into the channel portion increases due to the increase in LOCOS oxidation time,
Further, the angle of the side surface of the groove becomes about 30 degrees, which makes it impossible to miniaturize the cell and makes it impossible to expect a decrease in the on-voltage. Further, if the channel groove is formed only by LOCOS oxidation, the volume may be doubled when Si is oxidized, so that the channel portion may be distorted. Therefore, the etching step performed before the LOCOS oxidation, that is, the initial groove forming step is absolutely necessary.

From this point of view, the vertical MOSFET
In order to manufacture the semiconductor with a low on-voltage and while maintaining the uniformity of the electrical characteristics within the wafer surface, after the initial groove is formed, LOCOS oxidation is performed without introducing defects or contaminants into the channel portion, and L so that the shape is uniform on the wafer surface
It is necessary to remove the OCOS oxide film. However,
In the above publication, there is a problem that it is not possible to reduce the number of channel defects and accurately control the shape of the channel groove at the same time.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a method of manufacturing a MOSFET having a channel portion on the side surface of a groove, in which defects in the channel portion can be reduced and the shape of the groove can be accurately controlled, and a semiconductor device thereof.

[0021]

A method of manufacturing a semiconductor device according to claim 1, which is configured to achieve the above object, comprises:
A mask forming step of forming a mask having an opening in a predetermined region on the main surface of the semiconductor layer of the first conductivity type disposed on the semiconductor substrate, and chemical dry etching the semiconductor layer through the opening of the mask. , The semiconductor layer,
A chemical dry etching step of forming a first groove having an inlet portion wider than the opening, a bottom surface substantially parallel to the main surface, and a side surface connecting the inlet portion and the bottom surface; and the first groove By oxidizing the region containing
An oxidizing step of forming an oxide film having a predetermined thickness on the surface of the first groove; and introducing an impurity of the second conductivity type from the main surface side so as to include the semiconductor layer surface in contact with the oxide film. A second conductive type base layer is formed in the semiconductor layer, and a first conductive type impurity is introduced into the base layer from the main surface side to form a first conductive type source layer. Sometimes an impurity introducing step of forming a channel region on the sidewall of the base layer, and an oxide film removing step of removing the oxide film to form a second groove having a predetermined depth deeper than the first groove. Forming a gate electrode on at least the surface of the second groove between the source layer and the semiconductor layer via a gate insulating film, and forming a source electrode in electrical contact with the source layer and the base layer. A drain that makes electrical contact with the semiconductor substrate. It is characterized by comprising an electrode forming step of forming a down electrode.

The invention according to claim 2 which is configured to achieve the above object is characterized in that the chemical dry etching step in the invention according to claim 1 is an isotropic etching step. Further, the invention according to claim 3 configured to achieve the above object is the chemical dry etching step in the invention according to claim 1 or 2, wherein the chemical dry etching step is a gas system containing carbon tetrafluoride and oxygen. It is characterized by comprising an etching process.

Further, it is configured to achieve the above object.
The invention according to claim 4 relates to the invention according to claim 1 or claim 2.
In the invention, the chemical dry etching step is
Cl _Four, Cl₂, SF₆, CFCl₃, CF₂Cl₂,
CF₃Cl, CHF₃, C₂ClF_Five, F₂, NF₃,
BCl₃Gas system containing any one or more of
It is characterized by comprising an etching process.

According to the invention of claim 5 which is configured to achieve the above object, the chemical dry etching step of the inventions of claims 1 to 4 is characterized in that the chemical dry etching step is performed in an ionized gas atmosphere. It is characterized in that the cathode drop above the semiconductor layer is substantially absent. Further, the invention according to claim 6 configured to achieve the above object, the chemical dry etching step in the invention according to claims 1 to 4 is characterized in that the semiconductor layer is formed in an ionized gas atmosphere. It is characterized in that the absolute value of the cathode drop at the upper side is performed in a state of less than 10V.

According to a seventh aspect of the present invention configured to achieve the above object, the oxidizing step in the first to sixth aspects of the invention is characterized in that the region including the first groove is selectively oxidized. This comprises a selective oxidation step of forming a selective oxide film of a predetermined thickness between the surface of the first groove and the mask and the semiconductor substrate, and the impurity introduction step is performed on the selective oxide film. Impurities of the second conductivity type are introduced from the main surface side so as to include the surface of the semiconductor layer in contact with the semiconductor layer to form the second conductivity type base layer, and the main surface is formed in the base layer. The step of introducing the impurity of the first conductivity type from the side to form the source layer of the first conductivity type, and the step of removing the oxide film removes the selective oxide film, A second groove with a deeper predetermined depth It is characterized by comprising a selective oxide film removing step of forming.

According to the invention of claim 8 which is configured to achieve the above object, the selective oxidation step in the invention of claim 7 uses the mask formed in the mask forming step to selectively oxidize. It is characterized by doing.
Further, the invention according to claim 9 configured to achieve the above-mentioned object, the selective oxidation step in the invention according to claim 7 to claim 8, the surface of the first groove, and the mask and the It is characterized in that a selective oxide film having a predetermined thickness is formed between the semiconductor layer and the semiconductor layer.

According to a tenth aspect of the present invention configured to achieve the above object, the selective oxidation step in the invention according to the seventh to eighth aspects is the first step which is generated by the chemical dry etching step. By selectively oxidizing a region including the first groove, a first selective oxide film having a predetermined thickness is formed on the surface of the first groove, and the area between the mask and the semiconductor substrate is separated from the entrance portion. It is characterized by comprising a step of forming a second selective oxide film which becomes thinner.

According to the invention of claim 11 which is configured to achieve the above object, the step of removing the oxide film in the invention of claims 1 to 10 involves removing the surface of the oxide film in an aqueous solution. After the oxide film is removed while terminating with hydrogen to form a first groove having the predetermined depth,
It is characterized in that the step of oxidizing the surface of the first groove terminated with hydrogen in a gas containing oxygen to form a protective oxide film on the surface of the first groove.

According to the invention of claim 12 which is configured to achieve the above object, the step of removing the oxide film according to the invention of claim 11 comprises the step of removing the oxide film on the surface of the oxide film in an aqueous solution containing hydrofluoric acid. It is characterized in that the oxide film is removed while terminating the generated dangling bond with hydrogen. The invention according to claim 13 which is configured to achieve the above object, comprises a mask forming step of forming a mask having an opening in a predetermined region on the main surface of the first conductivity type semiconductor substrate; An etching step of etching the semiconductor substrate through an opening of a mask to form a first groove having an entrance portion wider than the opening in the semiconductor substrate, and selectively oxidizing a region including the first groove. Thereby, the surface of the first groove, the selective oxidation step of forming a selective oxide film having a predetermined thickness between the mask and the semiconductor substrate, and the surface of the semiconductor substrate in contact with the side surface of the selective oxide film are performed. A second conductivity type impurity is diffused from the main surface side so as to form a second conductivity type base layer, and a first conductivity type impurity is diffused from the main surface side into the base layer. 1 conductivity type A step of forming an impurity layer and forming a channel on the side wall of the base layer, and removing the selective oxide film while terminating the surface of the selective oxide film with hydrogen in an aqueous solution. After forming a second groove having a predetermined depth deeper than the groove, the surface of the second groove terminated with the hydrogen is oxidized in a gas containing oxygen to protect the surface of the second groove. A selective oxide film removing step of forming an oxide film for use, a gate electrode is formed on the surface of the second groove through the gate oxide film, and a source electrode electrically contacting the source layer and the base layer is formed. And an electrode forming step of forming a drain electrode in electrical contact with the other main surface side of the semiconductor substrate.

According to a fourteenth aspect of the invention configured to achieve the above object, the electrode forming step in the first to thirteenth aspects of the invention oxidizes an inner wall of the second groove. Forming a gate oxide film on the gate oxide film, forming a gate electrode on the gate oxide film, and forming a source electrode in electrical contact with both the source layer and the base layer. It is characterized by comprising a source / drain electrode forming step of forming a drain electrode electrically contacting the main surface side.

According to a fifteenth aspect of the invention configured to achieve the above object, the impurity introducing step according to the seventh aspect of the invention is the self-alignment with the selective oxide film. The base layer is formed on the surface of the first groove by diffusing the second conductivity type impurity from the main surface side, and the base layer is formed in the base layer from the main surface side in a self-aligning manner with the selective oxide film. The source layer is formed by diffusing an impurity of the first conductivity type.

According to a sixteenth aspect of the present invention, which is configured to achieve the above object, the oxide film removing step according to the first to fifteenth aspects of the invention is characterized in that at least the surface of the oxide film is exposed to light. It is characterized in that it is a step of removing the oxide film in a state where the irradiation is not performed. According to a seventeenth aspect of the invention, which is configured to achieve the above object, the semiconductor layer according to the first to sixteenth aspects is made of silicon, and the oxide film removing step further comprises the oxide film. Of removing the oxide film so that the surface orientation of the channel formation portion on the side surface of the second groove obtained by removing the oxide film is either the {110} surface or the {100} surface. I am trying.

According to the invention of claim 18 which is configured to achieve the above object, the semiconductor layer in the invention of claims 1 to 16 is made of silicon, and the oxide film removing step further comprises: The surface orientation of the channel forming portion on the side surface of the second groove obtained by removing the oxide film is {11
It is characterized in that it is a step of removing the oxide film so as to form a 1} plane.

According to a nineteenth aspect of the invention configured to achieve the above object, the oxide film removing step according to the eighteenth aspect of the invention is to remove the oxide film with a solution having a PH of more than 4. It is characterized by being a process. The semiconductor device according to claim 20, which is configured to achieve the above object, is formed on a semiconductor substrate of a first conductivity type and a main surface side of the semiconductor substrate, and is subjected to chemical dry etching and LOCOS after the chemical dry etching. An inlet having a predetermined inlet width, which is formed by applying oxidation, a bottom surface having a surface substantially parallel to the main surface,
And a second conductive type base layer formed to a predetermined depth from the main surface side and including a side surface of the groove portion, and a side surface that continuously connects the inlet and the bottom surface, and the base layer. Is formed on the main surface side in
A source layer for forming a channel region on the side surface of the groove portion, and a gate electrode formed in a region including the side surface and the bottom surface of the groove portion via a gate insulating film are provided.

According to a twenty-first aspect of the present invention, which is configured to achieve the above object, the groove portion of the semiconductor device according to the twentieth aspect has a depth of 1/2 or less of the entrance width from the main surface. It is characterized by having. Further, the invention according to claim 22 configured to achieve the above object is characterized in that the plane orientation of the semiconductor substrate of the semiconductor device according to any one of claims 20 to 21 is a {100} plane. There is.

Further, the invention according to claim 23, which is configured to achieve the above object, provides claims 20 to 22.
The semiconductor substrate of the semiconductor device according to, the base layer and the source layer are each made of silicon, and further, the plane orientation of the channel region on the side surface of the groove is:
It is characterized by being a {111} plane or a plane close to the {111} plane.

The invention according to claim 24, which is configured to achieve the above object, provides claims 20 to 21.
The semiconductor substrate of the semiconductor device according to, the base layer and the source layer are each made of silicon, and further, the plane orientation of the channel region on the side surface of the groove is:
{110} plane, plane close to {110} plane, {100} plane,
It is characterized in that it is one of the planes close to the {100} plane.

According to a twenty-fifth aspect of the invention configured to achieve the above object, the groove portion of the semiconductor device according to the twentieth aspect forms an initial groove by chemical dry etching the semiconductor substrate, After that, a region including the initial groove is oxidized to form an oxide film having a predetermined thickness on the surface of the initial groove, and the oxide film is removed by etching.

According to a twenty-sixth aspect of the present invention configured to achieve the above object, the groove portion of the semiconductor device according to the twentieth aspect has a bathtub shape.

[0040]

According to the first aspect of the present invention configured as described above, a predetermined region on the surface of the low-concentration semiconductor layer is removed by the chemical dry etching method before the selective oxidation. The chemical dry etching method is a kind of dry etching method and has high process controllability, uniform etching can be performed on the wafer surface, and reproducibility is also high. Further, in the chemical dry etching method, the damage given to the surface to be etched is relatively small in the dry etching process. Then, after this chemical dry etching, the surface of the first groove is oxidized. When oxidation is performed here, the state of the boundary surface between the resulting semiconductor layer and the oxide film differs depending on the surface of the first groove where the oxidation is started. That is, even if the surface etched by physical etching such as RIE is oxidized, the oxidation proceeds while the lattice defects are generated, and the resulting semiconductor layer has the lattice defects left. However, in the present invention, the first
By using the chemical dry etching method on the groove surface of No. 1, a first groove having a surface with few high defects is formed, and since the surface is oxidized, it is uniformly oxidized from the time when the oxidation is started, and the result is obtained. The surface of the second groove to be formed can also be a surface with few defects. Since the surface of the second groove is used as the channel region, low on-resistance can be obtained. Further, in order to form the second groove as the groove for the channel region, a two-step process of chemical dry etching and oxidation is performed. Therefore, when it is desired to obtain the second groove having a desired width, the oxidation is performed. Since it is only necessary to control the width of the groove, it is possible to accurately control the groove shape.

According to the second aspect of the invention, since the chemical dry etching process is isotropic, the first groove has no corners, and thus the second groove formed by oxidation is formed.
There are no corners in the groove. Therefore, the breakdown voltage between the drain and the source is improved. Further, according to the invention of claim 3, since the chemical dry etching step includes carbon tetrafluoride and oxygen in the gas, the process can be performed accurately and with good reproducibility by the ratio of carbon tetrafluoride and oxygen. .

According to the invention of claim 4, the chemi
Cal dry etching process uses CCl_Four, Cl₂, SF
₆, CFCl₃, CF₂Cl₂, CF₃Cl, CH
F₃, C ₂ClF_Five, F₂, NF₃, BCl₃What's in
Etching with a gas system containing one or more of them
Therefore, etching can be performed efficiently. Also bill
According to the invention of Item 5, the chemical dry etching process is performed.
And substantially no cathode fall above the semiconductor layer
Therefore, the ionized gas causes defects on the semiconductor layer surface.
It does not collide at such a speed. Because of this, the shape
The surface of the first groove formed should be a surface with very few defects.
Can be

According to the sixth aspect of the present invention, the chemical dry etching step is performed in an ionized gas atmosphere in a state where the absolute value of the cathode drop above the semiconductor layer is less than 10V. Therefore, the ionized gas does not collide with the surface of the semiconductor layer at a speed enough to cause a defect. Therefore, the surface of the formed first groove can be a surface with very few defects. Further, according to the invention of claim 7 having the above structure, since the oxidation step is a selective oxidation step of selectively oxidizing the first groove, the depth of the first groove can be increased.

According to the invention of claim 8 having the above structure,
Since the mask used in the chemical dry etching process is used as it is as the mask in the selective oxidation process, it is not necessary to form a new mask and alignment is not necessary.
According to the inventions of claims 9 and 10 having the above-mentioned configuration,
A selective oxide film having a predetermined thickness can be formed.

According to the eleventh aspect of the invention configured as described above, the step of removing the oxide film to expose the channel region after the oxidation step is performed by dangling bond on the surface of the semiconductor layer in an aqueous solution. Is terminated with hydrogen. As a result, the dangling bond having high reaction activity reacts with hydrogen before reacting with the pollutant and becomes stable, so that the reaction between the pollutant and the semiconductor layer can be prevented.
Then, when exposed to oxygen, a more stable oxide film is formed to protect the surface of the second groove, so that subsequent contamination of the channel region can be avoided, so that high channel mobility is obtained and low on-voltage is obtained. be able to.

According to the twelfth aspect of the invention configured as described above, since the oxide film is removed in an aqueous solution containing hydrofluoric acid, the selectivity ratio between the oxide film to be removed and the semiconductor layer to be left is set. Since it can be taken very large, the oxide film can be removed without damaging the surface of the semiconductor layer. Further, according to the invention of claim 13 configured as described above, the step of removing the oxide film to expose the channel region after the oxidation step is performed by hydrogenating the dangling bond on the surface of the semiconductor layer in an aqueous solution. Do it while terminating. This allows
The dangling bond having high reaction activity reacts with hydrogen before reacting with the contaminant and becomes stable, so that the reaction between the contaminant and the semiconductor layer can be prevented. Then, when exposed to oxygen, a more stable oxide film is formed to protect the surface of the second groove, so that subsequent contamination of the channel region can be avoided, so that high channel mobility is obtained and low on-voltage is obtained. be able to.

According to the fifteenth aspect of the present invention, since the base layer and the source layer are formed in self-alignment with the selective oxide film, alignment is unnecessary. Therefore, the base layer and the source layer can be formed at accurate positions, and the area of the device can be reduced. Further, according to the invention of claim 16 configured as described above, the surface of the oxide film is not irradiated with light during the removal of the oxide film, so that the semiconductor layer serving as a channel region is formed through the oxide film. It will not be illuminated by light. Therefore, the potentials of the first-conductivity-type source layer and the second-conductivity-type base layer in the vicinity of the channel region become substantially equal to each other, it is possible to prevent local progress of etching, and to perform uniform etching. it can. As a result,
A flat channel region can be obtained and high mobility can be obtained.

Further, claim 17 configured as described above.
According to the invention described above, the plane orientations of the side surfaces of the second groove obtained by removing the selective oxide film are the {110} plane and the {100} plane. This results in atomically flat sides in silicon. Therefore, high channel mobility can be obtained. According to the eighteenth aspect of the invention configured as described above, the plane orientation of the side surface of the second groove obtained by removing the selective oxide film is the {111} plane.
The silicon atoms on the side surface are terminated by one hydrogen atom, and an atomically flat side surface is obtained. Therefore, high channel mobility can be obtained.

Further, claim 19 configured as described above.
According to the above-mentioned invention, the step of removing the oxide film is performed with the pH of 4 or less.
Since it is performed in the above aqueous solution, the rate at which silicon atoms on the side surface of the second groove are terminated by one hydrogen atom is further increased, an atomically flat {111} plane is obtained, and high channel mobility is obtained. be able to. Further, according to the semiconductor device of the present invention configured as described above, since the groove portion is formed by chemical dry etching and LOCOS oxidation after the chemical dry etching, a defect in a portion to be a channel region is formed. Is very small and the surface of the channel region is very smooth, so that it is possible to prevent a decrease in carrier mobility in the channel region. As a result, a semiconductor device having an extremely low on-resistance can be obtained.

According to the twenty-first aspect of the present invention, the groove portion has a depth of ½ or less of the entrance width from the main surface, so that stress at the interface between the gate insulating film and the channel region is increased. Is less likely to be applied. This makes it difficult for lattice defects to occur in the channel region, and prevents the on-resistance from decreasing. Further, according to the invention of claim 23, since the plane orientation of the channel region is the {111} plane or a plane close to the {111} plane, it is possible to prevent the phonon scattering from decreasing and the ON resistance from decreasing.

According to the twenty-fourth aspect of the present invention, the plane orientation of the channel region is either the {110} plane, the plane close to the {110} plane, the {100} plane, or the plane close to the {100} plane. Since it is a surface, it is possible to prevent phonon scattering from decreasing and the ON resistance from decreasing. Furthermore, according to the twenty-fifth aspect of the present invention, it is possible to prevent the occurrence of lattice defects in the channel region and prevent the on-resistance from decreasing.

Further, according to the invention of claim 26,
Lattice defects are less likely to occur in the channel region, and it is possible to prevent the on-resistance from decreasing.

[0053]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a plan view of a vertical power MOSFET including a square unit cell according to the first embodiment of the present invention, and FIG. 1B is a sectional view taken along line AA in FIG. 2 to 22 are also vertical power MOSFs.
It is explanatory drawing in each stage in manufacture of ET. Further, FIG. 4 is a cross-sectional view of a wafer in which boron ions are implanted to form a central portion of a p-type base layer, and FIG. 5 is a cross-section of a wafer in which a silicon nitride film is patterned at intervals of unit cell size a for LOCOS oxidation. FIG. 8 is a cross-sectional view of a wafer on which a LOCOS oxide film is formed. FIG. 9 is a cross-sectional view of a wafer on which boron ions are implanted to form a p-type base layer using the LOCOS oxide film as a mask. FIG. 11 is a sectional view of a wafer on which a p-type base layer is formed.
A cross-sectional view of a wafer in which phosphorus ions are implanted to form an n ⁺ -type source layer using an oxide film as a mask, FIG. 12 is a cross-sectional view of a wafer in which an n ⁺ -type source layer is formed by thermal diffusion, and FIG. 18 is a LOCOS oxide film removed. 21 is a sectional view of a wafer in which a gate oxide film is formed by thermal oxidation after that, FIG. 19 is a sectional view of a wafer in which a gate electrode is formed on the gate oxide film, FIG.
Is a cross-sectional view of a wafer into which boron ions have been implanted to form a p ⁺ -type base contact layer, and FIG. 22 shows p ⁺ by thermal diffusion.
FIG. 1B is a sectional view of the wafer on which the mold base contact layer is formed, and FIG. 1B is a completed sectional view of the wafer on which the interlayer insulating film, the source electrode and the drain electrode are formed.

The vertical power MOSFET of this embodiment is
A main part thereof, that is, a unit cell portion has a structure as shown in FIG. 1, and a large number of unit cells 15 are regularly arranged in a vertical and horizontal plane in a pitch width (unit cell size) a. In FIG. 1, the wafer 21 has an impurity concentration of about 10 ²⁰ cm ⁻³ and a thickness of 100 to 300 μm.
The n ⁻ type epitaxial layer 2 having an impurity density of about 10 ¹⁶ cm ^{−3 and} a thickness of about 7 μm is formed on the semiconductor substrate 1 made of n ⁺ type silicon, and the unit cell is formed on the main surface of the wafer 21. 15 are configured. A U-shaped groove 50 is formed on the main surface of the wafer 21 with a unit cell size a of about 12 μm.
In order to form the p-type base layer 16 having a junction depth of about 3 μm, a LOCOS oxide film having a thickness of about 3 μm is formed, and the oxide film is used as a mask to perform self-aligned double diffusion.
And an n ⁺ type source layer 4 having a junction depth of about 1 μm are formed, whereby the channel 5 is set on the side wall portion 51 of the U groove 50. The junction depth of the p-type base layer 16 is set to a depth that does not cause breakdown due to breakdown at the edge portion 12 at the bottom of the U groove 50. Further, boron is diffused in the central portion of the p-type base layer 16 in advance so that the junction depth of the central portion of the p-type base layer 16 is deeper than the surroundings, and a high voltage is applied between the drain and the source. It is set so that breakdown occurs at the central portion of the bottom surface of the p-type base layer 16 when it is opened. Further, after the double diffusion, the diffusion mask and the LOCOS oxide film used for forming the U groove 50 are removed, and the gate oxide film 8 having a thickness of about 60 nm is formed on the inner wall of the U groove 50. A gate electrode 9 made of polysilicon having a thickness of about 400 nm and an interlayer insulating film 18 made of BPSG having a thickness of about 1 μm are formed on the top. Furthermore, a p-type base layer 16 having a junction depth of about 0.5 μm is formed on the central surface of the p-type base layer 16.
^{The +} type base contact layer 17 is formed, and the interlayer insulating film 1 is formed.
Source electrode 19 and n ⁺ type source layer 4 formed on
And the p ⁺ type base contact layer 17 is in ohmic contact through the contact hole. Further, the drain electrode 20 is formed so as to make ohmic contact with the back surface of the semiconductor substrate 1.

Next, the manufacturing method of this embodiment will be described. First,
As shown in FIGS. 2 and 3, n ^{− is} formed on the main surface of the semiconductor substrate 1 made of n ⁺ type silicon and having a plane orientation of (100).
A wafer 21 on which a mold type epitaxial layer 2 is grown is prepared. The semiconductor substrate 1 (corresponding to a semiconductor substrate) has an impurity concentration of about 10 ²⁰ cm ^-3 . The thickness of the epitaxial layer 2 (corresponding to the semiconductor layer) is 7 μm.
The impurity concentration is about 10 ¹⁶ cm ⁻³ . Next, as shown in FIG. 4, the main surface of the wafer 21 is thermally oxidized to form a field oxide film 6 having a thickness of about 60 nm.
After forming 0, a resist film 61 is deposited, and the resist film 61 is patterned by a known photolithography process into a pattern having an opening at the center of the planned cell formation position. Then, using the resist film 61 as a mask, boron (B ⁺ )
Is ion-implanted.

After the resist is stripped off, a p-type diffusion layer 62 having a junction depth of about 3 μm is formed by thermal diffusion as shown in FIG. The p-type diffusion layer 62 finally becomes a part of the p-type base layer 16 described later, and when a high voltage is applied between the drain and the source, the p-type diffusion layer 62 stably breaks down at the bottom. Raising it fulfills the purpose of improving surge resistance.

Next, as shown in FIG. 5, a silicon nitride film 63 is deposited to a thickness of about 200 nm on the main surface of the wafer 21, and the silicon nitride film 63 (corresponding to a mask) is formed in the <011> direction as shown in FIG. To form a lattice-shaped opening pattern having a pitch width (dimension of the unit cell 15) a (corresponding to a mask forming step). The opening pattern is masked so that the p-type diffusion layer 62 described above is located at the center of the pitch interval.

Next, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and subsequently, FIG.
As shown in, the discharge chamber 7 containing carbon tetrafluoride and oxygen gas
02 to generate plasma to create chemically active species,
This active species is transported to the reaction chamber 703, where it is n
^{The −} type epitaxial layer 2 is isotropically subjected to chemical dry etching to form a groove 64 (corresponding to a chemical dry etching step).

Next, as shown in FIG. 8, the portion of the groove 64 is thermally oxidized using the silicon nitride film 63 as a mask (corresponding to an oxidizing step and a selective oxidizing step). This is LOCOS (Local O
This oxidation method is well known as the xidation of Silicon method, and this oxidation causes the LOCOS oxide film 65 (oxide film,
(Corresponding to a selective oxide film) is formed, and at the same time, a U groove 50 (corresponding to a second groove) is formed on the surface of the n ⁻ type epitaxial layer 2 eaten by the LOCOS oxide film 65, and the shape of the U groove 50 is Determine.

At this time, the chemical dry etching condition and the LOCOS oxidation condition are selected so that the surface orientation of the channel forming portion on the side surface of the U groove 50 becomes a surface close to (111).
The U-groove 5 thus formed by LOCOS oxidation
The inner wall surface of No. 0 is flat and has few defects, and the surface has a good surface condition to the same extent as the initial main surface of the wafer 21 shown in FIG.

Next, as shown in FIG. 9, boron is ion-implanted to form the p-type base layer 16 through the thin field oxide film 60 using the LOCOS oxide film 65 as a mask. At this time, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 is in a self-aligned position, and the ion-implanted region is accurately defined. Next, FIG.
As shown in (3), heat is diffused to a junction depth of about 3 μm. By this thermal diffusion, the p-type diffusion layer 62 previously formed in the step shown in FIG. 5 and the boron diffusion layer implanted in the step shown in FIG. 9 are integrated, and one p-type base layer 16 (base layer is formed). Equivalent). Further, both end faces of the region of the p-type base layer 16 are defined by the positions of the side walls of the U groove 50 in a self-aligned manner.

Next, as shown in FIG. 11, patterning is performed with a pattern left in the center of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 in a grid pattern. Using both the resist film 66 and the LOCOS oxide film 65 as a mask, phosphorus is ion-implanted through the thin field oxide film 60 to form the n ⁺ -type source layer 4 (corresponding to the source layer). Also in this case, as in the case where boron is ion-implanted in the step shown in FIG. 9, the boundary portion between the LOCOS oxide film 65 and the field oxide film 60 is in a self-aligned position, and the ion-implanted region is accurately defined.

Next, as shown in FIG.
Heat diffusion is performed for 5 to 1 μm to form the n ⁺ type source layer 4, and at the same time, the channel 5 (corresponding to the channel region) is also set. In this thermal diffusion, the end surface of the region of the n ⁺ type source layer 4 which is in contact with the U groove 50 is defined in a self-aligned manner at the position of the sidewall of the U groove 50 (corresponding to the impurity introducing step). Above, FIGS. 9 to 1
The second step determines the junction depth of the p-type base layer 16 and its shape. What is important in the shape of the p-type base layer 16 is that the position of the side surface of the p-type base layer 16 is defined by the side surface of the U-groove 50 and self-aligns for heat diffusion.
The shape of the p-type base layer 16 is completely symmetrical with respect to the U groove 50.

Next, as shown in FIG. 13, the LOCOS oxide film 65 is terminated with hydrogen in the aqueous solution 700 containing hydrofluoric acid while the pH is adjusted to about 5 by ammonium fluoride. Meanwhile, the oxide film is removed to expose the inner wall 51 of the U groove 50. This removing step is performed by shielding the surface on which the selective oxide film is formed from light with a light-shielding cloth (corresponding to the oxide film removing step and the selective oxide film removing step).

After that, it is taken out from the aqueous solution and dried in clean air. Next, as shown in FIG. 15, the side surface 5 of the U groove of the p-type base layer 16 in which a channel is to be formed.
An oxide film is formed until the (111) plane is formed. By this thermal oxidation step, the flatness on the atomic order of the surface on which the channel is to be formed is increased. This thermal oxidation step is
As shown in FIG. 14, the oxygen atmosphere is maintained at about 1000
This is performed by gradually inserting the wafer 21 into the oxidation furnace 601 which is maintained at a temperature of 0 ° C. By doing so, since the initial stage of oxidation is performed at a relatively low temperature, the p-type base region 1
6. Impurities in the n ⁺ type source region 4 can be suppressed from scattering outside the wafer during the oxidation process. Next, as shown in FIG. 16, this oxide film 600 is removed. This oxide film 6
Similarly to the removal of the selective oxide film, the removal of 00 is also carried out in an aqueous solution containing hydrofluoric acid while terminating the exposed silicon surface with hydrogen in a state where the pH is adjusted to about 5 with ammonium fluoride. U groove 50 formed by such a method
The inner wall 51 of is a good silicon surface with high flatness and few defects.

Subsequently, as shown in FIG. 18, a gate oxide film 8 having a thickness of about 60 nm is formed on the side surface and the bottom surface of the U groove 50 by thermal oxidation. In this oxidizing step, the wafer 21 is gradually inserted into the oxidizing furnace 601 which is maintained in an oxygen atmosphere and is maintained at about 1000 ° C., as described above. In this way, since the initial oxidation is performed at a relatively low temperature, impurities in the p-type base region 16 and the n ⁺ -type source region 4 can be suppressed from scattering outside the wafer during the oxidation process. The film quality and thickness uniformity of the gate oxide film 8, the interface state density of the interface of the channel 5, and the carrier mobility are the same as those of the conventional DM.
It is as good as the OS.

Next, as shown in FIG. 19, a polysilicon film having a thickness of about 400 nm is deposited on the main surface of the wafer 21, and the distance is 2β from the distance b between the upper ends of two adjacent U-grooves 50.
The gate electrode 9 is formed by patterning so as to be separated by a short distance c. Next, the end portion of the gate electrode 9 is oxidized so that the gate oxide film 8 becomes thick. Figure 2 at this time
As shown in 0, β is set so that β> x, where x is the length of the portion where the gate oxide film becomes thicker at the gate end.

As described above, the steps shown in FIGS. 9 to 19 are the most important manufacturing steps in this embodiment.
Using the oxide film 65 as a self-aligned double diffusion mask to form the p-type base layer 16, the n ⁺ -type source layer 4 and the channel 5, and then removing the LOCOS oxide film 65,
Gate oxide film 8 (corresponding to gate insulating film), gate electrode 9
(Corresponding to a gate electrode) is formed (corresponding to a gate electrode forming step).

Then, as shown in FIG. 21, boron is ion-implanted through the oxide film 67 using the patterned resist film 68 as a mask to form the p ⁺ -type base contact layer 17. Next, as shown in FIG. 22, a junction depth of about 0.5 μm is thermally diffused to form the p ⁺ -type base contact layer 17.

Then, as shown in FIG. 1B, an interlayer insulating film 18 made of BPSG is formed on the main surface of the wafer 21, and contact holes are formed in a part of the interlayer insulating film 18 to form p ⁺ -type base contact layers 17 and n. ^{The +} type source layer 4 is exposed. Further, a source electrode 19 (corresponding to a source electrode) made of an aluminum film is formed, and ohmic contact is made with the p ⁺ type base contact layer 17 and the n ⁺ type source layer 4 through the contact hole. Further, a passivation film (not shown) made of silicon nitride or the like is formed by a plasma CVD method or the like for protecting the aluminum film, and the wafer 21
The back surface of the drain electrode 20 made of three layers of Ti / Ni / Au (corresponds to the drain electrode) is formed, n ⁺ -type semiconductor substrate 1 ohmic contact (source and drain electrode forming step, the electrode forming step Equivalent to).

According to the method of manufacturing the semiconductor device of the present embodiment having the above-described structure, the predetermined region on the surface of the low-concentration semiconductor layer is removed by the chemical dry etching method before the selective oxidation. The chemical dry etching method is a kind of dry etching method and has high process controllability, uniform etching can be performed on the wafer surface, and reproducibility is also high. Further, in the chemical dry etching method, the damage given to the surface to be etched is relatively small in the dry etching process. Then, after this chemical dry etching, the surface of the groove 64 (first groove) is oxidized. When oxidation is performed here, the surface of the groove 64 where the oxidation is started causes
The resulting n ⁻ -type epitaxial layer 2 (semiconductor layer) has a different interface state with the oxide film. That is, even if the surface that has been etched by physical etching such as RIE is oxidized, the oxidation proceeds with lattice defects,
Lattice defects remain on the surface of the resulting n ⁻ type epitaxial layer 2. However, in the present invention, by using the chemical dry etching method for the surface of the groove 64, the groove 64 having a surface with few high defects is formed, and the surface is oxidized, so that it is uniformly oxidized from the time when the oxidation is started. As a result, the surface of the U groove 50 obtained can be a surface with few defects. And
Since the surface of the U groove 50 is used as the channel region, low on-resistance can be obtained. Further, in order to form the U groove 50 as a groove for the channel region, a two-step process of chemical dry etching and oxidation is performed. Therefore, the groove shape can be accurately controlled.

Further, according to the present embodiment, since the chemical dry etching process is isotropic, the groove 64 has no corner, and therefore the U groove 50 formed by oxidation also has no corner. Therefore, the breakdown voltage between the drain and the source is improved. Further, the angle of the groove 64 near the surface of the n ⁻ type epitaxial layer 2 becomes close to 90 °, and U formed after the selective oxidation.
The inclination angle of the side surface of the groove 50 can be made steep, and the cell size can be reduced to obtain a low on-voltage.

Since the chemical dry etching step includes carbon tetrafluoride and oxygen in the gas, the process can be performed accurately and with good reproducibility depending on the ratio of carbon tetrafluoride and oxygen. Further, according to the present embodiment, in the chemical dry etching process, since the cathode is substantially dropped above the semiconductor substrate 1 or the n ⁻ type epitaxial layer 2, the ionized gas causes defects on the surface of the n ⁻ type epitaxial layer 2. Will not collide at a speed that would give Therefore, the surface of the groove 64 to be formed can be a surface with very few defects.

Furthermore, according to the present embodiment, since the oxidation process is a selective oxidation process for selectively oxidizing the groove 64, the depth of the groove 64 can be increased. Further, since the mask used in the chemical dry etching process is used as it is as the mask in the selective oxidation process, it is not necessary to form a new mask and the alignment is also unnecessary. After the oxidation step, the step of removing the oxide film to expose the channel region is performed while terminating the dangling bond on the surface of the n ⁻ type epitaxial layer 2 with hydrogen in an aqueous solution. As a result, the dangling bond having high reaction activity reacts with hydrogen before reacting with the pollutant to be in a stable state, and the reaction between the pollutant and the n ⁻ type epitaxial layer 2 can be prevented. When it is subsequently exposed to oxygen, a more stable oxide film is formed to protect the surface of the U groove 50, so that the subsequent contamination of the channel region can be avoided, so that high channel mobility can be obtained and low on-voltage can be obtained. You can

Further, the oxide film is removed in an aqueous solution containing hydrofluoric acid.
The oxide film you want to remove and the^-Type d
The selection ratio with the axial layer 2 is very large.
First, n ^-Do not damage the surface of the epitaxial layer 2
The oxide film can be removed. Furthermore, selective oxide film
In order to form the base layer and source layer in self-alignment with
No alignment is required. Therefore, the base layer at the correct position,
The source layer can be formed, and the area of the device can be reduced.

By preventing the surface of the oxide film from being irradiated with light during the removal of the oxide film, the semiconductor layer serving as the channel region is not irradiated with light through the oxide film. Therefore, the potentials of the n ⁺ type source layer 4 and the p type base layer 16 in the vicinity of the channel region become substantially equal to each other, it is possible to prevent the etching from locally progressing, and uniform etching can be performed. As a result, a flat channel region can be obtained and high mobility can be obtained.

Then, U obtained by removing the selective oxide film
The plane orientation of the side surface of the groove 50 is the {111} plane. The silicon atoms on the side surface are terminated by one hydrogen atom, and an atomically flat side surface is obtained. Therefore, high channel mobility can be obtained. Also, since the step of removing the oxide film is performed in an aqueous solution of 4 or more, the rate at which silicon atoms on the side surface of the U groove 50 are terminated by one hydrogen atom is further increased, resulting in an atomically flat {111}. A surface can be obtained and high channel mobility can be obtained.

As described above, by performing LOCOS oxidation after the conventional physical etching such as RIE or wet etching, the lattice defects introduced at the time of forming the initial groove (first groove, that is, the groove 64) are LOCOS oxidized and That L
It was thought to be removed by removing the OCOS oxide film. However, when the present inventors actually made a prototype, it was confirmed that the lattice defects introduced at the time of introducing the initial groove are not removed but remain on the surface of the channel region. As a result, it has been found that it causes a leak current between the drain and the source. From this result, it was found that it is necessary to perform a defect-free process from the beginning when forming the initial groove. However, chemical dry etching, which is known as a defect-free process similar to wet etching, has a slower etching rate than wet etching.
Further, since it is isotropic etching as in wet etching, side etching occurs, which is not suitable for miniaturization. Therefore, chemical dry etching is considered to be unsuitable for the groove forming process in view of the current technology of reducing the channel resistance and the on-resistance by shortening the channel length by miniaturization. However, after etching L
In the manufacturing method of forming the initial groove (first groove, that is, the groove 64) by the OCOS oxidation, the time required for etching does not differ much between chemical wet etching and chemical dry etching. It was found that the number of lattice defects on the surface of the channel region obtained in Example 1 was extremely small, and an arbitrary exponential plane could be formed accurately.

Although the present invention has been specifically described based on an embodiment, the present invention is not limited to the above embodiment, and it goes without saying that various modifications can be made without departing from the scope of the invention. . For example, after removing the LOCOS oxide film in the aqueous solution containing hydrofluoric acid as shown in FIG. 13, the silicon surface is protected by the natural oxide film by natural oxidation in this embodiment. You can go. Then, the n-type source layer and the p-type source layer are formed by L
After removing the OCOS oxide film, a resist mask may be used. Further, the surface orientation and patterning shape of the substrate may be selected so that the surface orientation of the side surface of the groove obtained by removing the selective oxide film is the low index surface (110) surface or (100) surface. . In addition, the above-mentioned embodiment applies the present invention to the vertical power M.
Although only the case of applying to the OSFET has been described, the present invention is not limited to this, and the vertical power M
It may be applied to a power MOSIC incorporating an OSFET. Furthermore, in this embodiment, a vertical power MOSFET having an n ⁺ type semiconductor substrate as a semiconductor substrate.
However, the present invention can be applied to the gate structure of an insulated gate bipolar transistor (IGBT) using a p ⁺ type semiconductor substrate. In addition, the chemical dry etching process is performed using CCl ₄ , Cl ₂ , SF ₆ , CFCl.
₃ , CF ₂ Cl ₂ , CF ₃ Cl, CHF ₃ , C ₂ ClF
It is also possible to use a gas system containing any one or more of ₅ , F ₂ , NF ₃ , and BCl ₃ . This enables efficient etching. Further, in the present example, the voltage was not applied to the semiconductor substrate, but the chemical dry etching step was performed in an ionized gas atmosphere in which the absolute value of the cathode drop above the semiconductor layer was less than 10V. You may do it in the state. This prevents the ionized gas from colliding with the surface of the semiconductor layer at such a speed as to give a defect to the surface of the semiconductor layer. Then, the surface of the formed groove 64 can be a surface with very few defects. Although only the n-channel type has been described in the present embodiment, it goes without saying that the same effect can be obtained with the p-channel type in which the n-type and p-type semiconductor types are interchanged.

[Brief description of drawings]

1A is a plan view showing a part of a vertical power MOSFET according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA of FIG.

FIG. 2 is a vertical power MOSF according to the first embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 3 is a vertical power MOSF according to the first embodiment of the present invention.
It is sectional drawing with which the manufacturing process of ET is demonstrated.

FIG. 4 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 5 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 6 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a plan view of a principal part for explaining the manufacturing process of the ET.

FIG. 7 is a vertical power MOSF according to the first embodiment of the present invention.
It is a figure with which an ET manufacturing process is explained.

FIG. 8 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 9 is a vertical power MOSF according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of a main part provided for explaining a manufacturing process of ET.

FIG. 10 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 11 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 12 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 13 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 9 is a diagram which is used for describing a manufacturing process of the FET.

FIG. 14 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 9 is a diagram which is used for describing a manufacturing process of the FET.

FIG. 15 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 16 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 9 is a diagram which is used for describing a manufacturing process of the FET.

FIG. 17 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 9 is a diagram which is used for describing a manufacturing process of the FET.

FIG. 18 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 19 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 20 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 21 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 22 is a vertical power MOS according to the first embodiment of the present invention.
FIG. 6 is a main-portion cross-sectional view which is provided for describing a manufacturing process of an FET.

FIG. 23 (a) is a plan view showing a part of a conventional vertical power MOSFET, and FIG. 23 (b) is a sectional view taken along the line AA of FIG.
It is sectional drawing.

FIG. 24 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 25 is a cross-sectional view of an essential part for explaining the manufacturing process of the conventional vertical power MOSFET.

FIG. 26 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 27 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 28 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 29 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 30 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 31 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 32 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 33 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 34 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

FIG. 35 is a main-portion cross-sectional view which is provided for describing a manufacturing process of a conventional vertical power MOSFET.

[Explanation of symbols]

1 n ⁺ type semiconductor substrate 2 n ⁻ type epitaxial layer 4 n ⁺ type source layer 5 channel 6 n ⁻ type drain layer 7 JFET part 8 gate oxide film 9 gate electrode 16 p type base layer 19 source electrode 20 drain electrode 50 U groove 51 U-groove inner wall 65 LOCOS oxide film 601 Oxidation furnace 603 Wafer boat 700 Aqueous solution 702 Discharge chamber 703 Reaction chamber 704 Light-shielding cloth

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yuichi Takeuchi, 1-1, Showa-cho, Kariya city, Aichi Prefecture, Nihon Denso Co., Ltd. (72) In-house, Norihito Tokura, 1-1, Showa-cho, Kariya city, Aichi prefecture Within the corporation

Claims (26)

[Claims] 1. A mask forming step of forming a mask having an opening portion in a predetermined region on a main surface of a semiconductor layer of a first conductivity type arranged on a semiconductor substrate, and the semiconductor layer through the opening portion of the mask. By chemical dry etching to form a first groove in the semiconductor layer having an inlet portion wider than the opening, a bottom surface substantially parallel to the main surface, and a side surface connecting the inlet portion and the bottom surface. A chemical dry etching step, an oxidation step of oxidizing a region including the first groove to form an oxide film having a predetermined thickness on the surface of the first groove, and a surface of the semiconductor layer in contact with the oxide film A second conductivity type impurity is introduced from the main surface side to form a second conductivity type base layer in the semiconductor layer, and a second conductivity type base layer is formed in the base layer from the main surface side. Introducing impurities First
An impurity introducing step of forming a conductive type source layer and forming a channel region on the side wall of the base layer at the time of forming the source layer; and removing the oxide film to form a predetermined depth deeper than the first groove. An oxide film removing step of forming a second groove having; a gate electrode is formed on at least the surface of the second groove between the source layer and the semiconductor layer via a gate insulating film, and the source layer and the An electrode forming step of forming a source electrode in electrical contact with the base layer and a drain electrode in electrical contact with the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the chemical dry etching step is an isotropic etching step. 3. The chemical dry etching process comprises:
3. The method of manufacturing a semiconductor device according to claim 1, comprising a step of etching with a gas system containing carbon tetrafluoride and oxygen. 4. The chemical dry etching step comprises:
CCl_Four, Cl₂, SF₆, CFCl₃, CF₂C
l₂, CF₃Cl, CHF₃, C₂ClF_Five, F ₂, N
F₃, BCl₃A moth containing any one or more of
A contract characterized by comprising a process of etching
A method for manufacturing a semiconductor device according to claim 1 or claim 2. 5. The chemical dry etching process comprises:
5. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed in an ionized gas atmosphere in a state where there is substantially no cathode drop above the semiconductor layer. 6. The chemical dry etching step comprises:
5. The method for manufacturing a semiconductor device according to claim 1, wherein an absolute value of cathode fall above the semiconductor layer is less than 10 V in an ionized gas atmosphere. 7. The oxidizing step selectively oxidizes a region including the first groove to selectively oxidize a surface of the first groove and a predetermined thickness between the mask and the semiconductor substrate. In the semiconductor layer, the impurity introducing step comprises introducing the second conductivity type impurity from the main surface side so as to include the semiconductor layer surface in contact with the selective oxide film. Forming a base layer of a second conductivity type into the base layer, and introducing an impurity of the first conductivity type into the base layer from the main surface side to form the source layer of the first conductivity type, The oxide film removing step comprises a selective oxide film removing step of removing the selective oxide film to form a second groove having a predetermined depth deeper than the first groove. 7. A method of manufacturing a semiconductor device according to claim 6. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the selective oxidation step, the selective oxidation is performed using the mask formed in the mask formation step. 9. The selective oxidation step forms a selective oxide film having a predetermined thickness between the surface of the first groove and the mask and the semiconductor layer. Item 9. A method of manufacturing a semiconductor device according to item 8. 10. The selective oxidation step selectively oxidizes a region including the first groove formed by the chemical dry etching step, so that the surface of the first groove has a first selective oxidation of a predetermined thickness. 9. The method according to claim 7, further comprising: forming a film, and forming a second selective oxide film between the mask and the semiconductor substrate, the second selective oxide film becoming thinner as the distance from the entrance portion increases. Manufacturing method of semiconductor device. 11. The oxide film removing step removes the oxide film while terminating the surface of the oxide film with hydrogen in an aqueous solution to form the first groove having the predetermined depth, 2. A step of oxidizing the surface of the first groove terminated with the hydrogen in a gas containing oxygen to form a protective oxide film on the surface of the first groove.
11. A method of manufacturing a semiconductor device according to claim 10. 12. The oxide film removing step removes the oxide film while terminating dangling bonds generated on the surface of the oxide film with hydrogen in an aqueous solution containing hydrofluoric acid. 11. The method for manufacturing a semiconductor device according to item 11. 13. A mask forming step of forming a mask having an opening in a predetermined region on a main surface of a semiconductor substrate of the first conductivity type, the semiconductor substrate being etched through the opening of the mask, the semiconductor substrate An etching step of forming a first groove having an entrance portion wider than the opening, and selectively oxidizing a region including the first groove to form a surface of the first groove and the mask. A selective oxidation step of forming a selective oxide film having a predetermined thickness with the semiconductor substrate; and a second conductivity type impurity from the main surface side so as to include the surface of the semiconductor substrate in contact with a side surface of the selective oxide film. A second conductive type base layer is formed by diffusing, and a first conductive type impurity is diffused into the base layer from the main surface side.
An impurity introduction step of forming a conductive type source layer and forming a channel on the side wall of the base layer, and removing the selective oxide film while terminating the surface of the selective oxide film with hydrogen in an aqueous solution, After forming a second groove having a predetermined depth deeper than the first groove, the surface of the second groove terminated by the hydrogen is oxidized in a gas containing oxygen to form a surface of the second groove. A selective oxide film removing step of forming a protective oxide film on the source electrode, and a source electrode electrically contacting the source layer and the base layer by forming a gate electrode on the surface of the second groove through the gate oxide film And an electrode forming step of forming a drain electrode in electrical contact with the other main surface side of the semiconductor substrate. 14. The step of forming an electrode comprises oxidizing an inner wall of the second groove to form a gate oxide film,
A gate electrode forming step of forming a gate electrode on the gate oxide film, forming a source electrode in electrical contact with both the source layer and the base layer, and electrically contacting the other main surface side of the semiconductor substrate. 14. The method of manufacturing a semiconductor device according to claim 1, further comprising a source / drain electrode forming step of forming a drain electrode for forming the semiconductor device. 15. The impurity introducing step diffuses the second conductivity type impurity from the main surface side in a self-aligned manner with the selective oxide film to form the base layer on the surface of the first groove, 15. The source layer is formed by diffusing the impurity of the first conductivity type into the base layer from the main surface side in a self-aligning manner with the selective oxide film. A method for manufacturing a semiconductor device as described above. 16. The semiconductor according to claim 1, wherein the oxide film removing step is a step of removing the oxide film in a state where at least the surface of the oxide film is not irradiated with light. Device manufacturing method. 17. The semiconductor layer is made of silicon, and in the oxide film removing step, the surface orientation of the channel forming portion on the side surface of the second groove obtained by removing the oxide film is {1.
2. The step of removing the oxide film so as to form either one of the 10} plane and the {100} plane.
17. A method of manufacturing a semiconductor device according to claim 16. 18. The semiconductor layer is made of silicon, and in the oxide film removing step, the surface orientation of the channel formation portion on the side surface of the second groove obtained by removing the oxide film is {1.
17. The method for manufacturing a semiconductor device according to claim 1, which is a step of removing the oxide film so as to form a {11} plane. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the oxide film removing step is a step of removing the oxide film with a solution having a pH of more than 4. 20. A semiconductor substrate of a first conductivity type, a chemical dry etching formed on the main surface side of the semiconductor substrate, and a LOC after the chemical dry etching.
An inlet having a predetermined inlet width, a bottom surface having a plane substantially parallel to the main surface, and a side surface continuously connecting the inlet and the bottom surface, which is formed by performing OS oxidation.
A second conductive type base layer formed to a predetermined depth from the main surface side, including a side surface of the groove portion, and a groove part formed in the base layer on the main surface side. A semiconductor device comprising: a source layer for forming a channel region on a side surface; and a gate electrode formed in a region including the side surface and the bottom surface of the groove portion via a gate insulating film. 21. The semiconductor device according to claim 20, wherein the groove has a depth from the main surface that is ½ or less of the entrance width. 22. The plane orientation of the semiconductor substrate is {10.
20} to claim 2 which are 0 planes.
1. The semiconductor device according to 1. 23. The semiconductor substrate, the base layer, and the source layer are each made of silicon, and the plane direction of the channel region on the side surface of the groove is {1.
23. The semiconductor device according to claim 20, which is a surface close to the 11} plane or the {111} plane. 24. The semiconductor substrate, the base layer and the source layer are each made of silicon, and the plane direction of the channel region on the side surface of the groove is {1.
10} plane, plane close to {110} plane, {100} plane, {1
22. The semiconductor device according to claim 20, wherein the semiconductor device is any one of the surfaces close to the {00} surface. 25. The groove portion is formed by chemically dry etching the semiconductor substrate to form an initial groove, and then oxidizing a region including the initial groove to form an oxide film having a predetermined thickness on a surface of the initial groove. 21. The semiconductor device according to claim 20, wherein the semiconductor device is formed by removing the oxide film by etching. 26. The semiconductor device according to claim 20, wherein the groove has a bathtub shape.