JPH08236704A - Semiconductor intergrated circuit - Google Patents

Abstract

PURPOSE: To prevent malfunction of the other electronic circuit and electronic device by reducing radiation of an electromagnetic wave due to current of signal wiring on a semiconductor integrated circuit. CONSTITUTION: A clock signal CK on a semiconductor integrated circuit 1 and a clock signal CKB in an inversed phase relation thereto are adjacently arranged, then one side clock signal wiring CKB is provided with a dummy load capacitor Cd so as to adjust that absolute values of charge and discharge currents of the respective signal wirings may be equal. Thereby, magnetic fields generated by the charge and discharge currents can be cancelled with high accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which operates at high speed, and more particularly to a semiconductor integrated circuit which controls electromagnetic wave energy radiated from the semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become faster and larger in scale, malfunction of electronic equipment due to electromagnetic waves radiated from the semiconductor integrated circuits has become a problem.

To solve this problem, a semiconductor integrated circuit 1 for reducing electromagnetic wave energy radiated from a semiconductor integrated circuit having a structure as shown in FIG. 4 includes a clock signal generating circuit 2 for generating a basic clock signal and a functional circuit. 3, a clock signal 4, and an inverted signal 5 of the clock signal.

FIG. 5 is a timing chart for explaining the operation of the semiconductor integrated circuit 1. A conventional example will be described with reference to these drawings. The clock signals CK and CKB used in the semiconductor integrated circuit 1 have an opposite phase relationship in the timing chart shown in FIG. 5, and the charging / discharging current I clock signals CK and ICKB flowing through the respective signal wirings at that time are the same as those on the charging side. If it is positive, the maximum value of each current depends on the load of each wiring and the current supply capability of the transistor that drives it. In general,
The maximum value of each current is different.

A magnetic field is generated by these currents, which becomes an electromagnetic wave and affects other electric circuits. Approximating with a current flowing through an infinitely long wire, the generated magnetic field H is H = (I / 2πr), where I is the current flowing through the wire and r is the distance from the wire.

Magnetic field HC due to currents ICK and ICKB
K and HCKB are clock signals CK and CK in FIG.
Since the sum of the magnetic field HCK by the clock signal CK and the magnetic field HCKB by the clock signal CKB is at a position far away from the distance of the wiring B, HCK + HCKB = (1 / 2π). (ICK + ICK
B) and the value (HCK + HCKB) shown in FIG.

In other words, by wiring signals having opposite phases in close proximity to each other, the magnetic fields due to the respective signal wirings cancel each other, and as a result, it is possible to reduce the electromagnetic wave energy radiated from the semiconductor integrated circuit. ing.

[0008]

However, in the conventional method of reducing the electromagnetic wave energy radiated from the semiconductor integrated circuit, the signals of the antiphase relation on the semiconductor integrated circuit are selected and simply wired in close proximity to each other. Only.
Therefore, when the load of the pair of signal wirings is not the same or when there is no anti-phase signal in the signal wiring through which a large current flows, there is a problem that the effect is insufficient or no countermeasure can be taken.

[0009]

According to the method for reducing electromagnetic wave energy radiation according to the present invention, when there is a signal wiring having an opposite phase relationship, a dummy element is provided so that the charge and discharge currents of the two signal wirings are absolute. The values are adjusted to be the same, and when there is no signal wiring having an opposite phase relationship, a dummy signal wiring and a dummy element are provided.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. Figure 2
3 is a timing chart showing the operation of the embodiment of FIG. In the figure, the same components as those of the conventional example are designated by the same reference numerals. The difference from the conventional example is that a dummy load capacitance Cd is added so that the charge / discharge current ICKB of the clock signal CKB has the same absolute value as the charge / discharge current ICB of the clock signal CK. If the dummy load capacitance Cd is determined by estimating the load capacitance of each signal wiring at the time when the mask design of the semiconductor integrated circuit is completed, highly accurate adjustment can be realized.

The charging / discharging currents ICK and ICKB of the respective signal lines and the magnetic fields HCK and HCKB generated by the charging / discharging currents ICK and ICKB with the dummy load capacitance Cd are as shown in FIG. Since the absolute value of the maximum value I1 of the charging / discharging current of the clock signal CK and the maximum value I2 of the charging / discharging current of the clock signal CKB are the same and their reversion is opposite, the sum of the magnetic fields becomes zero.

FIG. 3 shows a second embodiment of the present invention. In this embodiment, there is no signal having the opposite phase, the clock signal CK1 and the dummy clock signal CDM are included, and the dummy clock signal CDM and the clock signal CK1 have the opposite phase relationship. Furthermore, dummy load capacitors Cd1 and Cd2
have. The same symbols as those in the first embodiment are attached to the same symbols in the drawings.

In the case of this embodiment, the dummy clock signal CDM is wired close to the clock signal CK1. The dummy load capacitances Cd1 and Cd2 estimate the load capacitance of the signal wiring at the end of the mask design of the semiconductor integrated circuit,
Must be a reflected value. That is, the absolute value of the charge / discharge current of each signal must be set to be equal. The basic operation and other operational effects of this embodiment are similar to those of the first embodiment, and detailed description thereof will be omitted.

[0015]

As described above, according to the present invention, the magnetic field generated by the current flowing through the signal wiring can be canceled with high accuracy by using the signal wiring, the dummy load capacitance or the dummy signal wiring of the opposite phase. . That is, there is an effect that the electromagnetic wave energy radiated from the semiconductor integrated circuit can be reduced.

Although the clock signal wiring has been described in the present embodiment, the present invention is not limited to this, but if it is applied to a signal wiring through which a relatively large current flows, a sufficient effect can be obtained. Further, although the capacitive element has been described as the dummy element, the same effect can be obtained even if a resistive element or an inductance element is used as the dummy element according to the property of the flowing current.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart explaining the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional semiconductor integrated circuit.

FIG. 5 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 1 semiconductor integrated circuit 2 clock generation circuit 3 functional circuit 4 clock signal CK 5 clock signal CKB 6 clock signal CK1 7 dummy clock signal CDM Cd, Cd1, Cd2 dummy load capacitance ICK charging / discharging current of clock signal CK ICKB clock signal CKB charging Magnetic field generated by discharge current HCK I CK Magnetic field generated by HCKB I CKB

Claims (2)

[Claims] 1. A first signal wiring formed on a semiconductor substrate, and a second signal which is arranged in the vicinity of this wiring and which transmits a signal having a phase opposite to that of a signal transmitted to the first signal wiring. A semiconductor integrated circuit having a wiring and including a dummy element connected to the second signal wiring. 2. A dummy wiring is arranged as the second signal wiring when there is no signal wiring for transmitting a signal having an opposite phase in the vicinity of the first signal wiring.
The semiconductor integrated circuit described.