JPH08235129A - Parallel processor - Google Patents

Abstract

PURPOSE: To efficiently perform multiplication with grouped filters whose coefficient values are not 0 like a filter used for a ghost canceler. CONSTITUTION: For data which are inputted at a sufficient interval of time, plural serial/parallel converters 1-3 are shifted in timing and then the passing and receiving time of the data is shortened by bringing necessary data to respective processor elements 4(j) or nearby processor elements 4(j) without passing and receiving the data to and from adjacent processor elements 4(j), thereby ending computation within one horizontal period. Namely, serial/parallel conversion is performed in different timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor used for digital processing of video signals.

[0002]

2. Description of the Related Art As a device for digitally processing a video signal, for example, "SVP: SERIAL VIDEO PROCESSOR / Proceedin
gs of the IEEE 1990 CUSTOM INTEGRATED CIRCUITS CON
FERENCE / P.17.3.1-4 "is known.

This device is specifically constituted by a parallel processor as shown in FIG. 10, for example. That is, FIG.
0, for example, a video signal in which each pixel is composed of a plurality of bits is word (pixel) serially supplied from a serial data input terminal (hereinafter, SIN), and "capacity (m) for one horizontal period (1H)" is supplied. And a serial / parallel converter having “” (hereinafter, abbreviated as SP) 101. The m pieces of data stored in the SP 101 are the corresponding m pieces of parallel data output terminals (POU).
T1 to POUTm). In FIG. 10, m = 100 for simplicity. In general, m is the number of data for one horizontal period, so several hundreds
~ A few thousand.

The above-mentioned parallel data output terminal (POUT
1 to POUTm), the m pieces of data are respectively associated with m corresponding processor elements (hereinafter, PE).
102 (1) to PE 102 (m). Each PE 102 (j) has a memory and an arithmetic circuit to be described later, and a desired arithmetic operation is performed by a control signal from the control circuit 103.

Further, each PE 102 (j) has an adjacent P
It is wired so that data can be exchanged with E102 (j-1) and PE102 (j + 1). The delivery of this data is also controlled by the control circuit 103.

After the PE 102 (1) to PE 102 (m) have performed a desired operation, the resulting m pieces of data are "parallel / serial having a capacity (m) of one horizontal period (1H)". Converter "(hereinafter abbreviated as PS) 10
4 m parallel data input terminals (PIN1 to PIN
m) respectively. The data input in parallel from the parallel data input terminals (PIN1 to PINm) is converted into word (pixel) serial and output in word (pixel) serial from the serial data output terminal (SOUT).

Therefore, in this device, the data of each pixel of the video signal supplied to the SP 101 every horizontal period is
It is stored in the PE 102 (j) within the subsequent horizontal blanking period. The data stored in the PE 102 (j) is arithmetically processed by the arithmetic circuit in the PE 102 (j) during the next one horizontal period. Then, during the subsequent horizontal blanking period, the arithmetically processed data in the PE 102 (j) is input to the PS 104, and the arithmetically processed video signal is taken out for each horizontal period. In this way, for example, digital processing of the video signal is performed.

Further, PE 102 (1) to PE 102
The control circuit 103 for controlling the calculation in (m) is
It is only one and is common to all m PEs. That is, FIG. 4 shows a SIMD (Single Instruction Multiple) having the same number of PEs as the number of data (m) for one horizontal period.
Data) method parallel processor. In video signal processing, since the same arithmetic processing is often performed on all pixels, the SIMD method in which the same processing instruction is given to all processor elements can be sufficiently applied and there is no inconvenience.
The SIMD method has an advantage that only one control circuit is required and the circuit scale is reduced.

Here, the above-mentioned SI which is an example of a conventional circuit is used.
The MD parallel processor will be described in detail.

As shown in FIG. 11, the SP 101 shown in FIG. 10 has registers 111 (1) to 111 (100),
1-bit unit delay elements 112 (1) to 112 (10
0) and switches 113 (1) to 113 (100). Delay elements 112 (1) to 1
12 (100) are connected in series, and the ON signal from the write pointer input terminal (WPTR) receives the delay element 112 (1), the delay element 112 (2), and the delay element 112.
(3), ... It is sequentially sent to the delay element 112 (100). The switch 113 (j) is provided in the input section of the register 111 (j) (j = 1 to 100).
If (j) is turned on, the serial data input terminal (SI
The data from N) is stored in register 111 (j). The output of the delay element 112 (j) is the switch 113.
It is used as the ON signal of (j).

The output of the register 111 (j) is sent to the PE 102 via the parallel data output terminal (POUTj).
Input to (j). By applying an ON signal to the write pointer input terminal (WPTR) as shown in FIG. 12 (b), it is serially input to the serial data input terminal (SIN) during time T21 as shown in FIG. 12 (a). Incoming data Di1, Di2, Di3, ..., Di99,
Di100 is respectively stored in registers 111 (1) to 111 (100) as shown in FIG.
OUT1, POUT2, POUT3 ,. ． ． , POUT
It is output from 99 and POUT100. Especially at time T2
In No. 2, Dij is stored in all registers, and all parallel data output terminals (POUTj) (j
= 1 to 100), and Dij is output.

Each PE 102 (j) (j = 1 to 100)
Is the memory 121 and the arithmetic circuit 1 as shown in FIG.
It is composed of 22. Data Di from SP101
j is stored in the memory 121 via the input terminal (PEIN) at time T22. The arithmetic circuit 122 performs a desired arithmetic operation on the data stored in the memory 121. At this time, if necessary, input / output terminals (LF
T, RGT), the adjacent PE 102 (j-1), P
Data is exchanged with E102 (j + 1). The LFT terminal is a terminal for exchanging data with the PE 102 (j-1), and the RGT terminal is the PE 102 (j +).
This is a terminal for transferring data to and from 1).

Data DOUTj (j = 1 to 10) which is the result calculated by each PE 102 (j) (j = 1 to 100)
0) is output from the output terminal (PEOUT), and the parallel data input terminals PINj (j
= 1 to 100). As described above, the control circuit 103 controls the PEs 102 (j) (j = 1 to 100) in this calculation process.

As shown in FIG. 14, the PS 104 includes registers 131 (1) to 131 (100), 1-bit unit delay elements 132 (1) to 132 (100), and a switch 13.
3 (1) to 133 (100). The delay elements 132 (1) to 132 (100) are connected in series, and the ON signal from the read pointer input terminal (RPTR) receives the delay element 132 (1) and the delay element 132.
(2), delay element 132 (3), ..., Delay element 132
It is sequentially sent to (100). The data DOUTj (j = 1 to 100) input from the parallel data input terminal (PINj) (j = 1 to 100) are respectively
Once stored in the register 131 (j). Register 1
The output part of 31 (j) (j = 1 to 100) has a switch 133 (j). When the switch 133 (j) is turned on, the data stored in the register 131 (j) is
It is output from the serial data output terminal (SOUT).

Delay element 132 (j) (j = 1 to 100)
Is used as an ON signal of the switch 133 (j). That is, by giving an ON signal to the read pointer input terminal (RPTR), the data DOUT1, DO
UT2, DOUT3, ..., DOUT99, DOUT10
0 serially, serial data output terminal (SOU
It is output from T).

This flow will be described with reference to the timing chart of FIG. 15. As shown in FIG. 15A, Pij (j = 1
15 to 100), the data DOUTj is input once to the register 131 as shown in FIG.
It is stored in (j). Then, at time T31, as shown in FIG.
As shown in FIG. 5 (c), the read pointer input terminal (RPT
When the ON signal is input to R), DOUTi is sequentially output from the serial data output terminal (SOUT) at time T32 thereafter, as shown in FIG.

FIG. 16 shows a timing chart of the overall operation of this conventional parallel processor.

As shown in FIG. 16A, the video signal is
The serial data input terminal (SI
N) is serially supplied from the word (pixel) (time T).
1). Then, as shown in FIG. 16B, an ON signal is input from the write pointer input terminal (WPTR) of the SP 101 immediately before the first data of one horizontal period is input. As a result, the first input data (Di1) has the ON signal sent to the delay element 112 (1) and the switch 113 (1) is turned on, so that the register 111 (1) is turned on.
Stored in. For the next input data (Di2), the ON signal is sent to the delay element 112 (2) and the switch 113
Since (2) is turned on, it is stored in the register 111 (2). Thereafter, similarly, input data (Di3 to Di1
00) is the register 111 (3) to the register 111 (1
00). That is, data for one horizontal period (1H) is stored in the registers 111 (3) to 111 (10).
0).

Subsequent horizontal blanking period (time T
In (2), as shown in FIG. 16C, the data (Di1 to Di100) stored in the registers 111 (3) to 111 (100) are transferred to the parallel data output terminals (POUT1 to POUT100) of the SP101.
Through PE 102 (1) to PE 102 (100).

A desired calculation is performed during the following one horizontal horizontal period (time T3). That is, each PE 102 (j) (j = 1 to 1
100) is the received data Di at time T2.
j is stored in the memory 121, data is read from the memory 121 within the time T3, the arithmetic circuit 122 performs arithmetic operation, and the arithmetic result (DOUTj) is stored again in the memory 121. This control is performed by the CTRL control circuit 103.

Further, in the subsequent horizontal blanking period (time T4), as shown in FIG.
DOUTj (j = 1 to 100) is connected to P104 via the parallel data input terminals PIN1 to PIN100 of PS104.
Registers 131 (1) to 131 (100) in S104
Is supplied to.

Immediately before one horizontal period (time T5) after storing, as shown in FIG. 16 (e), an ON signal is input from the read pointer input terminal (RPTR) of the PS 104. This causes the ON signal to be delayed by the delay element 132.
Since the switch 133 (1) is first turned on after being sent to (1), the operation result data DOUT1 stored in the register 131 (1) is transferred to the serial data output terminal (SOU).
It is output from T). Then, the ON signal is transmitted to the delay element 13
2 (2), the switch 133 (2) is turned on, and the operation result data DOUT2 stored in the register 131 (2) is transferred to the serial data output terminal (SOU).
It is output from T). After that, in the same manner, the register 131
The operation result data DOUT3 to DOUT100 stored in (3) to 131 (100) are output from the serial data output terminal (SOUT). That is, FIG. 16 (f)
As shown in, data of the calculation result for one horizontal period (1H) is serially output from SOUT in a word (pixel) manner.

The next data (Di1 '...
Di100 ′) and the next data (Di1 ″ to Di100 ″) that is further delayed by one horizontal period are subjected to the same operation,
The desired operation is performed and the resulting data (DOUT
1'to DOUT100 ', DOUT1 "to DOUT10
0 ") is output.

Now, as an example of the above "desired calculation",
Consider a case where a filter is applied to the input image data (Di1 to Di100) shown in FIG. The filter coefficient is, for example, as shown in FIG. That is, Will be calculated and DOUT1 to DOUT100 will be output as output image data. here,
COEa to COEe are constants.

The input image data (Di1 to Di100) supplied in word (pixel) serial are parallelized by SP101, and PE102 (1) to PE102 (P), respectively.
E102 (100) is supplied.

During the following one horizontal horizontal period (time T in FIG. 16).
Filter calculation is performed in 3). That is, each PE 102 (j)
(J = 1 to 100) stores the received data Dij in the memory 121 at time T2, and within time T3,
The data is read from the memory 121, and the arithmetic circuit 12
2 performs the filter calculation, and the calculation result (DOUT
j) is stored again in the memory 121. This arithmetic operation is specifically shown below.

First, each PE 102 (j) has an SP 101
The received data Dij is given to the left. Each PE
102 (j-1) stores this data Dij in the memory 121.
To be stored. Next, each PE 102 (j-1) further supplies the data Dij stored in the memory 121 to the left side. Each PE 102 (j-2) stores this data Dij in the memory 121.

Next, each PE 102 (j) has an SP 101
The received data Dij is given to the right. Each PE
102 (j + 1) stores this data Dij in the memory 121.
To be stored. Next, each PE 102 (j + 1) further supplies the data Dij stored in the memory 121 to the right next. Each PE 102 (j + 2) stores this data Dij in the memory 121.

By this series of operations, each PE 102 is
In (j), the data Dij received from SP101
And adjacent PE 102 (j-1) and PE 102 (j-
2), PE102 (j + 1) and PE102 (j + 2)
Data received from Dij-1, Dij-2, Dij
That is, +1 and Dij + 2 are stored in the memory 121.

Each PE 102 (j) sequentially receives data Dij-1, Dij-2, Dij + from the memory 121.
1 and Dij + 2 are read out and supplied to the arithmetic circuit 122 in the PE 102 (j). In the arithmetic circuit 122, COEa, COEb, COEc, COEd, C are sequentially added to these data.
OEe is multiplied and the result is accumulated. The cumulative result finally obtained, Are again stored in the memory 121.

This completes the "desired operation".

Therefore, in the subsequent horizontal blanking period, DOUTj is serialized by PS104 and sequentially output from DOUT1 via the serial data output terminal (SOUT). That is, the data of the filter calculation result for one horizontal period (1H) is output in word (pixel) serial from the serial data output terminal (SOUT).

[0033]

Now, consider the case where the filter coefficient is shown in FIG. Those having a coefficient value other than 0 form a group, and those having a coefficient value of 0 continue between the groups. An example of such a filter coefficient is, for example, a ghost canceller. That is, in order to remove the ghost of the terrestrial TV broadcast, multiplication with such a "filter whose coefficient value is not 0 forms a group" may be performed.

When applying the filter shown in FIG. 19, as can be inferred from the example of the 5 Tap filter shown in FIG. 18, the time required for the calculation in the PE 102 (j) becomes too long. Therefore, it cannot be completed within one horizontal horizontal period (time T3 in FIG. 16), which makes calculation impossible.

That is, in PE 102 (j), You have to calculate. However, for example, Dij
-15 is PE 102 (j) at time T2 in FIG.
-15), and the data is stored in PE 102 (j-1) for use by PE 102 (j).
4), PE102 (j-13), ..., PE102 (j-)
I have to send it to the right next to 1). It takes too much time to transfer the data between the processor elements. Therefore, this calculation is too time consuming.

In order to shorten the data transfer time, it is sufficient to wire 15 adjacent processor elements so that the data can be transferred at one time, but this increases the wiring amount and the circuit scale is large. Too much,
Unrealistic.

That is, for example, when performing multiplication with "a filter whose coefficient value is not 0 forms a group", which is used in a ghost canceller, etc., a parallel processor having a conventional configuration requires a data transfer time. However, there is a problem in that the calculation cannot be completed during one horizontal horizontal period (time T3 in FIG. 16) because it takes too much time.

The present invention has been made in view of the above circumstances, and it is possible to efficiently perform multiplication with a filter whose coefficient value is not 0, which is used in a ghost canceller or the like, forms a group. It is intended to provide a processor.

[0039]

According to a first aspect of the present invention, there is provided a parallel processor, comprising: a plurality of serial / parallel conversion means for converting a plurality of serially input first data into parallel data; and a plurality of serial / parallel conversion means. A plurality of arithmetic means for inputting parallelized first data from the means in parallel and arithmetic processing, and second data generated by arithmetic operation by the arithmetic means are input in parallel, and the second data is serialized. A parallel / serial conversion means for converting and outputting serially is provided.

The plurality of serial / parallel conversion means can input the first data at the same timing and can perform the parallel conversion by shifting the timing between the plurality of serial / parallel conversion means.

The first data is a video signal, and the calculation performed by the calculation means can be a filter process for a ghost canceller.

According to a fourth aspect of the present invention, there is provided a parallel processor in which serial / parallel conversion means for converting a plurality of first data input in serial into parallel data and first parallelized data from the serial / parallel conversion means. Parallel / serial inputting a plurality of arithmetic means for inputting data in parallel and arithmetically operating, and second data inputted in parallel by the arithmetic means, serially converting the second data and serially outputting the second data In the parallel processor provided with the conversion means, there are a plurality of serial / parallel converters, and at least one of the plurality of serial / parallel converters has a register connected in series and the first data is provided in the first stage of the register. It is characterized in that the first data which is input and parallelized is taken out from each register output.

According to a fifth aspect of the present invention, there is provided a parallel processor in which a data delay means for delaying a plurality of serially input first data and a serial / serial converter for converting the delayed first data from the delay means into parallel data. The parallel conversion means and a plurality of arithmetic means for inputting the first data parallelized by the serial / parallel conversion means in parallel and performing arithmetic processing, and the second data generated by arithmetic operation by the arithmetic means in parallel. And parallel / serial conversion means for serially converting the second data to serially output the second data.

Of the first data, the delay unit can delay the time when the data that is not necessary for the arithmetic processing in the arithmetic unit is input.

[0045]

According to the parallel processor of claim 1, the serial / parallel conversion means shifts the timing of the serial / parallel conversion, and the plural arithmetic means perform arithmetic processing so that the parallel processor is used in a ghost canceller or the like. A coefficient having a non-zero coefficient value can efficiently perform multiplication with a filter forming a group.

According to another aspect of the parallel processor of the present invention, the serial / parallel conversion means in which a plurality of registers are connected in series inputs the first data to the first stage of the registers, and the parallelized first data is output from each register output. Is taken out, the timing of serial / parallel conversion is shifted, and arithmetic processing is performed by the arithmetic means to efficiently perform multiplication with a filter whose coefficient value that is not 0, such as used in a ghost canceller, forms a group. To be able to do.

According to another aspect of the parallel processor of the present invention, the ghost canceller is provided by delaying the data input by the data delaying means with a sufficient time difference and performing serial / parallel conversion, and performing arithmetic processing by the plurality of arithmetic means. When the coefficient value is not 0 as used in, it is possible to efficiently perform multiplication with a filter forming a group.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 relate to the first embodiment of the present invention, FIG. 1 is a block diagram showing the configuration of a parallel processor, FIG. 2 is a block diagram showing the configuration of the processor element of FIG. 1, and FIG. 3 is a timing chart for explaining the operation of the parallel processor of No. 1.

Conventionally, there was one serial / parallel converter as shown in FIG. 10, but in this embodiment,
Multiple serial / parallel converters are available. Specifically, for example, as shown in FIG. 1, it has three serial / parallel converters (SP) 1, 2, and 3. SP
1, SP2, SP3 are serial / parallel converters, respectively. Each of SP1, SP2, and SP3 has the same configuration as SP101 shown in FIG. 11 which is a conventional example (see FIG. 1).
1)).

In FIG. 1, reference numerals 4 (1) to 4 (10
Reference numeral 0) is a processor element (PE), which is a conventional example PE102 (1) to PE102 shown in FIG.
It has almost the same configuration as (100). However, each PE4
(J) (j = 1 to 100) is the PE 102 of the conventional example.
In (j), as shown in FIG. 13, the number of input terminals from the serial / parallel converter is one (PEIN), whereas in the present embodiment, PE4 (j) in FIG. 3 input terminals (PEIN1, PEIN) so that data from SP1, SP2, SP3 can be received.
2, PEIN 3) Each input terminal (PEIN
The data from 1, PEIN2, PEIN3) can be stored in the memory 121 as in the conventional example.

Further, as in the conventional case, PE4 (1) to PE4
There is only one control circuit 103 for controlling 4 (100), which is common to all 100 processor elements. That is, FIG. 1 shows a SIMD (Single Instruction Multiple Data) parallel processor having the same number of processor elements as the number of data (100) for one horizontal period.

The description of the other parts is the same as that described in the conventional example, the same symbols are given, and the description thereof is omitted.

In the configuration of FIG. 1 which is the present embodiment,
The operation of applying the filter shown in FIG. 9 will be described in detail below with reference to FIG.

The video signal is a serial data input terminal (SIN) of SP1 and a serial data input terminal (SI of SP2).
N), common to the serial data input terminal (SIN) of SP3, and at the same time, word (pixel) serial data is supplied (time T11 in FIG. 3).

Then, 15 cycles before the first data of one horizontal period shown in FIG. 3A is input, the data shown in FIG.
As shown in, the write pointer input terminal (WP
TR), input an ON signal. As a result, FIG.
, The first input data (D
In i1), since the ON signal is sent to the delay element 112 (16), the switch 113 (16) is turned ON,
It is stored in the register 111 (16). Since the ON signal of the next input data (Di2) is sent to the delay element 112 (17) and the switch 113 (17) is turned on,
It is stored in the register 111 (17). Thereafter, similarly, the input data (Di3 to Di85) is transferred to the register 111
(18) to the register 111 (100). That is, 15 dummy data before D1 is input and D
The data of i1 to Di85 are stored in the registers 111 (1) to 111 (100) of SP1, respectively.

After being stored (at time T1 in FIG. 3)
2), register 1 of SP1 as shown in FIG.
The data in 11 (1) to the register 111 (100) is
PEIN of PE4 (1) to PE4 (100), respectively
1 is stored in the memory 121 of PE4 (1) to PE4 (100) (see FIG. 2).

Immediately before the first data in one horizontal period in FIG. 3A is input, an ON signal is input from the write pointer input terminal (WPTR) of SP2, as shown in FIG. 3C. To do. Thus, referring to FIG. 11, in SP2, the first input data (Di1)
Of the register 111 because the ON signal is sent to the delay element 112 (1) and the switch 113 (1) is turned on.
It is stored in (1). As for the next input data (Di2), the ON signal is sent to the delay element 112 (2) and the switch 113 (2) is turned on. Therefore, the register 111 (2)
Stored in. After that, input data (Di3 ...
Di100) is the register 111 (3) to the register 11
1 (100). That is, one horizontal period (1H)
The minute data Di1 to Di100 are stored in the registers 111 (1) to 111 (100) of the SP2, respectively.

After being stored (at time T1 in FIG. 3)
3), as shown in FIG. 3E, register 1 of SP2
The data in 11 (1) to the register 111 (100) is
PEIN of PE4 (1) to PE4 (100), respectively
2 is stored in the memory 121 of PE4 (1) to PE4 (100) (see FIG. 2).

Further, 15 cycles after the first data of one horizontal period shown in FIG. 3A is input, the data shown in FIG.
As shown in, the write pointer input terminal (WP
TR), input an ON signal. As a result, FIG.
Referring to SP16, the 16th input data (Di16) is stored in the register 111 (1) because the ON signal is sent to the delay element 112 (1) and the switch 113 (1) is turned ON. . Next input data (D
i17) is stored in the register 111 (2) because the ON signal is sent to the delay element 112 (2) and the switch 113 (1) is turned on. Thereafter, similarly, the input data (Di18 to Di100) is transferred to the register 111
(3) to the register 111 (85). Then, 15 pieces of dummy data input after Di100 are registered in the registers 111 (86) to 111 (10).
0). That is, Di16 to Di100 and 15
Each of the dummy data is the register 111 of SP3.
(1) to the register 111 (100).

After being stored (at time T1 in FIG. 3)
4), as shown in FIG. 3E, register 1 of SP3
The data in 11 (1) to the register 111 (100) is
PEIN of PE4 (1) to PE4 (100), respectively
3 is stored in the memory 121 of PE4 (1) to PE4 (100).

After these data are stored, a desired calculation is performed (described later). That is, in FIG.
(J) (j = 1 to 100) is the time T12, 13, 14
In the received data Dij-15, Dij, D
ij + 15 is read from the memory 121, and the arithmetic circuit 1
The calculation is performed at 22, and the calculation result (DOUTi) is stored again in the memory 121. This control is performed by the control circuit 103.

After the calculation, DOUT is output as in the conventional case.
1 to DOUT100, PS10
4 parallel data input terminals (PIN1 to PIN10
0) through the registers 131 (1) to 131 in the PS104.
It is supplied to the register 131 (100). Then, the data (DOUT1 to DOUT) of the calculation result for one horizontal period (1H)
OUT100) is serialized, and is output in word (pixel) serial from the serial data output terminal (SOUT).

The above "desired calculation" will be described in detail.

First, after time T12, each PE4 (j)
Is the data Dij− received from SP1 at time T12.
Give 15 to the left. Each PE 4 (j-1) stores this data Dij-15 in the memory 121.

Next, each PE4 (j) is set to S at time T12.
The data Dij-15 received from P1 is given to the right. Each PE 4 (j + 1) stores this data Dij-15 in the memory 121.

Through this series of operations, each PE4 (j) receives the data Dij-15 received from SP1 and the data Dij-1 received from the adjacent processor element.
6 and Dij-14 are stored in the memory 121.

Next, after time T13, each PE4 (j)
Gives the data Dij received from SP2 at the time T13 to the left. Each PE4 (j-1) uses this data D
ij is stored in the memory 121. Next, each PE4 (j-
In 1), the data Dij now stored in the memory 121 is further provided to the left. Each PE 4 (j-2) stores this data Dij in the memory 121.

Next, each PE4 (j) makes S at time T13.
The data Dij received from P2 is given to the right. Each PE 4 (j + 1) stores this data Dij in the memory 121.
To be stored. Next, each PE (j + 1) is now in memory 1
The data Dij stored in 21 is further provided on the right side.
Each PE4 (j + 2) stores this data Dij in the memory 12
Store in 1.

Through this series of operations, each PE4 (j) receives data Dij received from SP2 and data Dij-1 and Di received from the adjacent processor element.
That is, j−2, Dij + 1, and Dij + 2 are stored in the memory 121.

Next, after time T14, each PE4 (j)
Is the data Dij + received from SP3 at time T14
Give 15 to the left. Each PE 4 (j-1) stores this data Dij + 15 in the memory 121.

Next, each PE4 (j) is set to S at time T14.
The data Dij + 15 received from P3 is given to the right. Each PE (j + 1) stores this data Dij + 15 in the memory 121.

Through this series of operations, each PE4 (j) receives data Dij + 15 received from SP3 and data Dij + 1 received from the adjacent processor element.
4 and Dij + 16 are stored in the memory 121.

By the above operation, Dij-16, Dij-15, Dij- are stored in the memory 121 of each PE 4 (j).
14, Dij-2, Dij-1, Dij, Dij + 1,
Dij + 2, Dij + 14, Dij + 15, Dij + 1
6 is stored.

Each PE 4 (j) sequentially receives Dij-16, Dij-15, Dij-14, and Di from the memory 121.
j-2, Dij-1, Dij, Dij + 1, Dij +
2, Dij + 14, Dij + 15, Dij + 16 are read out and supplied to the arithmetic circuit 122 in PE4 (j). In the arithmetic circuit 122, COEa0, COE are sequentially added to these data.
Eb0, COEc0, COEa1, COEb1, COE
c1, COEd1, COEe1, COEa2, COEb
2, COEc2 is multiplied and the result is accumulated.
The cumulative result finally obtained, Are again stored in the memory 121.

This is the end of the description of the "desired calculation".

Conventionally, data (“Dij-16, Dij-15, Dij-
14 "and" Dij-2, Dij-1, Dij, Dij + "
1Dij + 2 ”and“ Dij + 14, Dij + 15, Di
j + 16 "), it is necessary to bring necessary data to each processor element by exchanging data with adjacent processor elements.

However, according to the present invention, in the case of data that are input with a sufficient time separation, by shifting the timing of each of the plurality of serial / parallel converters,
Since necessary data can be brought to each processor element or a processor element in the vicinity thereof without transferring data to and from the adjacent processor element, the data transfer time can be shortened. Therefore, the calculation can be completed within one horizontal horizontal period.

That is, according to this embodiment, serial / parallel conversion can be performed at different timings. For example, when the filter shown in FIG. 19 is applied, the timings of the three serial / parallel converters SP1, SP2, and SP3 are shifted by 15 cycles, so that PE4 (j) changes SP1 to Dij-15. ,
It is possible to supply PE (j) from SP2 to Dij and PEi from SP3 to Dij + 15, so that it does not take time to transfer data between processor elements as in the conventional case.

The serial data input terminal (SIN) of SP1 and the serial data input terminal (SI of SP2)
N), since the same common signal is given to the serial data input terminals (SIN) of SP3, the three serial data input terminals (SIN) may be combined into one to be one input terminal. At this time, from the serial data input terminal (SIN) of SP1 to the switches 113 (1), 11 of SP1.
Bus lines to 3 (2), ..., 113 (100) and SP2
From the serial data input terminal (SIN) of SP2 to switches 113 (1), 113 (2), ..., 113 (10) of SP2.
0) bus line and SP3 serial data input terminal (SIN) to SP3 switches 113 (1), 113
The bus lines to (2), ..., 113 (100) are common bus lines.

Next, the second embodiment will be described. 4 to 7 relate to the second embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of a parallel processor, FIG. 5 is a block diagram showing a configuration of the SPR of FIG. 4, and FIG. 6 is a block diagram of the SPR of FIG. FIG. 7 is a timing diagram for explaining the operation, and FIG. 7 is a block diagram showing the configuration of the processor element of FIG. Since the second embodiment is almost the same as the first embodiment, only different configurations will be described, the same configurations will be denoted by the same reference numerals, and description thereof will be omitted.

Conventionally, there was one parallel type serial / parallel converter as shown in FIG. 11, but in the present embodiment, a plurality of serial type and parallel type serial / parallel converters are prepared. are doing.

Specifically, for example, as shown in FIG.
It has one parallel type serial / parallel converter (SP) 1 and one serial type serial / parallel converter (SPR) 11.

At different timings (time T42, T43, T44, T45, T46, T in FIG. 5 described later).
47, T48), each PE 12 (j) can receive arbitrary data by receiving the data from the serial-type serial / parallel converter. For example, in the case of applying the filter shown in FIG. 19, by receiving data from the SPR 12 at the timing of time T42, P
E12 (j) to SPR11 to Dij-15 to PE12
(J) can be supplied, and it does not take time to transfer data between processor elements as in the conventional case.

Here, the serial type serial / parallel converter will be described.

As shown in FIG. 5, the serial-type serial-to-parallel converter SPR11 includes registers 21 (1) to 21 (21).
There is (100). Registers 21 (1) to 21 (10
0) are connected in series, and data from the serial data input terminal (SINR) is stored in the register 21 (10
0), register 21 (99), ..., Register 21
(2), it is sequentially sent to the register 21 (1). The output of the register 21 (j) (j = 1 to 100) is output from the parallel data output terminal (POUTRj). As shown in FIG. 6A, data Di1, Di2, Di serially input from the SINR during the time T41 period.
, ..., Di99, and Di100 shift on the registers 21 (100) to 21 (1), respectively.

That is, at each time, POUTRj (j
= 1 to 100), the data shown in FIG. 6B is output. Particularly, at time T42, “15 dummy data before Di1 is input” and “input data Di1 are input.
~ Di85 "are POUTRj (j = 1 to 1), respectively.
00). At time T43, “Di
"2 dummy data before 1 is input" and "input data Di1 to Di98" are respectively POUTRj (j
= 1 to 100).

At time T44, "one dummy data before Di1 is input" and "input data Di1 to Di1".
Di99 ”are POUTRj (j = 1 to 10), respectively.
0) is output. At time T45, the “input data Di1 to Di100” are respectively POUTRj.
(J = 1 to 100). At time T46, “Input data Di2 to Di100” and “Di10” are input.
One piece of dummy data after 0 is input is output from POUTRj (j = 1 to 100), respectively.
At time T47, “input data Di3 to Di10 is displayed.
"0" and "two dummy data after Di100 is input" are output from POUTRj (j = 1 to 100), respectively. At time T48, “input data D
i16 to Di100 ”and“ 15 dummy data after Di100 are input ”are respectively POUTRj
(J = 1 to 100).

Returning to FIG. 4, the parallel processor of this embodiment is
It will be described in more detail. A processor element (PE) 12 (j) (j = 1 to 100) shown in FIG.
PE102 (1) to PE102 (10 shown in the conventional example
It is almost the same as 0). However, each PE 12 (j) (j =
1 to 100) has one input terminal from the serial / parallel converter (PEI) as shown in FIG. 13 in the conventional example.
N), the PE 12 of FIG.
(J) has two input terminals (PEIN) so that the data from SP1 and SPR11 can be received as shown in FIG.
1, PEIN 2) Each input terminal (PEIN
The data from 1, PEIN2) can be stored in the memory 121. Further, as in the conventional case, there is only one control circuit 103 for controlling each processor element (PE1 to PE100), and it is common to all 100 processor elements. That is, FIG. 4 shows a SIMD (Single Instrument) having the same number of processor elements as the number of data (100) for one horizontal period.
It is a parallel processor of the method Multiple Data).

The description of the other parts is the same as that of the first embodiment, and the same symbols are attached and the description thereof is omitted.

Now, the operation in the case of applying the filter shown in FIG. 18 in the configuration of FIG. 4 which is an embodiment of the present invention will be described in detail below.

The video signal is supplied in word (pixel) serial from the SNR SINR (time T41 in FIG. 6).

At time T43 in FIG. 6, POUTRj
From (j = 1 to 100), register 21
The data stored in (j) is assigned to P of each PE 12 (j).
It is stored in the memory 121 of each PE 12 (j) via EIN2. Thereby, PE12 (1) to PE12
(100) In each memory 121, “two dummy data before Di1 is input” and “input data D
i1-Di98 "is stored.

At time T44 in FIG. 6, POUTRj
From (j = 1 to 100), register 21
The data stored in (j) is assigned to P of each PE 12 (j).
It is stored in the memory 121 of each PE 12 (j) via EIN2. Thereby, PE12 (1) to PE12
In each memory 121 of (100), "Di1
"One piece of dummy data before being input" and "input data Di1 to Di99" are stored.

At time T45 in FIG. 6, POUTRj
From (j = 1 to 100), register 21
The data stored in (j) is assigned to P of each PE 12 (j).
It is stored in the memory 121 of each PE 12 (j) via EIN2. Thereby, PE12 (1) to PE12
"Input data Di1 to Di100" are stored in each memory 121 of (100).

At time T46 in FIG. 6, POUTRj
From (j = 1 to 100), register 21
The data stored in (j) is assigned to P of each PE 12 (j).
It is stored in the memory 121 of each PE 12 (j) via EIN2. Thereby, PE12 (1) to PE12
In each memory 121 of (100), "input data Di2 to Di100" and "one piece of dummy data after Di100 is input" are stored.

At time T47 in FIG. 6, POUTRj
From (j = 1 to 100), register 21
The data stored in (j) is assigned to P of each PE 12 (j).
It is stored in the memory 121 of each PE 12 (j) via EIN2. Thereby, PE12 (1) to PE12
In each memory 121 of (100), "input data Di3 to Di100" and "two dummy data after Di100 are input" are stored, respectively.

After these data are stored in the memory 121, a desired calculation is performed. That is, each PE 12 (j)
(J = 1 to 100) are times T43, T44, T45,
At T46 and T47, the received data Dij-
2, Dij-1, Dij, Dij + 1, Dij + 2,
The data is sequentially read from the memory 121 and A in PE12 (j) is read.
The data is supplied to the LU, and in the arithmetic circuit 122, COEa, COEb, COEc, COEd, COEe are sequentially added to these data.
Is multiplied and the result is accumulated. The cumulative result finally obtained, Are again stored in the memory 121. This control is performed by the control circuit 1
03.

After the calculation, DOUT is output as in the conventional case.
1 to DOUT100 are supplied to the registers 131 (1) to 131 (100) in the PS104 via the parallel data input terminals PIN1 to PIN100 of the PS104. Then, the data (DOUT1 to DOUT100) of the operation result for one horizontal period (1H) is serialized,
Word (pixel) serial output from SOUT.

As described above, by using the serial type serial / parallel converter SPR11, the video signals (Di1 to Di1) can be obtained.
00) is parallelized, so POUT is changed at each time.
The data output from j (j = 1 to 100) is different. As described above, the times T43, T44, T45, T4
Data is sent to each PE12 at different times of 6 and T47.
By supplying the data to (j), each PE 12 (j) receives the data D.
ij-2, Dij-1, Dij, Dij + 1, Dij +
2 can be received directly from the SPR.

Therefore, since it is not necessary to transfer data between the processor elements as in the conventional case, the processing time is shortened.

Of course, since the serial type serial / parallel converter is used in the present invention, the power consumption becomes large as compared with the case of using the conventional parallel type serial / parallel converter. If you prioritize power consumption,
In FIG. 4, SP1 is used and SPR11 is not used. That is, the video signals (Di1 to Di100) are supplied from the SIN of SP1 of FIG.
Dij is POUTj and PEIN1 of each PE12 (j)
To the memory 121 of each PE 12 (j).
Then, as in the conventional case, data may be transferred between the processor elements and the calculation may be performed.

That is, in this embodiment, the SPR11 is used when the calculation time is prioritized, and the SP1 is used when the power consumption is prioritized. in this way,
Conventionally, there was no right to select which of calculation time and power consumption should be prioritized, but in the present embodiment, it can be selected.

Next, referring to FIG.
A detailed description will be given below of the operation when the filter shown in FIG.

The video signal is supplied in word (pixel) serial from the SINR of SPR11 (time T4 in FIG. 6).
1).

At time T42 in FIG. 6, POUTRj
From (j = 1 to 100), the data stored in Qi is passed through PEIN2 of each PE12 (j),
The memory 121 of each PE 12 (j) is stored in the memory 121. As a result, each memory 12 of PE1 to PE100
1 stores "15 dummy data before Di1 is input" and "input data Di1 to Di85", respectively.

At time T45 in FIG. 4, POUTRj
From (j = 1 to 100), register 21
The data stored in (j) is assigned to P of each PE 12 (j).
It is stored in the memory 121 of each PE 12 (j) via EIN2. Thereby, PE12 (1) to PE12
"Input data Di1 to Di100" are stored in each memory 121 of (100).

At time T48 in FIG. 4, POUTRj
From (j = 1 to 100), register 21 (j)
The data stored in the PEIN of each PE12 (j)
2 is stored in the memory 121 of each PE 12 (j). Thereby, PE12 (1) to PE12 (10
0) In each memory 121, "input data D
"i16 to Di100" and "15 dummy data after Di100 is input" are stored.

After these data are stored, a desired calculation is performed (described later). That is, each PE 12 (j) (j = 1
˜100), at time T42, 45, 48, the received data Dij-15, Dij, Dij + 15 are
The data is read from the memory 121, the calculation is performed by the calculation circuit 122, and the calculation result (DOUTi) is stored again in the memory 121. This control is performed by the control circuit 103.

After the calculation, DOUT is output as in the conventional case.
1 to DOUT100 are supplied to the registers 131 (1) to 131 (100) in the PS1 and 4 via the parallel data input terminals PIN1 to PIN100 of the PS104. Then, the data (DOUT1 to DOUT100) of the operation result for one horizontal period (1H) is serialized,
Word (pixel) serial output from SOUT.

The above "desired calculation" will be described in detail.

First, after time T42, each PE 12
(J) gives the data Dij-15 received from the SPR 11 at time T42 to the left. Each PE12 (j-
1) stores this data Dij-15 in the memory 121.

Next, each PE 12 (j) supplies the data Dij-15 received from the SPR 11 at time T42 to the right adjacent. Each PE 12 (j + 1) has this data Dij
-15 is stored in the memory 121.

By this series of operations, each PE 12 (j)
Is the data Dij-15 received from SPR11.
And the data D received from the adjacent processor element
That is, ij-16 and Dij-14 are stored in the memory 121.

Next, after time T45, each PE 12
In (j), the data Dij received from the SPR 11 at time T45 is provided to the left. Each PE12 (j-1) is
This data Dij is stored in the memory 121. Next, each PE 12 (j-1) further supplies the data Dij stored in the memory 121 to the left side. Each PE12 (j-
2) stores this data Dij in the memory 121.

Next, each PE 12 (j) supplies the data Dij received from the SPR 11 at time T45 to the right adjacent. Each PE 12 (j + 1) stores this data Dij in the memory 121. Next, each PE 12 (j + 1)
Now, the data Dij stored in the memory 121 is further provided on the right side. Each PE 12 (j + 2) has this data Di
j is stored in the memory 121.

Through this series of operations, each PE (j) receives the data Dij received from the SPR11 and the data Dij-1 received from the adjacent processor element,
Dij−2, Dij + 1, and Dij + 2 are stored in the memory 121.

Next, after the time T48, each PE 12
(J) gives the data Dij + 15 received from the SPR 11 at time T48 to the left. Each PE12 (j-
1) stores the data Dij + 15 in the memory 121.

Next, each PE 12 (j) supplies the data Dij + 15 received from the SPR 11 at time T48 to the right adjacent. Each PE 12 (j + 1) has this data Dij
+15 is stored in the memory 121.

By this series of operations, each PE 12 (j)
Is the data Dij + 15 received from SPR11.
And the data D received from the adjacent processor element
That is, ij + 14 and Dij + 16 are stored in the memory 121.

By the above operation, Dij-16, Dij-15, Dij are stored in the memory 121 of each PE 12 (j).
-14, Dij-2, Dij-1, Dij, Dij +
1, Dij + 2, Dij + 14, Dij + 15, Dij
+16 is stored.

Each PE 12 (j) is
Sequentially, Dij-16, Dij-15, Dij-14, D
ij-2, Dij-1, Dij, Dij + 1, Dij +
2, Dij + 14, Dij + 15, Dij + 16 are read out and supplied to the arithmetic circuit 122 in PE12 (j). In the arithmetic circuit 122, COEa0, C
OEb0, COEc0, COEa1, COEb1, CO
Ec1, COEd1, COEe1, COEa2, COE
b2 and COEc2 are multiplied and the result is accumulated. The cumulative result finally obtained, Are again stored in the memory 121.

This is the end of the description of the "desired calculation".

As described above, by using the serial type serial / parallel converter SPR11, the video signals (Di1 to Di1) can be obtained.
00) is parallelized, so POUT is changed at each time.
The data output from j (j = 1 to 100) is different. As described above, by supplying data to each PE 12 (j) at different times of time T42, T45, T48, each PE 12 (j) receives data Dij-15, Dij ,.
Dij + 15 can be received directly from the SPR.

Therefore, unlike the prior art, it is not necessary to exchange data between processor elements so much.
Processing time is shortened.

Of course, in this embodiment, since the serial type serial / parallel converter is used, the power consumption becomes larger than that in the case of using the conventional parallel type serial / parallel converter. If power consumption is prioritized, SP1 is used and SPR is not used 11 in FIG. That is, a video signal (Di1 to Di100) is supplied from SIN of SP1 of FIG.
It is given to the memory 121 of each PE 12 (j) via N1. Then, as in the conventional case, data may be transferred between the processor elements and the calculation may be performed.

That is, in this embodiment, the SPR11 is used when the calculation time is prioritized, and the SP1 is used when the power consumption is prioritized. in this way,
Conventionally, there was no right to select which of calculation time and power consumption should be prioritized, but in the present embodiment, it can be selected.

Next, the third embodiment will be described. 8 and 9 relate to the third embodiment of the present invention, FIG. 8 is a block diagram showing a configuration of a parallel processor, and FIG. 9 is a timing diagram illustrating an operation of the parallel processor of FIG. Since the third embodiment is almost the same as the first embodiment, only different configurations will be described, the same configurations will be denoted by the same reference numerals, and description thereof will be omitted.

For example, since the image data has 8 bits, the register 111 (j) of SP1 shown in FIG. 1 (j =
1 to 100) are registers each capable of storing 8-bit data. In addition, the switch 113 (j) (j =
1 to 100) are switches each having an 8-bit width. Then, from SIN, the switches 113 (1), 113
The bus lines to (2), ..., 113 (100) are 8 bits wide.

The serial / parallel converters of the prior art and the above-described embodiments have an 8-bit width as described above, but in the present embodiment, the bit width of the serial / parallel converter is expanded to A delay circuit is prepared for the input section.

Specifically, for example, as shown in FIG. 8, the serial / parallel converter (SP) 31 has a bit width of 24.
It is a bit and has delay circuits 32 and 33 at its input.

By using the delay circuits 32 and 33,
The same input data can be input to SP31 at different timings. For example, when the filter shown in FIG. 19 is applied, the delay circuits 32 and 33 adjust the timing to 15
It is possible to input three sets of input data that are shifted by each cycle to the SIN of the SP31 having a 24-bit width.

Therefore, the PE 102 (j) has Dij-1.
5, Dij, Dij + 15 can be supplied, and it takes no time to transfer data between processor elements as in the conventional case.

Further, FIG. 8 will be described in detail. The SP 31 has almost the same configuration as the SP shown in FIG. 12 which is a conventional example. However, the conventional example has a width of 8 bits, but the present embodiment has a width of 24 bits. That is, in FIG. 11, the register 111 (j) (j = 1
.About.100) are registers each capable of storing 24-bit data. Switch 113 (j) (j = 1 to 1
00) are switches each having a width of 24 bits. Then, from SIN, the switches 113 (1), 113
The bus lines to (2), ..., 113 (100) are 24 bits wide.

The delay circuits 32 and 33 are circuits for delaying 8-bit wide data. If the delay amount is made variable and the delay amount can be changed by an external control, versatility comes out. However, here, the delay amount is fixed to 15 cycles in order to simplify the description.

The input data (8 bits) serially supplied to the word (pixel) is directly input to the lower 8 bits of SIN of SP31. Also, input data (8 bits)
Is input to the delay circuit 32, and the delay circuit 32
Thus, the data delayed by 15 cycles is input to the middle 8 bits of SP SIN. Further, the data (8 bits) from the delay circuit 32 is input to the delay circuit 33, and the data delayed by 15 cycles by the delay circuit 33 is input to the upper 8 bits of SIN of SP.

The description of the other parts is the same as that described in the conventional example, and the same symbols are attached and the description thereof is omitted.

Now, the operation of the filter shown in FIG. 19 in the configuration of FIG. 8 which is an embodiment of the present invention will be described in detail below.

Data which is a video signal is supplied in word (pixel) serial as shown in FIG. This data is delayed by 15 cycles by the delay circuit 32, as shown in FIG.

This data is further delayed by the delay circuit 33 for another 15 cycles as shown in FIG. 9 (c).

These data (the data shown in FIGS. 9A to 9C) are respectively the lower 8 bits of SP31,
It is sent to the middle 8 bits and the upper 8 bits.

Immediately before the data of FIG. 9B is sent to the SP, as shown in FIG. 9D, an ON signal is input from the WPTR of SP31.

Immediately after the ON signal is input, Di16 is input below the SIN. Therefore,
In the 16th input data (Di16), the ON signal is sent to the delay element 112 (1) and the switch 113 (1)
Is turned on, and is stored in the register 111 (1). The next input data (Di17) is stored in the register 111 (2) because the ON signal is sent to the delay element 112 (2) and the switch 113 (2) is turned on.
After that, input data (Di18 to Di100) is similarly processed.
Are stored in the registers 111 (3) to 111 (85). Then, the registers 111 (86) to 111 (10
0) is not input. That is, Di16 to Di100 and 15 pieces of dummy data (indeterminate values) are stored in the lower order of the registers 111 (1) to 111 (100), respectively (see FIG. 12).

Immediately after the ON signal is input, the SIN
It means that Di1 is input to the middle position. Therefore, in the first input data (Di1), the ON signal is sent to the delay element 112 (1) and the switch 113 (1)
Is turned on, and is stored in the register 111 (1). The next input data (Di2) is stored in the register 111 (2) because the ON signal is sent to the delay element 112 (2) and the switch 113 (2) is turned on. Thereafter, similarly, the input data (Di3 to Di100) is
It is stored in the registers 111 (3) to 111 (100). That is, Di1 to Di100 are register 1
It is stored in the middle of 11 (1) to 111 (100).

Also, when the first input data (Di1) is input to the upper part of SIN, the ON signal changes to the delay element 112.
Since it has been sent to (16), switch 113 (16)
Is turned on and stored in the register 111 (16).
For the next input data (Di2), the ON signal is the delay element 11
2 (17) and the switch 113 (17) is turned on, and is stored in the register 111 (17).
Thereafter, similarly, the input data (Di3 to Di85) is
It is stored in the registers 111 (18) to 111 (100). That is, the 15 dummy data before Di1 is input and the data of Di1 to Di85 are respectively stored in the register 1
It is stored in the higher order of 11 (1) to 111 (100).

In this way, the data input during the time T51 in FIG. 9 is transferred to the registers 111 (1) to 111 (100) in the high-order, middle-order, and high-order as shown in FIG. 9 (e).
It is stored in the lower order. That is, the register 111 (j) (j =
1-100), the upper, middle, and lower are Dij + 15,
Dij and Dij-15 are stored.

Immediately after time T51, the data shown in FIG. 9 (e) is stored in the registers 111 (1) to 111 (100), so that POUT1 to POUT10 of SP31 are stored.
0 through PE 102 (1) to PE 102 (100)
Stored in the memory 121.

After these data are stored, a desired calculation is performed (described later). That is, each PE 102 (j) (j =
Immediately after time T51, the received data Dij-15, Dij, and Dij + 15 are read from the memory 121, and the arithmetic circuit 122 performs arithmetic operation.
The calculation result (DOUTj) is stored again in the memory 121. This control is performed by the control circuit 103.

After the calculation, DOUT is output as in the conventional case.
1 to DOUT100 are supplied to the registers 131 (1) to 131 (100) in the PS104 via the parallel data input terminals PIN1 to PIN100 of the PS104. Then, the data (DOUT1 to DOUT100) of the operation result for one horizontal period (1H) is serialized,
Word (pixel) serial output from SOUT.

The above "desired calculation" will be described in detail.

First, after receiving data from SP31 via POUTj, each PE 102 (j)
The received data Dij-15 is given to the left.
Each PE 102 (j-1) stores this data Dij-15 in the memory 121.

Next, each PE 102 (j) supplies the data Dij-15 received from SP31 to the right adjacent. Each PE 102 (j + 1) stores this data Dij-15 in the memory 121.

By this series of operations, each PE 102 is
(J) shows the data Dij-1 received from SP31.
5 and the data Dij-16 and Dij-14 received from the adjacent processor element are stored in the memory 121.

Next, each PE 102 (j) supplies the data Dij received from SP31 to the left adjacent. Each PE1
02 (j-1) stores the data Dij in the memory 121. Next, each PE 102 (j-1) further supplies the data Dij stored in the memory 121 to the left side. Each PEi-2 stores this data Dij in the memory 121.
To be stored.

Next, each PE 102 (j) supplies the data Dij received from SP31 to the right adjacent. Each PE1
02 (j + 1) stores this data Dij in the memory 121. Next, each PE 102 (j + 1) further supplies the data Dij stored in the memory 121 to the right next. Each PE 102 (j + 2) stores this data Dij in the memory 121.

By this series of operations, each PE 102 is
In (j), the data Dij received from SP31,
Data Dij received from the adjacent processor element
-1, Dij-2, Dij + 1, Dij + 2 are the memory 1
It is stored in 21.

Next, each PE 102 (j) supplies the data Dij + 15 received from SP31 to the left side. Each PE 102 (j-1) stores this data Dij + 15 in the memory 121.

Next, each PE 102 (j) supplies the data Dij + 15 received from SP31 to the right side. Each PE 102 (j + 1) stores this data Dij + 15 in the memory 121.

By this series of operations, each PE 102
In (j), the data Dij + 1 received from SP31
5 and the data Dij + 14 and Dij + 16 received from the adjacent processor element are stored in the memory 121.

By the above operation, Dij-16, Dij-15, Di are stored in the memory 121 of each PE 102 (j).
j-14, Dij-2, Dij-1, Dij, Dij +
1, Dij + 2, Dij + 14, Dij + 15, Dij
+16 is stored.

Each PE 102 (j) sequentially receives from the memory 121, Dij-16, Dij-15, Dij-1.
4, Dij-2, Dij-1, Dij, Dij + 1, D
ij + 2, Dij + 14, Dij + 15, Dij + 16
Is read out and supplied to the arithmetic circuit 122 in the PE 102 (j).
a0, COEb0, COEc0, COEa1, COEb
1, COEc1, COEd1, COEe1, COEa
2, COEb2, COEc2 are multiplied and the results are accumulated. The cumulative result finally obtained, Are again stored in the memory 121.

This is the end of the description of the "desired calculation".

Conventionally, data (“Dij-16, Dij-15, Dij-
14 "and" Dij-2, Dij-1, Dij, Dij + "
1Dij + 2 ”and“ Dij + 14, Dij + 15, Di
j + 16 "), it is necessary to bring necessary data to each processor element by exchanging data with adjacent processor elements. However, in the present embodiment, in the case of data that is input with a sufficient time separation, serial / serial data is delayed by the amount of the separation.
Since the data is input to the parallel converter and the necessary data can be brought to each processor element or the processor elements in the vicinity without transferring the data to and from the adjacent processor elements, the data transfer time can be shortened. You can do it.

Therefore, the calculation can be completed within one horizontal horizontal period.

[0165]

As described above, according to the parallel processor of the first aspect, since the timing of serial / parallel conversion is shifted by the plurality of serial / parallel conversion means and the arithmetic processing is performed by the plurality of arithmetic means, the ghost canceller. There is an effect that a filter having a coefficient value other than 0, which is used for example, can be efficiently multiplied with a filter forming a group.

According to the parallel processor of claim 4, the serial / parallel conversion means in which a plurality of registers are connected in series inputs the first data to the first stage of the registers, and the first output is parallelized from the output of each register. Data is taken out, the timing of serial / parallel conversion is shifted, and the arithmetic processing is performed by the arithmetic means, so that multiplication with a filter whose coefficient value is not 0, which is used in a ghost canceller, forms a group efficiently. There is an effect that can be done.

According to the parallel processor of the fifth aspect, the data delay means delays the data input with a sufficient time separation to perform serial / parallel conversion, and the arithmetic processing is performed by the plurality of arithmetic means. There is an effect that a filter having a coefficient value other than 0 as used in a canceller or the like can efficiently perform multiplication with a filter forming a group.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a parallel processor according to the present invention.

FIG. 2 is a block diagram showing a configuration of a processor element of FIG.

FIG. 3 is a timing chart illustrating the operation of the parallel processor of FIG.

FIG. 4 is a block diagram showing a configuration of a second embodiment of the present invention of a parallel processor.

5 is a block diagram showing the configuration of the SPR of FIG.

6 is a timing diagram illustrating an operation of SPR of FIG.

FIG. 7 is a block diagram showing a configuration of a processor element of FIG.

FIG. 8 is a block diagram showing a configuration of a parallel processor according to a third exemplary embodiment of the present invention.

9 is a timing diagram illustrating the operation of the parallel processor of FIG.

FIG. 10 is a block diagram showing a configuration of a conventional parallel processor.

11 is a block diagram showing the configuration of the SP shown in FIG.

12 is a timing diagram illustrating the operation of the SP shown in FIG.

13 is a block diagram showing a configuration of a processor element of FIG.

14 is a block diagram showing a configuration of PS of FIG.

FIG. 15 is a timing diagram illustrating the operation of the PS of FIG.

16 is a timing diagram illustrating the operation of the parallel processor of FIG.

17 is an explanatory diagram illustrating data processed by the parallel processor in FIG.

18 is an explanatory diagram illustrating a first example of filter processing performed by the parallel processor in FIG.

FIG. 19 is an explanatory diagram illustrating a second example of filter processing performed by the parallel processor in FIG. 10.

[Explanation of symbols]

 1,2,3 SP 4 (1) to 4 (100) PE 11 SPR 12 (1) to 12 (100) PE 21 (1) to 21 (100) Register 31 SP 32,33 Delay circuit 101 SP 102 (1) ) -102 (100) PE 103 control circuit 104 PS 111 (1) -111 (100) register 112 (1) -112 (100) delay element 113 (1) -113 (100) switch 121 memory 122 arithmetic circuit 131 ( 1) to 131 (100) register 132 (1) to 132 (100) delay element 133 (1) to 133 (100) switch

Claims (6)

[Claims] 1. A plurality of serial / parallel conversion means for converting a plurality of serially input first data into parallel data, and a plurality of parallelized first data from the plurality of serial / parallel conversion means. A plurality of arithmetic means for inputting in parallel and performing arithmetic processing, and parallel / serial for inputting in parallel the second data generated by the arithmetic operation by the arithmetic means, serially converting the second data, and outputting serially. A parallel processor, comprising: a conversion unit. 2. The plurality of serial / parallel conversion means inputs the first data at the same timing, and performs parallel conversion by shifting the timing between the plurality of serial / parallel conversion means. The parallel processor according to claim 1. 3. The parallel processor according to claim 1, wherein the first data is a video signal, and the operation performed by the operation means is a filter process for a ghost canceller. . 4. A serial / parallel conversion means for converting a plurality of first data input serially into parallel, and the parallelized first data from the serial / parallel conversion means being input in parallel. A plurality of arithmetic means for performing arithmetic processing, and a parallel / serial conversion means for inputting in parallel the second data calculated and generated by the arithmetic means, converting the second data serially, and outputting serially. In the parallel processor provided, there are a plurality of the serial / parallel converters, and at least one of the plurality of serial / parallel converters has a register connected in series, and the first data is provided in the first stage of the register. A parallel processor, characterized in that the first data is input and the parallelized first data is taken out from each register output. 5. A data delay means for delaying a plurality of first data inputted serially, a serial / parallel conversion means for parallel-converting the delayed first data from the delay means, The first data parallelized by the serial / parallel conversion means is input in parallel, and a plurality of arithmetic means for performing arithmetic processing, and the second data generated by the arithmetic operation by the arithmetic means are input in parallel. A parallel processor, comprising: parallel / serial conversion means for converting the second data to serial and outputting serially. 6. The delay means delays a time of the first data, which is not necessary for the arithmetic processing in the arithmetic means, to be input to the delay means. Item 5. A parallel processor according to item 5.