JPH08234877A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide the semiconductor integrated circuit which is equipped with a CMOS logic for keeping the logic level of a logical block at standby time and quickly responding at the time of operation recovery. CONSTITUTION: This circuit is provided with a power source 1, constant current source 2, large current block 3, small current block 4, and PMOS transistor 5. The large current block 3 shows a logical block out of the object of current consumption suppression, and the small current block 4 shows a logical block defined as the object of current consumption suppression at the standby time. At the standby time, the PMOS transistor 5 is turned off by inputting a standby signal at 'H' level to its gate and the current to be supplied from the power source 1 is suppressed to the standby current specified value of the semiconductor integrated circuit by the constant current source. Thus, the internal logic level of CMOS logic provided in the small current block 4 is held at prescribed level and when the normal operating state is recovered, the circuit can quickly respond to the normal operating state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit formed by a CMOS logic circuit.

[0002]

2. Description of the Related Art In general, a semiconductor integrated circuit formed by a conventional CMOS logic circuit has a function of suppressing current consumption during standby, and some improvements have been seen. As a known example of improving the function of suppressing current consumption during standby, for example, in a semiconductor integrated circuit including a plurality of logic blocks, a standby control circuit is provided for each of the logic blocks and the supply current to each logic block is switched. As an example of the method, there is a semiconductor integrated circuit device disclosed in JP-A-62-251819. In this known example, in an integrated circuit device configured by a plurality of logic blocks controlled by a horizontal microprogram,
As described above, the standby control circuit is provided for each logical block, the standby control circuit is selectively operated by the microprogram, and each logical block is selectively set to the standby state, so that the consumption in the standby state is achieved. It is characterized in that current is suppressed.
As its technical idea, as shown in FIG.
In a semiconductor integrated circuit composed of a plurality of logical blocks including block 1, block 2, block 3 and block 4 connected to the data bus 10 and the data bus 103, a plurality of blocks including block 1, block 2, block 3 and block 4 are provided. A standby register 11 functioning as a standby control circuit is provided for each of these logical blocks, and at the time of standby, a MOS transistor 17a according to the operation state is provided.
, 17b, 17c and 17d,
By selectively performing on / off control via the standby register 11 controlled by the microprogram, the power supply 16 supplies power to each logic block including the block 1, the block 2, the block 3, and the block 4. The feature is that selective control is performed according to the operating state.

[0003]

In the above-described conventional semiconductor integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 62-251819, a plurality of blocks formed by four blocks connected by a CPU and a data bus. The power supply to the logical block is controlled by a microprogram according to the operation state of each block, and among the blocks whose power supply is cut off, the internal level operation state is completely undefined. . For example,
In a flip-flop or the like forming a logic circuit in the block, power supply is cut off,
There is a drawback that the data held up to now cannot be held and the block cannot be operated immediately when the block is returned to normal operation and started.

[0004]

According to the semiconductor integrated circuit of the present invention, a first type logic block whose current consumption is suppressed during standby and a second type logic block which is not subject to current consumption suppression during standby are provided. In a semiconductor integrated circuit formed as a CMOS logic circuit including at least one or more, at a standby time, a predetermined power supply is used.
Circuit means for regulating a current value supplied to the first type logic block to a predetermined specified current value is provided on a power supply line connecting the power supply and a power supply terminal of the first type logic block. I have.

The circuit means may be constituted as a parallel circuit of a constant current source having the specified current value as a current value and a MOS transistor which is turned on / off by a predetermined standby signal. The MOS transistor may be configured as a PMOS transistor that is set to an ON state by an “H” level standby signal.

[0006]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CMOS logic circuit forming a semiconductor integrated circuit according to the present invention. As shown in FIG. 1, in this embodiment, a power source 1
Constant current source 2, large current block 3, small current block 4
And a PMOS transistor 5. The large current block 3 and the small current block 4 are logic blocks each including a plurality of CMOS logics. The large current block 3 indicates a logic block that is not subject to current consumption suppression. 3 shows a logic block to be reduced in current consumption. Of course, CMOS that constitutes a semiconductor integrated circuit
Depending on the configuration of the logic, the number of these logic blocks increases.

FIG. 2 is a diagram showing the internal structure of the small current block 4 whose current consumption is suppressed during standby. The CMOS circuit corresponds to the power source 1, the constant current source 2 and the PMOS transistor 5. Logic block (1) 6, CMOS logic block (2) 7, P
It is configured to include MOS transistors 8a and 8b and NMOS transistors 9a and 9b. Note that, in FIG. 2, the large current block 3 shown in FIG. 1 is omitted.

In FIG. 1, during a normal operation, a standby signal is input at an "L" level to the gate of a PMOS transistor 5 functioning as a switch, and the PMOS transistor 5 is turned on. Through the PMOS transistor 5, the low current block 4
Is supplied with a power supply voltage VDD from the power supply 1, and a sufficient current is supplied. Of course, the power supply voltage VDD is directly applied to the large current block 3, and the semiconductor integrated circuit including the large current block 3 and the small current block 4 is maintained in a normal operation state.

In the standby state, the standby signal 101 is at "H" level, whereby the PMOS transistor 5 functioning as a switch is turned off, and the current supplied from the power supply 1 to the low current block 4 is a constant current source. In this state, the operation is restricted by the current value obtained by the second operation. In the present embodiment, the current value of the constant current source 2 is set so as to conform to the standby current standard of the semiconductor integrated circuit, whereby the CMOS logic block (1) 6 included in the low current block 4 is set. The logic level held in the internal logic circuits constituting the CMOS logic block (2) 7 and the like is also held at a predetermined logic level corresponding to the standby current standard even in the standby mode. Block 4
However, even when the device returns from the standby state to the normal operation state, a state capable of immediately coping with the normal operation state is maintained. Further, even if a leak current occurs in the low-current block 4 during standby, the leak current is suppressed to the leak current value within the above-mentioned standard.

Referring to FIG. 2, an operation when a leak occurs in small current block 4 in the standby state will be described. In FIG. 2, CMOS logic block (1) 6 and CMOS logic block (2) 7
And the PMOS transistor 8a and the NMOS transistor 9a, which are assumed to be the circuit portion in which the leakage current is generated, are shown. The PMOS transistor 8b and the NMOS transistor 9a are shown corresponding to these MOS transistors.
Transistor 9b is shown. In FIG. 2, in the standby state, the CMOS logic block (1) 6
It is assumed that the “H” level is being output from the output terminal of “1”. As a result, the PMOS transistor 8a is turned off, and the NMOS transistor 9a is turned on.
It becomes the state of. Normally in such a situation, the PMO
Although no leakage current is generated from the S transistor 8a to the NMOS transistor 9a, it is assumed that a leakage current occurs between the drain and the source of the PMOS transistor 8a for some reason. When such a leakage current occurs, the leakage current of the PMOS transistor 8a flows to the ground via the NMOS transistor 9a. In this state, the level of the voltage V _DD2 supplied to the small current block 4 is slightly lowered to be in an equilibrium state. However, the current flowing into the small current block 4 including the leak current value is reduced by the constant current source 2. Of the supply voltage V _DD2 in the equilibrium state, the level of the PMOS transistor and NM included in the entirety of the small current block 4 is reduced.
The level is maintained at a level at which the operating functions of the OS transistor and the like are maintained.

[0012]

As described above, the present invention provides a CMO
The present invention is applied to a semiconductor integrated circuit formed by an S logic circuit, and regulates a current supplied to a logic block, which is included in the semiconductor integrated circuit and whose current consumption is to be reduced, to a predetermined standard current value during standby. In addition, the logic level in the logic block can be maintained at a predetermined value, and when returning from the standby state to the normal operation state, it is possible to immediately shift to the normal operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an internal configuration of a low current block according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 16 power supply 2 current source 3 large current block 4 low current block 5, 8a, 8b PMOS transistor 6 CMOS logic block (1) 7 CMOS logic block (2) 9a, 9b NMOS transistor 10 CPU 11 standby register 12 block (1) 13 block (2) 14 block (3) 15 block (4) 17a, 17b, 17c, 17d switch 101 standby signal 102 power supply line 103 data bus

Claims (3)

[Claims] 1. A CMOS logic circuit including at least one type 1 logic block for which current consumption is suppressed during standby and at least one type 2 logic block for which current consumption is not suppressed during standby. In a semiconductor integrated circuit according to the present invention, circuit means for restricting a current value supplied to the first type logic block from a predetermined power source to a predetermined specified current value during standby is provided with the power source and the power source of the first type logic block. A semiconductor integrated circuit provided on a power supply line for connecting a terminal. 2. The method according to claim 1, wherein the circuit means is turned on by a constant current source having the specified current value as a current value and a predetermined standby signal
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured as a parallel circuit with a MOS transistor controlled to be turned off. 3. A PM in which the MOS transistor is set to an ON state by an “H” level standby signal.
3. The semiconductor integrated circuit according to claim 2, which is configured as an OS transistor.