JPH0823458A - Synchronization detection circuit - Google Patents

Abstract

PURPOSE:To output a stable digital synchronizing signal independently of a level of a received composite video signal and to obtain a synchronization detection circuit detecting a synchronizing signal stably without malfunction by a noise signal. CONSTITUTION:A reference level generating circuit 11 generates a prescribed DC voltage at all times independently of the amplitude of an input signal. A DC conversion circuit 12 keeps a peak DC level of a synchronization of an input to be a reference level. An upper limit level setting circuit 13b and a lower limit level setting circuit 13c for discriminating a level for a synchronizing signal period. Thus, a synchronization level comparator circuit 13a is used to discriminate whether the level of the synchronizing signal is a specified level or within a permissible range and a switch circuit 13d is operated to detect the synchronizing signal. A synchronization width discrimination circuit 14 discriminates whether or not the output signal is a regular synchronizing signal to extract only the regular synchronizing signal. Furthermore, a valid/ invalid discrimination circuit 15 is used to discriminate a valid/invalid input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection circuit for detecting a sync signal of a composite video signal.

[0002]

2. Description of the Related Art Conventionally, this type of synchronization detection circuit has been used for the purpose of extracting a synchronization signal when a composite video signal of a standard value is input.

For example, the detection of the synchronization signal disclosed in Japanese Patent Laid-Open No. 58-177079 is carried out as follows. The peak value of the horizontal sync signal portion of the input composite video signal is compared with the composite signal level and a constant reference level to generate a comparison result signal. By switching the switch using this comparison result signal, the peak value of the horizontal synchronizing signal portion is made to match the level of the potential difference between the reference level and the input signal. In this way, the peak value of the synchronization signal is clamped into a clamp signal, and the synchronization signal is detected using this clamp signal.

FIG. 5 shows an example of a conventional synchronization detection circuit. In this figure, a is a sync tip clamp circuit section and b is a comparator section. The video signal is input to the input terminal 1 of the sync tip clamp circuit section a through the external capacitor C1. The sync tip of the video signal is clamped at the input terminal 1 to a potential lower than the potential of the constant voltage source V1 (the value is V1) by the base-emitter voltage Vbe of the transistor Q1. The clamped video signal is the emitter follower transistor Q.
It is input to the base of the transistor Q3 of the comparator section b through 2. The transistors Q3 and Q4 form a differential pair and form a comparator. Transistor Q5
Q6 forms a pair with the transistors Q2 and Q1, respectively, and serves to eliminate the offset of the voltage input to the comparator including the transistors Q3 and Q4. The potential of the constant voltage source V2 (its value is referred to as V2) is set to be slightly higher than the potential V1 as shown below. FIG. 6a shows the base voltages of transistors Q3 and Q4 on the same figure. In this figure, in the video signal which is the waveform of the base voltage of the transistor Q3, the potential of the sync tip is
The potential (V1-2Vbe) is lowered from the potential V1 by the base-emitter voltage Vbe of the transistors Q1 and Q2.

The base voltage of the transistor Q4 is
The potential (V2-2Vbe) is lowered from the potential V2 by the base-emitter voltage Vbe of the transistors Q5 and Q6. The value of the potential V2 is shown in FIG.
Is set so as to cross the vicinity of the center of the synchronizing signal in the base voltage waveform of the transistor Q3. By doing so, when the base voltage of the transistor Q3 becomes lower than the base voltage of the transistor Q4 which is the threshold value, that is, when the synchronization signal is input, the transistor Q3 is turned off and the voltage drop of the resistor R1 disappears. , The separated synchronizing signal is output to the output terminal 2.
(See Figure 6b)

[0006]

In the conventional sync detection circuit, the clamp level is determined by the potential difference between the level of the input signal and the reference level, so that it operates normally with respect to the input signal near the standard value. However, when the amplitude of the input video signal becomes small, or when the video signal approaches the vertical blanking period, the potential of the sync chip rises, and the base voltage of Q4, which is the threshold value, becomes Q3. There is a problem in that the margin of the base voltage waveform crossing the synchronization signal portion is reduced and the synchronization detection becomes unstable.

For the same reason, even when the amplitude of the sync signal is larger than the standard value, the sync detection is performed without limitation, so that a signal that largely deviates from the standard of the video signal is also changed to normal sync. Process without
An accurate sync signal cannot be detected.

Further, when a composite video signal on which a noise component is superimposed is input, there is a problem that the noise signal may be determined to be a synchronization signal and malfunction may occur.

Further, if the above configuration is performed by digital processing, the problem that the circuit scale becomes large occurs.

Therefore, an object of the present invention is to provide a sync detection circuit capable of outputting a stable digital sync signal without depending on the level of an input composite video signal.

Another object of the present invention is to provide a synchronization detection circuit capable of eliminating a malfunction due to a noise signal and detecting a stable synchronization signal.

Still another object of the present invention is to detect a sync signal of a composite video signal up to a level in consideration of the standard value and margin of the sync signal without being influenced by the amplitude, DC component and noise component of the input signal. It is to provide a synchronization detection circuit.

[0013]

According to the present invention, in a sync detecting circuit for detecting a sync signal of an input composite video signal, reference level generating means for generating a reference level signal representing a reference level, and the reference level generating means. Level converting means for suppressing the peak value of the synchronizing signal to the reference level according to the level signal to generate a clamp synchronizing signal, upper limit level setting means for generating an upper limit allowable level signal representing an upper limit allowable level, and lower limit allowance. A lower limit level setting means for generating a lower limit allowable level signal indicating a level, and a level of the clamp synchronization signal according to the clamp synchronization signal, the upper limit allowable level signal, and the lower limit allowable level signal. A comparison means for comparing with an allowable level and generating a comparison result signal, and an on / off switch according to the comparison result signal. Switch circuit for generating a switch circuit output signal, and a determination means for determining whether the synchronization signal is valid or invalid according to the width of the switch circuit output signal. can get.

[0014]

1 is a block diagram showing a synchronization detecting circuit according to a first embodiment of the present invention. The synchronization detection circuit shown is
Reference level generation circuit 11 and DC level conversion circuit 12
It has a synchronization level comparison circuit 13a, an upper limit level setting circuit 13b, a lower limit level setting circuit 13c, a switch circuit 13d, a synchronization signal width determination circuit 14, and a valid / invalid determination circuit 15.

The reference level generating circuit 11 generates a reference level signal representing a DC reference level which serves as a reference for unifying the DC voltage of the peak value of the synchronizing signal in the video signal. The DC level conversion circuit 12 clamps or suppresses the peak value of the sync signal of the video signal according to the reference level signal, regardless of the DC and AC levels of the video signal as the input signal, and generates the clamp sync signal.

The upper limit level setting circuit 13b is a circuit for setting an allowable range when the synchronization signal compared by the synchronization level comparison circuit 13a is equal to or higher than the standard value, and generates an upper limit allowable level signal representing the upper limit allowable level. Similarly, the lower limit level setting circuit 13c is a circuit for setting an allowable range when the sync signal is equal to or lower than the standard value, and generates a lower limit allowable level signal indicating a lower limit allowable level. The upper limit allowable level is set higher than the level of the synchronizing signal, and the lower limit allowable level is set lower than the level of the synchronizing signal. By using the upper limit and lower limit allowable level signals, it is determined whether the sync signal is at a valid level or not as described below.

The synchronization level comparison circuit 13a compares the levels of the clamp synchronization signal and the upper limit and lower limit allowable level signals, and generates a comparison result signal indicating the comparison result. The switch circuit 13d is turned on / off according to the comparison result signal, and only the signal in the period corresponding to the synchronization signal is detected as the switch circuit output signal.

The synchronization signal width determination circuit 14 determines whether the output signal of the switch circuit is due to the synchronization signal or due to noise, and generates a determination result signal indicating the determination result. In other words, the synchronization signal width determination circuit 14 determines whether the signal detected from the input signal is the synchronization signal.

The valid / invalid judging circuit 15 judges the presence / absence of an input signal and judges whether the input signal is regular or not in accordance with the judgment result signal, and detects the synchronization when there is a regular input signal. It is for generating a signal.

Next, the operation of the synchronization detection circuit shown in FIG. 1 will be described.

The reference level generating circuit 11 always generates a constant DC voltage as a reference level signal without being influenced by other external environment such as power supply voltage fluctuation and temperature fluctuation. It is assumed that the input signal is input to the DC level conversion circuit 12 in this state. At this time, the DC level conversion circuit 12 cuts the DC component of the input signal to leave only the AC signal. When the peak value of the synchronizing signal of the input signal is equal to or lower than the reference level, the peak value of the synchronizing signal of the input signal is adjusted to the reference level by turning on a switch S1 to be described later and passing a current. If the peak value of the sync signal of the input signal is equal to or higher than the reference level, the switch S2, which will be described later, is turned on, and a current is supplied in the GND (± when using the ± power supply) direction to lower the DC level and set the reference value. Adjust the peak value of the sync signal to the level. Therefore, ON / OFF of the switch circuit 13d is controlled by the potential difference between the DC level of the input signal and the reference level, the DC voltage is adjusted by changing the amount of current, and the input signal is synchronized regardless of the amplitude and DC level of the input signal. Keep the signal at a constant value (reference level).

According to the upper limit allowable level signal, the lower limit allowable level signal, and the clamp synchronizing signal, the synchronization level comparing circuit 13a judges whether the level of the clamp synchronizing signal is less than or equal to the level of the upper limit allowable level signal, and the lower limit allowable level. It is determined whether the signal level is equal to or higher than the level, and a comparison result signal is generated. In response to the comparison result signal, the switch circuit 13d connected to the next stage operates as described below.

If this comparison result signal is higher than the set value,
One switch S1 of the switch circuit 13c composed of two switches is turned on, and the other switch S2 is turned on.
Is turned off, a voltage of a certain constant level is output as a switch circuit output signal. When the comparison result signal is lower than the set value, the switch S2 that has been turned off is turned on, and the switch that has been turned on is turned off, contrary to the above operation. As a result, the switch circuit 13d
The switch circuit output signal of is generated at one of two levels depending on the level of the comparison result signal.

In the above, if it is determined that the signals are all sync signals when the level is lower than the upper limit allowable level and higher than the lower limit allowable level, it is possible that signals such as noise are also determined as the synchronizing signals. Therefore, the width of the signal determined to be the synchronization signal in the switch circuit output signal is
The sync signal width determination circuit 14 determines whether the sync signal width standard is satisfied.

The valid / invalid judgment circuit 15 judges whether the input signal is input or not, and judges whether the input signal is within the standard or not, based on the result of whether or not the synchronization signal is a value according to the standard. Outputs a valid / invalid signal.

When a standard-value video signal is input to this synchronization detection circuit, the signal input to the synchronization level comparison circuit 13a is within the range of level values set by the upper limit allowable level and the lower limit allowable level. Therefore, the switch circuit 13d performs an on / off operation at the start and end of the synchronization signal period. As a result, a waveform equivalent to the synchronizing signal appears as the switch circuit output signal. Since the synchronization signal width determination circuit 14 measures the width of the section regarded as the synchronization signal in the switch circuit output signal, the signal width in this case matches the reference value of the synchronization signal period. Therefore, valid /
The invalidity determination circuit 15 determines that the input signal is at the standard level, and outputs a signal having a level indicating validity as the synchronization detection signal.

When no signal is input to this synchronization detection circuit, the output of the DC level conversion circuit 12 becomes equal to the level of the reference level generation circuit 11, so that the synchronization level comparison circuit 13a operates as a reference level and an upper limit level setting circuit 13b. Since the value of the lower limit level setting circuit 13c is compared, the output is always at a constant level. (A different value from when there is a synchronization signal) Therefore, the operation of the switch circuit 13d is the switch S
On / off of 1 and S2 does not occur and remains in one state. As a result, the sync signal width determination circuit 14 cannot measure the width of the sync signal and determines that there is no sync signal. Therefore, the output of the valid / invalid determination circuit 15 which is the final output outputs a signal of a level indicating invalidity.

The operation when the level of the synchronizing signal is below the specified value or above the standard value is as follows. Since the synchronization level comparison circuit 13a compares the values of the upper limit level setting circuit 13b and the lower limit level setting circuit 13c with the input signal clamped to the reference level, the levels between the above upper limit value and the lower limit value are normalized. Is determined as the sync signal level. Therefore, the output of the sync level comparison circuit 13a is the same as the operation in the case of the normal sync signal up to the video signal accompanied by the sync signal up to the allowable range. The other voltage value regions are determined to be other than the synchronization signal. Since this output signal is replaced with two levels by the switch of the switch circuit 13c, the output signal is different from that of the synchronizing signal within the standard value. Therefore, when the synchronization signal width determination circuit 14 determines the synchronization signal period of the output signal waveform of the switch circuit 13c, the synchronization signal period is different from the normal synchronization signal period and is not determined to be a synchronization signal. For this reason, the valid / invalid determination circuit 15 determines that the input signal is not the standard value, and therefore outputs a signal of a level indicating invalidity as the output signal.

The operation when the video signal on which the noise component of the level within the allowable range of the synchronizing signal is superimposed is input is as follows. Sync level comparison circuit 13a
Is the upper limit level setting circuit 13b and the lower limit level setting circuit 1
Since the value of 3c is compared with the input signal clamped to the reference level, the level between the above upper limit value and the lower limit value is determined as the normal synchronization signal level, and for the other voltage value regions, , Other than the synchronization signal. Since this output signal is replaced with two levels by the switch of the switch circuit 13c, the sync signal period and the noise signal period become constant levels as the sync signal.
Therefore, when the synchronization signal period determination circuit 14 determines the synchronization signal period of the output signal waveform of the switch circuit 13c, the regular synchronization signal period is determined to be the synchronization signal period, but the noise period is not determined to be the synchronization signal period. Therefore, a correct sync signal can be detected. In addition, the valid / invalid determination circuit 1 can detect a normal synchronization signal.
In 5, it is determined that the input signal is within the standard value, and therefore the output signal is a signal of a level indicating validity.

FIG. 2 shows the signal waveform of each part of the sync detection circuit of FIG. 1 when a sync signal within the standard value is input.

The reference level generating circuit 11 outputs the waveform of (b) in order to generate a certain DC voltage. At this time, when the input signal shown in (a) is input to the DC level conversion circuit 12, the peak value of the synchronizing signal is clamped to the reference level and the waveform shown in (c) is output. Upper limit value level setting circuit 13b and lower limit value level setting circuit 1
3c outputs a waveform as shown in (d) in order to generate a voltage for comparing the synchronizing signals. Further, since the waveforms (c) and (d) are input to the input of the synchronization level comparison circuit 13a, the waveforms shown in (e) and (f) are obtained by the operation of the switch circuit 13d. Since the synchronizing signal width judging circuit 14 judges whether the signal width of the synchronizing signal portion of the output signal is at the standard value level, the output of the valid / invalid judging circuit 15 is the input signal as shown in (g). Is a waveform indicating that it is effective.

FIG. 3 shows the signal waveform of each part of the sync detection circuit of FIG. 1 when no signal is input to the sync detection circuit.

Since the reference level generating circuit 11 generates a certain DC voltage, the waveform of (b) is output.
At this time, when the input signal shown in (a) is input to the DC level conversion circuit 12, it is clamped to the reference level and the waveform shown in (c) is output. The upper limit value level setting circuit 13b and the lower limit value level setting circuit 13c output a waveform as shown in (d) in order to generate a voltage for comparing the synchronization signals. Further, the synchronization level comparison circuit 13a
Since the waveforms of (c) and (d) are input to the input of,
The waveforms shown in (e) and (f) are obtained by the operation of the switch circuit 13d. The synchronization signal width determination circuit 14 determines whether or not the signal width of the synchronization signal portion of this output signal is at the standard value level. Therefore, the output of the valid / invalid determination circuit 15 is the input signal as shown in (g). Is a waveform indicating invalidity.

The signal waveforms of the respective parts of the sync detection circuit of FIG. 1 when a video signal having a sync signal level of (standard value-allowable range) or less or (standard value + allowable range) or more is input are shown.

The operation from the input of the video signal to the input of the sync level comparison circuit 13a has the same waveform as when the sync signal level is within the allowable range.
That is, the reference level generation circuit 11 generates a certain DC voltage, and thus the waveform (b) is output. At this time, when the input signal shown in (a) is input to the DC level conversion circuit 12, the peak value of the synchronizing signal is clamped to the reference level and the waveform shown in (c) is output. Upper limit level setting circuit 13b and lower limit level setting circuit 13c
Outputs a waveform as shown in (d) to generate a voltage for comparing the synchronizing signals. The waveforms (c) and (d) are input to the input of the synchronization level comparison circuit 13a.

When the sync signal is below the standard value-tolerance range, the sync level comparison circuit determines that the sync signal is not the sync signal, so that the switch circuit 13d is turned on / off.
Output is always constant without switching off (f)
Becomes the waveform of. Since the synchronizing signal width judging circuit 14 judges whether the signal width of the synchronizing signal portion of the output signal is at the standard value level, the output of the valid / invalid judging circuit 15 is the invalid input signal as shown in (g). The waveform becomes.

Further, when the sync signal is equal to or more than the (standard value + allowable range), the sync level comparison circuit determines that the sync signal is not the same as in the above operation, and therefore the switch circuit 13d is switched on / off. There is no operation, and the waveform of (f) is a constant output. The synchronization signal width determination circuit 14 determines whether or not the signal width of the synchronization signal portion of the output signal is at the standard value level. Therefore, the output of the valid / invalid determination circuit 15 is the input signal as shown in (g). Is a waveform indicating invalidity.

FIG. 3 shows a waveform of the operation of the block of FIG. 1 when a video signal on which a noise component having a level within the allowable range of the sync signal is superimposed is input to the sync detection circuit.

The operation from the input of the video signal to the input of the sync level comparison circuit 13a has the same waveform as when the sync signal level is within the allowable range.
That is, the reference level generation circuit 11 generates a certain DC voltage, and thus the waveform (b) is output. At this time, when the input signal shown in (a) is input to the DC level conversion circuit 12, the peak value of the synchronizing signal is clamped to the reference level and the waveform shown in (c) is output. Upper limit level setting circuit 13b and lower limit level setting circuit 13c
Outputs a waveform as shown in (d) to generate a voltage for comparing the synchronizing signals. The waveforms (c) and (d) are input to the input of the synchronization level comparison circuit 13a. Here, since a signal within the standard value ± tolerance range of the synchronization signal is determined to be a synchronization signal by the synchronization level comparison circuit, the switch circuit 13d performs an on / off switching operation (e), (f). ) Is the waveform shown in. The synchronization signal width determination circuit 14 determines whether the signal width of the synchronization signal portion of this output signal is at the standard value level, so the output waveform is (g), and the output of the valid / invalid determination circuit 16 is (h). ), The input signal has a waveform indicating invalidity.

Since the waveform finally output differs depending on the sync signal level and the sync signal width of the input signal as described above, it is possible to determine whether the input signal is valid or invalid.

In this way, it is judged whether the input signal is valid or invalid, and a T having a digital level, for example, "H" level of 2.4V to 5V and "L" level of 0 to 0.8V.
A TL level synchronization detection signal is obtained.

[0042]

As described above, the sync detection circuit according to the present invention does not depend on the amplitude and DC level of the input signal, and therefore can perform stable sync detection. Also,
Since the valid sync signal level is set by the upper limit level setting circuit and the lower limit level setting circuit, it is possible to realize that the valid range of synchronization (allowable value with respect to the normal value) is provided. Further, since the width of the output sync signal is counted, even if a noise signal is mixed, it is not judged as a sync signal, and thus a stable sync signal can be detected. In addition to the above, because the circuit configuration is easy, downsizing of the circuit,
It is possible to improve reliability and economy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization detection circuit according to a first embodiment of the invention.

FIG. 2 is a signal waveform showing an operation of each processing unit in the synchronization detection circuit of FIG. 1 when a video signal having a synchronization signal within (standard value ± allowable range) is input.

FIG. 3 is a signal waveform showing an operation of each processing unit in the synchronization detection circuit of FIG. 1 when a video signal is not input.

4 is a signal waveform showing the operation of each processing unit in the synchronization detection circuit of FIG. 1 when a video signal that is not a standard value (when the synchronization signal level is lower than the standard value) is input.

FIG. 5 is a circuit diagram showing a conventional synchronization detection circuit.

FIG. 6 is a signal waveform showing an operation in a conventional synchronization detection circuit.

[Explanation of symbols]

 11 Reference level generation circuit 12 DC level conversion circuit 13a Synchronous level comparison circuit 13b Upper limit level setting circuit 13c Lower limit level setting circuit 13d Switch circuit 14 Synchronous signal width determination circuit 15 Valid / invalid determination circuit

Claims (3)

[Claims] 1. A synchronization detection circuit for detecting a synchronization signal of an input composite video signal, a reference level generating means for generating a reference level signal representing a reference level, and a peak of the synchronization signal according to the reference level signal. Level conversion means for suppressing a value to the reference level to generate a clamp synchronization signal, upper limit level setting means for generating an upper limit allowable level signal indicating an upper limit allowable level, and lower limit allowable level signal indicating a lower limit allowable level A lower limit level setting means, the clamp synchronization signal, the upper limit allowable level signal, and the lower limit allowable level signal, the level of the clamp synchronization signal is compared with the upper limit allowable level and the lower limit allowable level, and a comparison result signal is obtained. Comparing means for generating and a switch circuit output signal which is turned on / off according to the comparison result signal A synchronization detection circuit comprising: switch means; and determination means for determining whether the synchronization signal is valid or invalid according to the width of the switch circuit output signal. 2. The synchronization detection circuit according to claim 1, wherein
The upper limit level setting means is a standard value level (28
6 mV + 10 dB) is set to an upper limit allowable level for allowing a signal level, and the lower limit level setting means sets and prints a lower limit allowable level for allowing a signal level up to (standard value level −10 dB). A synchronization detection circuit characterized by: 3. The synchronization detection circuit according to claim 1, wherein:
The determination means is a standard value of the synchronization signal (4.7).
A sync detecting circuit having a sync signal width judging means for judging whether or not it is within the range of (us ± 0.1 us).