JPH08233911A - Bit error measuring pattern generator, bit error measuring instrument and bit error measuring apparatus using the same - Google Patents

Abstract

PURPOSE: To measure corresponding bit error by outputting the generating zone of a plurality of channels of pattern generators while sequentially switching them, and controlling the operation of the other generator while outputting out generator, thereby generating the pattern of a desired bit row and a long period. CONSTITUTION: A pattern generating controller 10 has a PGC counter 12, a coincidence comparator 14, an SRFF 16, and a period counter 18, and supplies switching signals 16sel from the FF16 to a PRBS generator 62prbs, a WORD generator 62word and a multiplexer 62m. Thus, the pattern generations of the generators 62prbs, 62word are alternately switched and output from the multiplexer 62m. Thus, the desired pattern row and the long period pattern are multiplexed, and the bit error corresponding thereto can be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error measuring device for switching a specific pattern and a random pattern in real time to generate a test pattern and analyzing an error error of an output signal from a device under test. .

[0002]

2. Description of the Related Art In a bit error measuring device, a test pattern is given to a DUT such as a device under test or a device at a test rate up to a bit rate of several tens of GHz, and various test conditions are changed so that the error rate = error. Measure the error rate and set D
The performance of the UT is evaluated. In the conventional bit error measuring device, the test pattern given to the DUT is P
There are two generation modes, that is, pseudo random pattern generation of RBS and WORD pattern generation that repeatedly outputs memory contents. The test pattern is supplied to the DUT, the output signal from the DUT is received, the number of bit errors is counted by comparing with the expected value, and the error rate is calculated and displayed.

FIG. 5 shows an example of a connection configuration of a test by the bit error measuring device. The test pattern signal 71pat and the clock 73 from the pattern generator 71 are supplied to the DUT 74, and the signal under measurement and the clock output from the DUT 74 are supplied to the bit error measuring device 75 to measure the bit error.

FIG. 6 shows an example of the internal structure of the test pattern generator 71 side. The test pattern given to the DUT 74 is a PRB that generates a pseudo random pattern of PRBS.
There are two generators, an S generator 71prbs and a WORD generator 71word that outputs and generates a WORD pattern of memory contents. After either of these two test patterns is fixedly switched by the switch (MUX) 71m, the test pattern signal 71pat to which the desired amplitude and offset potential are added is supplied to the DUT 74 by the buffer amplifier 71buf.
Here, the memory content data, the generation conditions, etc. are stored in the external CPU.
It is preset from the (computer) to a desired test state. In response to this, the DUT 74 shown in FIG.
Output to 5 In response to this, the bit error measuring device 75 counts the number of mismatched bits by comparing with the internal expected value generation pattern, calculates the bit error rate, and outputs it for display.

FIG. 7 shows an internal configuration diagram of the bit error measuring device 75 side. The received signal under test 61 from the DUT 74 is compared with the reference pattern generator 62 by the collator 65, and the number of mismatch bits is counted by the error counter 70. By the way, since the positional relationship between the position of the pattern string of the received signal under test 61 from the DUT 74 and the bit string of the reference pattern generator 62 is indefinite, a pattern synchronization unit 66 for synchronizing the positional relationship of both bit strings is provided. are doing. The synchronization detection counter 66a detects whether the error rate is equal to or lower than a predetermined value, counts the number of mismatch bits 65err every fixed clock period (for example, 16384 clock periods), and gives a comparison test pulse 66tst to give a comparator. 66c is compared, and at the same time, the synchronization detection counter 66a is cleared to the initial value and repeatedly detected. If this comparison is the desired count value, that is, the threshold register 66b or more,
Since the bit string positional relationship between the two is still inconsistent,
A clock mask signal 67 for stopping the reference pattern generator 62 side for one clock time is supplied to shift the bit string to be compared. This operation is repeated for every fixed clock period by sequentially shifting by one clock time until the pattern rows match, and pattern synchronization detection is performed. Eventually, if a match is detected, it is considered that the two are synchronized, and thereafter the detection operation is stopped and the original bit error measurement state is entered.

Here, in the internal configuration diagram of the reference pattern generator 62, a PRBS generator 62prbs and a WORD generator 62 are shown.
The two word generators are the same pattern generators as the test pattern generator 71 side, except for the clock mask function which shifts by one clock time. Then, the test pattern generator 7
It is switched to the same side as the generator side used on the first side and supplied to the collator 65 as a reference pattern 62pat. The above various setting data, synchronization conditions, measurement conditions, etc.
Is preset to the desired test state.

[0007]

As described above, the conventional bit error measuring device is a bit error measuring device for selecting and generating either a WORD pattern generator or a PRBS pattern generator for testing. In the PRBS pattern generation, a long cycle pattern can be generated, but there is a drawback that a desired bit string cannot be output. On the other hand, in the WORD pattern generation, a desired bit string can be generated, but since it has a finite memory capacity, it has a drawback that a long-period pattern cannot be generated. For this reason, a predetermined pattern portion, which is a pseudo test pattern generation similar to the communication form of a transmission frame (for example, STM, SDH, ATM) of an actual communication line, and a pseudo pattern portion of a long period coexist and cannot be tested. However, in such a test form, the test evaluation cannot be performed, which is a difficulty in use.

[0008] Therefore, an object of the present invention is to realize a measuring apparatus capable of multiplexing a desired bit string generation and a long-period pattern generation and measuring a bit error corresponding thereto.

[0009]

FIG. 1 shows a first solution according to the present invention. In order to solve the above-mentioned problems, in the configuration of the present invention, an M-channel pattern generator is provided, the generation intervals of each pattern generator channel are sequentially switched in real time and output, and the 1-channel pattern generator is selected. A pattern generation control unit 10 for controlling the pattern generation operation of another channel during output is provided as a constituent means. As a result, a test pattern generator, which is used for bit error measurement, has a pattern generator of the number M of pattern selections, and selects and outputs the pattern generator is realized.

A pattern generation control unit 10 for selecting and outputting a pattern generator in the case of M = 2 channels in real time outputs P for generating a repeating frame period value 12 pset.
The GC counter 12 is provided, and the binary state means for receiving the frame period data 12dat from the PGC counter 12 and outputting the switching signal 16sel for dividing the multiplexing section of the 2-channel pattern generator by the coincidence comparator 14 means is provided. A pattern generator for bit error measurement, comprising a cycle counter 18 for giving the number of times of a frame cycle which is repeatedly generated, and comprising the above.

FIG. 2 shows a second solution according to the present invention. In order to solve the above-mentioned problem, in the configuration of the present invention, an M channel pattern generator having a pattern generation mode corresponding to the reception test pattern signal 61 of the pattern selection number M is provided, and each pattern corresponding to the reception test pattern signal 61 is provided. Of the pattern generator for each pattern generator, the pattern generator of M channel is sequentially switched by this generation interval signal and is supplied to the collator 65, while the pattern generator of 1 channel is selected and output. , A pattern generation control unit 10 for controlling the pattern generation operation of the pattern generator of another channel is provided, and in response to a switching signal from the pattern generation control unit 10, the output of the pattern generator of the M channel is sequentially output to perform reference comparison. A switching unit for supplying the pattern signal to the collator 65 is provided, and the switching signal from the pattern generation control unit 10 is provided. Receiving and detects the synchronization individually pattern, a configuration means the pattern synchronization detection provided pattern synchronizer of M channels to be synchronized by supplying a clock mask signal to the pattern generator corresponding to the time of detection asynchronous. As a result, a bit error measuring device is realized which is used for bit error measurement, generates a pattern of pattern selection number M channels and supplies it to the device under test, and receives an output signal from this to measure a bit error.

A bit error measuring pattern generator;
The bit error measuring device realizes a bit error measuring device for generating a pattern of the number M of pattern selections and supplying it to the object to be tested, and receiving an output signal from this to measure a bit error.

As a concrete means, the pattern generator is provided with at least one channel of the WORD pattern generator,
Alternatively, at least one channel of the PRBS pattern generator is provided. Further, as a generation mode of this pattern generator, there are a WORD generator 71 word which outputs and generates a WORD pattern of memory contents, and a PRBS generator 71 prbs which generates a pseudo random pattern of PRBS.

[0014]

Function: Pattern generation controller 1 on the side of the pattern generator 20
When M = 2, 0 alternately outputs two patterns of pattern generators in real time. PRB at this time
Each of the S pattern generator and the WORD pattern generator has an action of selecting and outputting a pattern while operating, or an action of stopping one pattern generator while outputting the other pattern generator. . The pattern generation control unit 10 on the side of the bit error measuring device 30 also has a function of generating a test pattern to be given to the collator 65. The reference pattern generator 34 has a role of generating the same comparison pattern as the pattern generation on the test pattern generator 20 side. In addition, the WORD pattern synchronization unit 31 and P
Upon receiving the individual clock mask signals from the RBS pattern synchronization unit 32, a pattern synchronized with the bit string of the received signal 61 can be generated at the time of synchronization.

The WORD pattern synchronization section 31 receives the switching signal 16sel from the pattern generation control section 10,
Synchronous detection of a section corresponding to the WORD pattern generation section Toh is performed, and when the error rate is equal to or higher than a desired error rate, a clock mask signal 31 inh pulse is supplied to the WORD generator 62 word to have a function of synchronizing the WORD pattern side. Similarly, the PRBS pattern synchronization unit 32 receives the switching signal 16sel from the pattern generation control unit 10 to detect synchronization of a section corresponding to the PRBS pattern generation section Tpayload, and when the error rate is equal to or higher than a desired error rate, the clock mask signal is generated. 32 inh pulse to PRBS generator 62 prbs
To supply the PRBS pattern side with the pattern synchronization. That is, both pattern synchronization units are
The pattern and the PRBS pattern each have a function of independently performing pattern synchronization.

[0016]

The embodiment of the present invention is a PRB that generates a long period.
S pattern generator and WO capable of generating a desired bit string
There is an example in which two pattern generators of the RD pattern generator are switched in real time and generated, and the pattern error corresponding to this generated pattern is taken to measure an error error. Regarding this, SDH (Synchronous Digital Hier)
archy) It explains using a frame configuration example.

As shown in FIG. 3, the SDH frame structure has a structure of 9 rows and 270 byte columns as one frame. The 9 byte column before the 270 byte column is overhead (OH) and the 261 byte after is 261. The byte string is the payload (P
AYLOAD). As a test pattern for this, a case where it is necessary to give a known predetermined value pattern to the overhead position and a random pattern to the payload position will be described. As the test pattern generator, this frame pattern is repeatedly generated in a large number of N frame periods. That is, every N frame periods, the overhead side generates the same bit stream, while the payload side generates a different bit stream.

In order to generate the above-mentioned test pattern, the structure of the test pattern generator 20 side of the present invention is a structure in which the pattern generation controller 10 is added to the conventional constituent elements as shown in FIG. PRBS generator 62prbs, WORD generator 62word, switcher 62m, and buffer amplifier 62buf
The constituent elements of are the same as the conventional ones. However, the PRBS generator 62prbs and the WORD generator 62word each have a pattern generation temporary stop function.

The internal structure of the pattern generation controller 10 is P
GC counter 12, coincidence comparator 14, SRFF (S
R flip-flop) 16 and a cycle counter 18. The PGC counter 12 has a borrow signal 12bo.
A counter that presets a repeating frame period value of 12 pset for each r and counts down,
In response to 2, the desired frame period data 12dat is generated. The frame cycle value 12pset can be arbitrarily set by the external CPU so that it can correspond to an arbitrary frame cycle.

SRFF (SR flip-flop) 16
Generates a signal for switching between two pattern generators within one frame section, as shown by the switching signal 16sel in FIG. Upon receiving the frame period data 12dat from the PGC counter 12 shown in FIG. 1, the coincidence comparator 14 detects the data value of the overhead OH in the 9-byte column time, and switches the SRFF 16 to the reset state. In addition, a borrow signal 12bo from the PGC counter 12
Upon receiving r, the SRFF 16 is switched to the set state.
The output switching signal 16sel of this flip-flop is set to M
After being supplied to the UX 62m to switch the input pattern in real time, it is supplied to the buffer amplifier 71buf. Further, the output switching signal 16sel is the PRBS generator 62prbs.
And a word generator 62 word address counter 62ct
Suspends the pause (pause) of r and alternately suspends the pattern generation. As a result, the pattern generator side selected by the MUX 62m operates, and the pattern generator side on the non-output side enters a state of waiting for a temporary stop. In this way, by alternately switching and repeating this in real time, a test pattern in which both patterns are multiplexed is output.

The cycle counter 18 has an O cycle at an N frame cycle.
This is for repeating the H-side pattern, receives the borrow signal 12bor from the PGC counter 12, performs counter down, and supplies this borrow signal 18ld to the load input terminal of the address counter 62ctr to supply the address counter 6
2ctr is set to the initial value. The self sets the initial value = 9 × N with this borrow signal 18ld and repeats. Here, the setting of the initial value and the setting value given to the other input terminal of the coincidence comparator 14 can be arbitrarily set by the external CPU, and can be made an arbitrary N frame cycle.

Next, the bit error measuring device 30 side of the received signal 61 whose test pattern from the test pattern generator 20 has passed through the DUT will be described. As shown in FIG. 2, this configuration has a WORD pattern synchronization unit 31 as two independent pattern synchronization units with respect to the conventional components.
And a PRBS pattern synchronization unit 32, which is a multiplexed reference pattern generator 34 similar to that on the side of the pattern generator 20.

The pattern generation control unit 10 of the reference pattern generator 34 is similar to the case of the test pattern generator 20 side, and generates a multiplexed pattern signal 34pat in which two test patterns are switched in real time, and this is generated. It is supplied to one input end of the collator 65. This reference pattern generator 34 is different from the test pattern generator 20 side in that in order to synchronize with the received signal 61, the WORD pattern synchronization unit 31 and the PRBS pattern synchronization unit 32 individually generate patterns for one clock time. Has a 1-clock stop function (pause function) that stops independently, and this pause function itself is similar to the function of a conventional reference pattern generator. The difference is that it is used as the input end.

In the pattern synchronization detection, both the synchronization detections of the two pattern synchronization sections are simultaneously performed in parallel and independently, and when it is detected that both are below a predetermined bit error rate, the synchronization detection state is changed. The original bit error measurement state is entered.

The synchronization detection of the first system is the synchronization of the WORD pattern synchronization section 31. The WORD pattern is repeated every N frames. An operation different from the conventional one in the operation of detecting the synchronization position is that only the WORD detection area section Toh is synchronized. That is, only when the switching signal 16sel from the pattern generation control unit 10 is in the high level section, the operation of the internal synchronization detection counter 66a is enabled. Then, as in the conventional case, when the error rate is higher than the desired error rate, the clock mask signal 31 inh pulse is sent to the WORD generator 62w.
It is supplied to ord and the pattern generation is delayed by one clock time. Eventually, if the error rate becomes equal to or lower than the desired error rate, the WORD pattern side considers that the synchronization has been detected, stops the synchronization detection operation, outputs the detection signal 31sync, and shifts to the WORD synchronization completion state.

The synchronization detection of the second system is the synchronization of the PRBS pattern synchronization unit 32. Similarly to the above description, the synchronization detection operation is performed only when the switching signal 16sel is in the low level section, and when the error rate is higher than the desired error rate, the clock mask signal 32inh pulse is supplied to the PRBS generator 62prbs to generate the pattern. Shift clock time. Eventually, if the error rate falls below the desired error rate, the PRBS pattern side considers that synchronization has been detected, stops the synchronization detection operation, and outputs the detection signal 3
2sync is output to shift to the PRBS synchronization completed state. When both of the above are in the synchronization completion state, the original bit error measurement state is entered.

By carrying out as described above, it is possible to realize a bit error measuring apparatus applicable to a test mode of a desired communication frame structure by multiplexing a desired pattern sequence and a long-period pattern. It goes without saying that a test form in which either the WORD pattern or the PRBS pattern, which is the same test form as the conventional one, is selectively output and tested can be easily implemented.

In the above description of the embodiment, the case where the test pattern generator is a 1-bit WORD pattern or PRBS pattern generator has been explained, but a pattern generator having an M-bit parallel configuration is used, and this is used as an Mto1 multiplexer ( Multiplexer) may be provided to convert into parallel-serial converted 1-bit bit stream and output.

In the description of the above embodiment, the collator 65 is used.
I explained in the case of comparing with 1 bit in
If desired, a 1 to M-bit demultiplexer (De
-Multiplexer) is installed for serial / parallel conversion.
The collator 65 and the following may be configured and implemented in bit units.

Further, in the description of the above embodiment, the combination of the test pattern generators is the WORD pattern and the PRBS.
Although the example of the combination of the patterns has been described, since it corresponds to the test form by the multiplexing of two predetermined patterns or the multiplexing of two random patterns, if desired, W
The ORD pattern may be provided in two systems, or the PRBS pattern may be provided in two systems, and the same operation can be performed.

Further, in the above description of the embodiment, the test pattern generator is provided in two systems, and the test pattern generator is multiplexed, but if desired, the two systems are P systems (P is 2 or more). Value) may be provided and a peripheral circuit such as a pattern synchronization unit corresponding thereto may be configured to be realized, and it can be easily realized by implementing the same realizing means as the above embodiment.

[0032]

Since the present invention is configured as described above, it has the following effects. The pattern generation control unit 10 on the side of the pattern generator 20 alternately switches the pattern generators of the two systems in real time and outputs the pattern generators, and waits for the pattern generator on the side not to be output to pause to generate the multiplexed test pattern. Can occur. Similarly, the pattern generation control unit 10 on the bit error measuring device 30 side can similarly generate the multiplexed test pattern. The reference pattern generator 34 generates a comparison pattern, which is an expected value, by the same multiplexing as the multiplexed pattern generation on the test pattern generator 20 side, and outputs the individual patterns from the WORD pattern synchronization unit 31 and the PRBS pattern synchronization unit 32. By receiving the clock mask signal, a pattern in which the received signal 61 and the bit string are synchronized can be generated.

The WORD pattern synchronization section 31 receives the switching signal 16sel from the pattern generation control section 10,
It is possible to perform pattern synchronization on the WORD pattern side by performing synchronization detection of a section corresponding to the WORD pattern generation section Toh and supplying a clock mask signal 31 inh pulse to the WORD generator 62 word when the error rate is higher than a desired error rate. Similarly, the PRBS pattern synchronization unit 32 receives the switching signal 16sel from the pattern generation control unit 10 to detect synchronization of a section corresponding to the PRBS pattern generation section Tpayload, and when the error rate is equal to or higher than a desired error rate, the clock mask signal is generated. 32 inh pulse to PRBS generator 62 prbs
, The PRBS pattern side can be pattern-synchronized. With both pattern synchronization units, W
Corresponding to each ORD pattern and PRBS pattern,
Pattern synchronization can be taken independently of each other.

As a result, it is possible to realize a measuring device which has both a desired bit string generation and a long-period pattern generation and is capable of bit error measurement corresponding thereto.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a test pattern generator of the present invention.

FIG. 2 is a block diagram of a bit error measuring device for received signals according to the present invention.

FIG. 3 is an example of a communication frame SDH (STM-1)
It is the frame structure of.

FIG. 4 is a timing diagram of a switching signal for multiplexing one frame period.

FIG. 5 is an example of a connection configuration for bit error measurement.

FIG. 6 is a configuration diagram of a conventional test pattern generator.

FIG. 7 is a block diagram of a conventional bit error measuring device for received signals.

[Explanation of symbols]

 10 pattern generation control unit 12pset frame period value 12 PGC counter 12dat frame period data 12bor, 18ld borrow signal 14 coincidence comparator 16sel switching signal 16 SRFF (SR flip-flop) 18 period counter 20, 71 pattern generator 30, 75-bit error measurement Device 31 WORD pattern synchronization unit 31sync, 32sync Sync detection signal 32 PRBS pattern synchronization unit 34, 62 Reference pattern generator 34pat Multiplex pattern signal 61 Received signal 62prbs, 71prbs PRBS generator 62word, 71word WORD generator 62pat Reference pattern 62m, 71m Switcher (MUX) 62ctr Address counter 65 Collator 66 Pattern synchronization unit 66a Synchronization detection counter 66tst Comparison test pulse 66c Comparator 67 Clock mask signal 70d Over the counter 71pat test pattern signal 71buf buffer amplifier 72 and 73 clock 74 DUT

Claims (7)

[Claims] 1. A pattern generator used for bit error measurement, having a pattern selection number (M) channels,
In a test pattern generator that selects and outputs this, a pattern generator for M channels is provided, and the generation intervals of each pattern generator channel are sequentially switched in real time and output, and a 1-channel pattern generator is selected and output. Pattern generation control unit (10) for controlling the pattern generation operation of another channel while
And a pattern generator for bit error measurement characterized by comprising the above. 2. A pattern generation control section (10) for selecting and outputting a pattern generator of M = 2 channels, a PGC for generating a repetitive frame period value (12 pset).
A counter (12) is provided, and the frame period data (1
2dat), a coincidence comparator (14) means is provided with a binary state means for outputting a switching signal (16sel) for dividing the selection section of the pattern generator of two channels, and a cycle counter for giving the number of times of the frame cycle repeatedly generated The bit error measuring pattern generator according to claim 1, further comprising (18). 3. A test apparatus for use in bit error measurement, which generates a pattern of pattern selection number (M) channels and supplies it to a device under test, and receives an output signal from this to measure a bit error. An M channel pattern generator having a pattern generation mode corresponding to several M reception test pattern signals (61) is provided to generate a generation section signal for each pattern generator corresponding to the reception test pattern signals (61). The pattern generator of the M channel is sequentially switched by this generation section signal and is supplied to the collator (65). While the pattern generator of the 1 channel is being selected and output, the pattern generator of the other channel is selected. Is provided with a pattern generation control unit (10) for controlling the pattern generation operation of, and receives a switching signal from the pattern generation control unit (10). A switching means for selecting the output of the pattern generator of the M channel and supplying the output reference comparison pattern signal to the collator (65), and receiving a switching signal from the pattern generation control section (10), An M-channel pattern synchronization section for individually detecting the pattern synchronization and supplying a clock mask signal to the corresponding pattern generator when the pattern synchronization detection detects the synchronization is provided. Bit error measuring instrument characterized by. 4. A test apparatus which is used for bit error measurement, generates a pattern of pattern selection number (M) channels, supplies the pattern to a device under test, and receives an output signal from the test device to measure a bit error. A bit error measuring device comprising the pattern generating means according to claim 1, the bit error measuring means according to claim 3, and the above. 5. The M-channel pattern generator according to claim 1, wherein at least one WORD pattern generator is provided in one channel, or at least one PRBS pattern generator is provided.
Bit error measuring device provided with a channel. 6. The pattern generator according to claim 5, wherein the WORD pattern is generated by outputting a WORD pattern of memory contents.
A pattern generator for bit error measurement, which is a generator (62 words). 7. The pattern generator according to claim 5, wherein the pattern generator is PR.
A bit error measurement pattern generator which is a PRBS generator (62 prbs) for generating a pseudo random pattern of a BS (Pseudo Random Binary Sequence).