JPH0823336A - Test equipment for atm system - Google Patents

Abstract

PURPOSE:To accurately discriminate missing of a cell and to reduce the hardware quantity. CONSTITUTION:A transmission section 100 has a sequential number generating section 101 generating a sequential number provided in a cell and an error check code generating section 102 generating an error check number to discriminate the acceptance of the sequential number. A reception section 200 has a sequential number error detection section 201 discriminating the acceptance of the sequential number based on the error check code. The transmission section 100 is provided with a pay load section error check code generating section 103 generating an error check code for checking an error of the pay load part, and the reception section 200 is provided with a pay load section error discrimination section 205 to discriminate it. The transmission section 100 is provided with a time stamp generating section 104 to add a cell transmission time and the reception section 200 is provided with a cell delay time calculation section 206 to obtain a cell delay time based on the transmission time and the reception time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
AT using Transfer Mode (Asynchronous Transfer Mode) technology
The present invention relates to an ATM system test device for conducting a communication test of an M system.

[0002]

2. Description of the Related Art Transmission / reception data is divided into short blocks,
There is an ATM system in which data is transmitted by a cell having a header indicating the destination etc. at the head thereof. In such an ATM system, since the VP (virtual path) is tested, for example, Japanese Patent Laid-Open No. 5-24419 is used.
As described in Publication No. 6, while online, P
A cell with a sequential number assigned sequentially is transmitted together with random data called N pattern. The receiving side is provided with the same PN pattern generating circuit as the transmitting side, the bit error is detected by the comparison, and the cell omission is detected by the sequential number detection.

[0003]

However, in the conventional ATM system test apparatus as described above, even when a plurality of cell omissions occur continuously, it can be recognized as only one error, and the sequential number is not detected. Even if a bit error occurs in the cell, the cell error is recognized as a missing cell instead of the bit error. Further, even if an error is detected, there is a problem that the error rate cannot be obtained as a system. From such a point, it is possible to accurately recognize a cell error,
Moreover, it has been desired to realize an ATM system test apparatus that can accurately determine the error rate of the system.

A PN pattern generating circuit is provided on the transmitting side and the receiving side. Since the PN pattern generating circuit has a large amount of hardware, the amount of hardware in the entire system increases, and the amount of hardware is reduced. Was hindering

Although it can be used as a continuity test of an ATM system, it cannot satisfy the test requirement of a cell depending on the size of the traffic of the cell flow. Therefore, the traffic of the cell flow can be arbitrarily changed and tested. There has been a demand for a test device for an ATM system capable of performing the above.

When the cell flow is an ATM cell, in addition to cell data for detecting a cell, a cell synchronization signal (cell SY
Although there is an NC signal), it is not possible to perform a test as to whether or not the system operates normally when some noise is actually present in the cell synchronization signal, and such an ATM system can also be tested. Was required.

[0007] In testing an ATM system, it is necessary to observe cell delays and fluctuations, but conventional systems cannot meet such requirements, and therefore it is not possible to carry out such a test. It has been desired to realize a test apparatus for an ATM system that can be used.

[0008]

In order to solve the above-mentioned problems, a test apparatus for an ATM system according to the present invention has a sequential number generation unit for generating a sequential number to be given to a cell to be transmitted, and a sequential number generation unit for this sequential number. An error detection code generation unit that generates an error detection code for correctness determination is provided. Further, the receiving unit, from the received cell, by the error detection code included in the cell, a sequential number error detection unit that determines whether or not the sequential number is correct, and for each reception of the cell, count the number of received cells If the receive cell counter and the sequential number error detection unit determine that the sequential number is correct, the sequential number of the cell is compared with the number of received cells of the receive cell counter, and these values do not match. In this case, a sequential number judging unit for judging a cell missing error is provided. Further, the receiving section is provided with an error rate calculating section for obtaining an error rate from the relationship between various errors and the total number of received cells of the receiving cell counter.

Further, in order to solve the above-mentioned problems, the test apparatus for the ATM system of the present invention has a payload for generating an error detection code for detecting a bit error with respect to the payload part of a cell to be transmitted, in the payload. A partial error detection code generation unit is provided, and a receiver unit is provided with a payload unit error determination unit that detects a bit error error with respect to the payload unit of the cell from the error detection code in the received cell.

Further, in order to solve the above-mentioned problems, the test apparatus of the ATM system of the present invention transmits a traffic pattern control unit for controlling the ratio of the test cell and the empty cell in the cell flow to be transmitted. It is provided in the section.

In order to solve the above-mentioned problems, the ATM system test apparatus according to the present invention uses, as a cell synchronization signal to be transmitted to the transmission section to the reception section, a test abnormality different from a normal cell synchronization signal. A test cell synchronization signal generator for transmitting a synchronization signal is provided. Further, the receiving unit is provided with a cell synchronization signal protection unit that generates a normal cell synchronization signal from the abnormal test synchronization signal when the abnormal test synchronization signal is received.

Further, in order to solve the above-mentioned problems, the test apparatus for the ATM system of the present invention is provided with a time stamp generating section for giving transmission time information to each cell to be transmitted. In addition, the receiving unit calculates the delay time for each cell from the transmission time information of each cell received and the reception time actually received, and from the delay times for a plurality of cells, the maximum delay time and the minimum delay time are calculated. A cell delay time calculating unit for calculating is provided.

[0013]

In the ATM system test apparatus of the present invention,
The sequential number generation unit generates a sequential number, and the error detection code generation unit generates an error detection code for determining whether the sequential number is right or wrong. The receiving unit first determines whether or not the sequential number is correct from the received cells. Next, for those whose sequential numbers are determined to be correct, the sequential numbers are compared with the sequential numbers on the receiving side to determine whether cell omission has occurred. Also, the error rate calculation unit
The error rate is calculated from the relationship between the number of received cells in the received cell counter and various errors.

Further, in the ATM system test apparatus of the present invention, the payload section error detection code generation section generates the error detection code. The payload section error determination section on the receiving side checks from the error detection code whether or not there is a bit error in the payload section of the cell.

Further, in the ATM system test apparatus of the present invention, the traffic pattern control unit controls the ratio of the test cell and the empty cell, and gives an instruction to transmit the cell at this control ratio.

In the ATM system test apparatus of the present invention, the test cell sync signal generator sends out various test abnormal sync signals different from the normal cell sync signal. When receiving the abnormal test synchronization signal, the cell synchronization signal protection unit of the reception unit generates a normal cell synchronization signal from the abnormal test synchronization signal.

Further, in the test apparatus for the ATM system of the present invention, the time stamp generation section gives the transmission time information to each cell. The cell delay time calculation unit of the reception unit calculates the delay time for each cell from the received transmission time information of each cell and the actually received reception time. Further, the maximum delay time and the minimum delay time of the cell are calculated from the delay times of the plurality of cells.

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an ATM system test apparatus of the present invention. The device shown in FIG.
0, a receiving unit 200 and an ATM switch 300.

The transmission unit 100 includes a sequential number generation unit 101, an error detection code generation unit 102, a payload unit error detection code generation unit 103, and a time stamp generation unit 10.
4, a test cell synchronization signal generator 105 and a traffic pattern controller 106. In addition, the receiving unit 200
Includes a sequential number error detection unit 201, a reception cell counter 202, a sequential number determination unit 203, an error rate calculation unit 204, a payload unit error determination unit 205, a cell delay time calculation unit 206, and a cell synchronization signal protection unit 207. .

The sequential number generation unit 101 in the transmission unit 100 has a function of generating a sequential number for giving a sequential number to each cell to be transmitted. The error detection code generation unit 102 generates an error detection code for determining whether the sequential number generated by the sequential number generation unit 101 is correct. Further, the payload section error detection code generation section 103 has a function of generating an error detection code for detecting a bit error in the payload section of the cell to be transmitted. Furthermore, the time stamp generation unit 104 adds transmission time information to each cell to be transmitted.

The test cell sync signal generator 105 is for generating various test abnormal sync signals different from the normal cell sync signal, and sending them out. In addition, the traffic pattern control unit 106, during the cell flow to be transmitted,
It has a function to control the ratio of test cells and empty cells.

The sequential number error detecting section 201 in the receiving section 200 has a function of detecting whether or not the sequential number is correct from the received cell. The reception cell counter 202 has a function of detecting the number of received test cells each time a cell is received. When the sequential number error detection unit 201 determines that the sequential number is correct, the sequential number determination unit 203 compares the sequential number and an expected value that is sequentially obtained from the number of reception cells detected by the reception cell counter 202. Collation is performed, and if these values do not match, it is determined as a cell missing error.

Further, the error rate calculation unit 204 calculates the total number of received cells received by the received cell counter 202)
The error rate is calculated from the bit error of the sequential number detected by the sequential number error detection unit 201, the cell missing error detected by the sequential number determination unit 203, and the bit error of the payload portion detected by the payload portion error determination unit 205 described later. It is a thing.

The payload section error determination section 205 detects a bit error in the payload section of the cell from the error detection code in the received cell. Further, the cell delay time calculation unit 206 calculates the delay time of the cell from the received transmission time information of each cell and the reception time of the actual reception, and determines the maximum delay time from the delay times of the plurality of cells. The minimum delay time is calculated. The cell synchronization signal protection unit 207 has a function of generating a normal cell synchronization signal from the abnormal test synchronization signal when the abnormal test synchronization signal is received.

The ATM switch 300 is a switch having a function as an exchange for switching VP (Virtual Path) in the ATM system. The broken lines in the figure show the flow of cell data.

Next, a specific structure of the ATM system test apparatus will be described. FIG. 2 is a block diagram showing a specific configuration of the transmission unit 100. << Configuration of Transmission Side >> The transmission unit 100 includes the sequential number generation unit 101 to the traffic pattern control unit 10 described above.
6, and a mode setting unit 108, a transmission cell counter unit 109, a PN generation circuit 110, a payload assembling unit 111, and a cell assembling unit 112.

The mode setting unit 108 is based on an address and data from a central processing unit (CPU) (not shown).
A traffic pattern mode signal or start signal to the traffic pattern control unit 106, and further the cell assembling unit 11
2 header value and test test cell sync signal generator 10
The control signal of the SYNC mode is sent to the S. As described above, the traffic pattern control unit 106 has a function of controlling the traffic of the test cells to be output. For example, the test pattern is output continuously in a burst manner, or n cells are empty in N cells. It controls traffic such as whether to flow cells.

The transmission cell counter section 109 includes a transmission section 10
A counter unit for counting the number of cells transmitted from 0. The time stamp generation unit 104 is a circuit for inserting the transmitted current time into a cell based on the cell transmission enable signal output from the traffic pattern control unit 106.

The PN generation circuit 110 is a circuit for generating PN pattern data to be inserted into the payload portion of an output cell. Further, the error detection code generation unit 102
As described above, the sequential number generation unit 101
It has a function of generating an error detection code with respect to the sequential number output from, and in the present embodiment, a parity bit for parity check is generated.

The payload assembling section 111 is a circuit for assembling a sequential number, a parity bit, PN data and a time stamp. Then, the payload section error detection code generation section 103 performs CRC calculation (Cy
clic redundancy check) to generate the error detection code. Further, the cell assembling unit 112 has a payload unit error detection code generating unit 103.
Is inserted into the cell, and the header value of the test cell given from the mode setting unit 108 is added to assemble the cell.

The test cell synchronization signal generator 105 is also provided.
Can generate several kinds of abnormal SYNC signals. For example, in addition to normal SYNC, there are SYNC cycle abnormality, SYNC width abnormality, abnormal SYNC insertion, and the like.

FIG. 3 is an explanatory diagram showing these signals. That is, in this case, the normal SYNC is 53 bytes, and the timing of the rising portion of the normal SYNC coincides with the abnormal SYNC width, but the SYNC is abnormal.
This SYNC width can be set to an arbitrary value with signals having different C widths. Further, the abnormal SYNC insertion is to insert an extra SYNC signal in addition to the normal SYNC. Furthermore, the SYNC cycle abnormality is a state in which SYNC is not output at the position of normal SYNC that is originally output.

Next, the structure of the receiving section 200 will be described. << Configuration of Receiving Side >> FIG. 4 is a block diagram showing the configuration of the receiving unit 200. The reception unit 200 includes the sequential number error detection unit 201 to the cell synchronization signal protection unit 207 described above.
And a VPI / VCI collating unit 208, an unallocated cell counter 209, and an arithmetic processing unit 210.

When the cell sync signal protector 207 receives an abnormal SYNC signal as shown in FIG.
It has a function of correcting to a YNC signal. VPI / VC
The I verification unit 208 uses the VPI / of the header part of the received cell.
It has a function of extracting only test cells based on the VCI.

The sequential number error detector 201 is
A parity check is performed on the sequential number in the received cell to determine whether the sequential number is correct or not. When a parity error is detected, a counter is provided for counting the number of errors. The reception cell counter 202 is a counter for counting the number of test cells extracted by the VPI / VCI matching unit 208.

The sequential number judging unit 203 generates an expected value for managing the sequential number on the receiving side based on the value counted by the receiving cell counter 202, and the expected value and the received cell are given. It has a function of comparing sequential numbers and checking the sequential numbers. Also, as a result of the comparison, if there is a mismatch, it is determined as a cell missing error,
Moreover, it is provided with a counter for counting the number.

The payload section error determination section 205 uses the CRC
The arithmetic circuit is provided with a counter for detecting a bit error in the payload portion by performing a CRC operation and counting the number of errors when there is an error. The cell delay time calculation unit 206 calculates the delay time of each cell from the transmission time information included in the received cell and the time actually received by the reception unit 200, and determines the maximum value (Max) of these delay times. The minimum value (Min) is obtained.

The unallocated cell counter 209 has a VPI / V
This is a counter for counting the number of unallocated cells other than the test cells extracted by the CI collating unit 208.
The arithmetic processing unit 210 includes a processor and the like, and the receiving unit 2
Various errors as 00 are performed. In addition, as described above, the error rate calculation unit 204 includes the number of reception cells of the reception cell counter 202, the number of parity errors of the sequential number error detection unit 201, the number of cell omission errors of the sequential number determination unit 203, and the payload unit. It has a function of obtaining an error rate as a system based on the number of CRC errors of the error determination unit 205.

Next, the operation of the ATM system test apparatus having the above configuration will be described. << Operation on Transmission Side >> First, what traffic pattern is to be tested from the central processing unit (CPU), what SYNC is to be output, and the definition (VPI / VCI) of the test cell, This is set in the mode setting unit 108.

As a result, the mode setting section 108 sends the setting signal to the traffic pattern control section 106, the test cell synchronization signal generating section 105 and the cell assembling section 112. The traffic pattern control unit 106 outputs a cell transmission enable signal only when outputting a test cell. As a result, the PN generation circuit 110 generates a random number. In addition, the sequential number generation unit 101
Generates a sequential number for each cell, and further adds a parity bit for determining the correctness of the sequential number in the error detection code generation unit 102. Then, the time stamp generation unit 104 inserts the time of transmission (time stamp information) in the payload part. Further, the transmission cell counter unit 109 counts the number of cells.

The payload assembling section 111 has the sequential number + parity bit, time stamp information,
The payload part is assembled based on the PN pattern data. Furthermore, the payload section error detection code generation section 10 in the next stage
In 3, the CRC operation is performed on the payload part, and the result is inserted into the 52nd and 53rd bytes of the cell by the cell assembling part 112, and this is output together with the cell header.

FIG. 5 is an explanatory diagram of a format of a cell to be output. The illustrated cell has a cell length of 53 bytes, with a cell header of 5 bytes and a cell payload portion of 48 bytes. Then, "P" in the payload part
“A” is a parity bit generated by the error detection code generation unit 102, and “CRC” is a bit of the CRC calculation result.

The test cell synchronization signal generator 105 is also provided.
Outputs the set SYNC to the assembled cell data at the timing.

<< Operation on Receiving Side >> The receiving section 200 inputs the cell data and the SYNC signal output from the transmitting section 100. First, when there is an abnormal SYNC signal, the cell synchronizing signal protecting section 207 Output as a normal SYNC signal. For example, in the case of the SYNC width abnormality shown in FIG. 3, paying attention to the rising timing, the S of a predetermined bit width is
Generate a YNC signal. When an abnormal SYNC is inserted, the period from the normal SYNC to the SYNC at the 53rd byte is masked by a counter (not shown) provided in the cell synchronization signal protection unit 207, and only the normal SYNC is inserted. To extract. Further, when the SYNC cycle is abnormal, a counter (not shown) generates the SYNC at the 53rd byte from the normal SYNC, and generates the SYNC signal with the 53-byte cycle.

The VPI / VCI collating section 208 detects only the cell under test by the VPI / VCI of the cell header section, and the sequential number error detecting section 201
Check the normality of the sequential numbers. Since this parity check is a known method, its explanation is omitted here. If the sequential number error detection unit 201 confirms the normality of the sequential number,
The sequential number determination unit 203 determines the sequential number. This determination is performed as follows.

That is, since the transmitting section 100 gives the sequential numbers and outputs the same, the receiving section 200 also sequentially counts each cell and uses this as an expected value. Then, the expected number and the sequential number of the received cell are collated by the sequential number determination unit 203. If the result of the collation is a mismatch, the sequential number determination unit 203 determines that there is an error (cell missing), and after the error, increments the sequential number that was in error (sequential number of the received cell) by 1 and It is used as the expected value of the sequential number of.

Further, the payload section error decision section 205 of the receiving section 200 detects the bit error by performing the CRC calculation of the payload section of the cell. In addition, this C
Since the RC calculation is a known method, its explanation is omitted here.

Then, the sequential number error detector 2
The number of parity errors detected in 01, the number of cell omissions detected in the sequential number determination unit 203, and the number of errors detected in the payload unit error determination unit 205 are output to the arithmetic processing unit 210. Further, the reception cell counter 202 counts the number of test cells received,
The value is output to the sequential number determination unit 203 and the arithmetic processing unit 210. Furthermore, the unallocated cell counter 209
Counts how many cells other than the test cell are received, and outputs this value to the arithmetic processing unit 210.

6 and 7 are explanatory diagrams of the sequence of the error counter. As shown in FIG.
At 0, parity check → sequential number check → CRC calculation check is performed from the received cell. And
The resulting counter values of (1) to (12) are as shown in FIG. That is, in (1), since the parity is OK, the sequential number is OK, and the CRC calculation is OK, this is a normal cell, and therefore only the counter value of the reception cell counter 202 is incremented. (2) is (1) and CRC operation is NG
Therefore, the CRC error counter (the counter of the payload error determination unit 205) is also incremented by 1.

Further, in (3), only the sequential number is N
Since it is G, the reception cell counter 202 and the sequential number error counter (the counter of the sequential number determination unit 203) are incremented by one. (4) is
Since the CRC calculation result is NG in the state of (3), the CRC error counter is further incremented by one.

Then, (5) is a case where the parity check result is NG and the CRC calculation result is OK. Accordingly, the reception cell counter 202 and the parity error counter are incremented by 1, and the sequential number error counter is incremented by 1 when the next cell is received. That is, in this case, since the expected value remains unchanged in this case, a sequential number error will always occur when the next cell is normal. In case of (6), it is (5), and C
Since the RC operation result was NG, CR
The C error counter is incremented by 1.

In the cases of (7) to (12), since it is an unallocated cell, only the value of the unallocated cell counter 209 is counted up.

The cell delay time calculating section 206 also receives the time stamp information of the received cell (time of the transmitted cell).
And the reception time of the cell delay time calculation unit 206 are compared, and the time from transmission to reception is converted (reception time-transmission time). And do this for each cell,
The maximum delay and the minimum delay are transmitted to the arithmetic processing unit 210.

The error rate calculation unit 204 receives the counter value of the reception cell counter 202, the counter value of the parity error of the sequential number error detection unit 201, the counter value of the sequential number error of the sequential number determination unit 203, and the payload unit error. The error rate of the system is obtained based on the CRC error counter value of the determination unit 205. That is, error rate = {(parity error counter value + sequential number error counter value + CRC
Error counter value) / (number of received allocation cells)} × 1
It is obtained from 00 (%).

The error rate may be calculated not for every error but for each error.

As described above, according to the above embodiment, a parity bit is added as an error detection code for the sender side to determine whether the sequential number is correct, and the receiver side uses this parity bit to determine whether the sequential number is correct or incorrect. Since the determination is made, when a sequential number causes a bit error, a parity error occurs instead of a cell loss, and a bit error occurs. Also,
Since the sequential number determination unit 203 counts the number of cell omissions, even when cell omissions occur, the number can be accurately grasped. Furthermore, since the error rate calculation unit 204 calculates the error rate, the error rate of the system can be calculated.

In the receiving section 200, the CRC calculation circuit
Since the bit error in the payload part is detected,
The PN generation circuit is not required, and therefore the circuit scale can be reduced while maintaining the same bit error detection capability. That is, the PN generation circuit has a much larger amount of hardware than the CRC calculation circuit.

While offline (when there is no user data), the traffic pattern control unit 106 can select a fixed arbitrary traffic pattern for the test cell to be output, so that the traffic of the cell of the system is selected. You can measure your ability to.

Since the test cell synchronization signal generator 105 outputs several kinds of SYNC signals, it is possible to perform a test for guaranteeing normal operation of the system when an abnormal cell synchronization signal is input.

The time stamp generation unit 104 and the cell delay time calculation unit 206 can easily measure cell delays and fluctuations, which is very effective in testing the performance of the ATM system.

In the above embodiment, as shown in FIG. 1, the VP is tested through the ATM switch 300. However, if the ATM system is used for testing the communication medium, other configurations are possible. Can be similarly applied.

FIG. 8 is a block diagram showing such another embodiment. That is, this embodiment is an example in which the transmission unit 100 and the reception unit 200 are connected to a line such as an optical fiber or an electric wire via the line interface circuits 400A and 400B that perform physical layer processing. With such a configuration, it is possible to test the line physical media such as the line interface circuits 400A and 400B, the optical fiber, and the electric wire. Examples of such a line include SDH and FDDI.

[0062]

As described above, the ATM system test apparatus of the present invention has the following effects.

Since the correctness of the sequential number is determined, the cell omission can be accurately detected.
Further, since the error rate regarding various errors is calculated, it is possible to obtain an accurate error rate as a system.

Since the bit error in the payload section is detected by the error detection code added to the payload section, the conventional PN generation circuit becomes unnecessary, and as a result, the amount of hardware can be reduced. it can.

Since the traffic pattern control unit selects an arbitrary traffic pattern, it is possible to measure the ability of the system cell for traffic.

Since the test cell synchronization signal generator sends an arbitrary abnormal cell synchronization signal, it is possible to perform a test for guaranteeing normal operation of the system when an abnormal cell synchronization signal is input. .

Since the cell delay time is obtained from the cell transmission time and cell reception time, the cell delay and fluctuation can be easily measured.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an ATM system test apparatus of the present invention.

FIG. 2 is a block diagram of a transmission unit in the test apparatus for the ATM system of the present invention.

FIG. 3 is an explanatory diagram of a cell synchronization signal output by a test cell synchronization signal generator of the ATM system test apparatus of the present invention.

FIG. 4 is a block diagram of a receiving unit in the ATM system test apparatus of the present invention.

FIG. 5 is an explanatory diagram of a format of an output cell in the ATM system test apparatus of the present invention.

FIG. 6 is an explanatory diagram (No. 1) of the sequence of the error counter in the ATM system test apparatus of the present invention.

FIG. 7 is an explanatory diagram (part 2) of the sequence of the error counter in the ATM system test apparatus of the present invention.

FIG. 8 is a configuration diagram showing another embodiment of the ATM system test apparatus of the present invention.

[Explanation of symbols]

 100 transmitter 101 sequential number generator 102 error detection code generator 103 payload error detection code generator 104 time stamp generator 105 test cell synchronization signal generator 106 traffic pattern controller 200 receiver 201 sequential number error detector 202 Received cell counter 203 Sequential number determination unit 204 Error rate calculation unit 205 Payload unit error determination unit 206 Cell delay time calculation unit 207 Cell synchronization signal protection unit 300 ATM switch

Claims (6)

[Claims] 1. An ATM system test apparatus for connecting a transmission unit and a reception unit via a communication medium of an asynchronous transfer mode system to test the communication medium, wherein the transmission unit is assigned to a cell to be transmitted. A sequential number generation unit that generates a sequential number and an error detection code generation unit that generates an error detection code for correctness determination with respect to the sequential number are provided, and the reception unit is included in the cell from the received cell. Error detection code, the sequential number error detection unit for determining whether the sequential number is correct, for each reception of the cell, a reception cell counter that counts the number of reception cells, the sequential number error detection unit, If it is determined that the sequential number is correct, the sequential number of the cell and the Matches with a received cell number of signal cell counter, if these values are in disagreement,
A test apparatus for an ATM system, comprising: a sequential number judging unit for judging a cell missing error. 2. A test apparatus of an ATM system for connecting a transmission unit and a reception unit via a communication medium of an asynchronous transfer mode system to test the communication medium, wherein the transmission unit is a payload unit of a cell to be transmitted. A payload section error detection code generation section for generating an error detection code for detecting a bit error for the cell, and the reception section detects a bit error error for the payload section of the cell from the error detection code in the received cell. A comprising a payload section error determination section
TM system test equipment. 3. A test apparatus of an ATM system, which connects a transmission unit and a reception unit via a communication medium of an asynchronous transfer mode system to test the communication medium, wherein the transmission unit transmits to the reception unit. As a cell synchronization signal, a test cell synchronization signal generator that transmits a test abnormal synchronization signal different from the normal cell synchronization signal is provided, and the receiving unit is for the test when the test abnormal synchronization signal is received. An ATM system test apparatus comprising a cell synchronization signal protection unit for generating a normal cell synchronization signal from an abnormal synchronization signal. 4. An ATM system test apparatus for connecting a transmitter and a receiver via a communication medium of an asynchronous transfer mode system to test the communication medium, wherein the transmitter is provided for each cell to be transmitted. A time stamp generating unit for giving transmission time information, wherein the receiving unit calculates the delay time of the cell from the transmission time information of each received cell and the actually received reception time, and a plurality of cells A test apparatus for an ATM system, comprising a cell delay time calculation unit for calculating a maximum delay time and a minimum delay time from the delay time for 5. In a test device of an ATM system for connecting a transmitter and a receiver via a communication medium of an asynchronous transfer mode system to test the communication medium, the transmitter is attached to a cell to be transmitted. A sequential number generation unit that generates a sequential number, an error detection code generation unit that generates an error detection code for determining whether the sequential number is correct, and an error detection code for detecting a bit error with respect to the payload portion of the cell to be transmitted. A payload section error detection code generating section for generating, the receiving section, from the received cell, by the error detection code contained in the cell, the sequential number error detection section to determine whether the sequential number is correct A reception cell counter that counts the number of reception cells each time the cell is received, In Kensharu ID error detection unit, when it is determined that the sequential number is correct, it matches it to a sequential number and the received cell number of the reception cell counter of the cell, when these values are in disagreement,
Sequential number determination unit for determining a cell missing error, a payload unit error determination unit for detecting a bit error error with respect to the payload unit of the cell from the error detection code in the received cell, and the total received cells received by the reception cell counter For the number of bits, an error rate is calculated from the bit error of the sequential number detected by the sequential number error detection unit, the cell missing error detected by the sequential number determination unit, and the bit error of the payload unit detected by the payload unit error determination unit. An ATM system test apparatus, comprising: an error rate calculation unit to be obtained. 6. The ATM according to claim 1.
In the system test apparatus, the transmitter includes a traffic pattern controller that controls a ratio of a test cell and an empty cell in a cell stream to be transmitted, the ATM system test apparatus.