JPH0823079A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily manufacture a semiconductor integrated circuit device equipped with ferroelectric capacitors high in degree of integration and in characteristics by a method wherein a second insulating film provided with a surface which is kept in contact with the side wall of a first electrode and flush with it is provided onto the selective region of a first insulating film. CONSTITUTION:A second insulating film 8 of a ferroelectric capacitor is provided with a surface flush with that of a first electrode 16 in the selective region of a first insulating film 7. Therefore, even if the first electrode 16 is formed of a single-layered film of platinum or the like hard to process or a laminated film whose surface layer is formed of Pt, the first electrode 16 can be patterned as prescribed in form and size conforming to a groove without an etching process through a method that the first electrode 16 is buried in the groove cut in the second insulating film 8 by fine processing. By this setup, ferroelectric capacitors can be provided high in degree of integration in a region of small area, so that a semiconductor integrated circuit device provided with ferroelectric capacitors high in degree of integration can be easily manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and is particularly effective when applied to a semiconductor integrated circuit device provided with a nonvolatile RAM (Random Access Memory) having a ferroelectric capacitor. Related technology.

[0002]

2. Description of the Related Art Nonvolatile RAM is an LSI (Large Scal).
e Integrated Circuit) A type of memory that can be freely read and written and can store a large amount of data.

The non-volatile RAM uses a ferroelectric capacitor composed of two electrodes and a ferroelectric film sandwiched between the electrodes as a memory element, and includes a switch MISFET and the ferroelectric substance connected to the switch MISFET. It is composed of a capacitor, and one of the ferroelectric capacitors corresponds to one bit.

Information of "1" and "0" is stored by changing the direction of spontaneous polarization generated in the ferroelectric film according to the direction of voltage applied to the two electrodes in the ferroelectric capacitor.

Since the direction of the spontaneous polarization generated in the ferroelectric film remains even after the voltage applied to the two electrodes is removed, the information can be stored in a nonvolatile manner.

Nikkei Microdevices March 1991 page 83 and 84 and Nikkei Microdevices 199
The method for manufacturing a non-volatile RAM described in pages 111 to 116 of the January 2, 2012 issue is a method of forming a switch MISFET and then forming a first conductive film made of platinum via an insulating film on the switch MISFET. And then the first conductive film is patterned to form a first electrode. Next, lead zirconate titanate (P
After forming a ferroelectric film made of ZT) or the like, a second conductive film is deposited on the ferroelectric film, and then the second conductive film is patterned to form a second electrode.

[0007]

However, the present inventor has found that the above-mentioned method for manufacturing a nonvolatile RAM has various problems as described below.

(1) There is a problem that the first electrode cannot be miniaturized.

That is, in order to increase the degree of integration of the nonvolatile RAM, it is necessary to miniaturize the ferroelectric capacitor as in the case of the dynamic RAM. The miniaturization of the ferroelectric capacitor means microfabrication of the first electrode and the second electrode. In the usual manufacturing process of semiconductor integrated circuit devices, electrodes are processed by a dry etching method using a gas containing halogen such as chlorine. Since halide exists in the conductive film such as silicon or aluminum used in the semiconductor integrated circuit device, etching is performed using this halide.

By the way, platinum used for the first electrode of the ferroelectric capacitor is used as the first electrode because it is difficult to react with other substances as described above. Therefore, dry etching using a halide cannot be used as it is as in the manufacturing process of the semiconductor integrated circuit device. Therefore, the platinum used for the first electrode is processed by physical collision using the ion milling method. Therefore, it is difficult to finely process the platinum used for the first electrode, and further, there is a problem that the insulating film below the first electrode is damaged.

Further, there has been an attempt by a reactive ion etching method using a halogen gas, but since a deposit is formed on the side surface and the upper part of the first electrode, it is necessary to remove the deposit. There is a problem that dust is generated during the removal.

(2) There is a problem that the film quality of the ferroelectric film is deteriorated at the step at the end of the first electrode.

That is, in the manufacturing method of patterning the first electrode after depositing the first conductive film on the insulating film, the film thickness of the first electrode is formed on the end portion of the first electrode. There is a step corresponding to. The step is usually 100
~ 200 nm. The ferroelectric film such as PZT is a composite material, and the ferroelectric film is deposited by the CVD method, the sol-gel method, the sputtering method, or the like.

The deposited film formed by the above-mentioned methods has a problem that if there is a stepped portion in the base, the film quality at the stepped portion is deteriorated as compared with the flat portion. Deterioration in the ferroelectric film is a decrease in relative permittivity, a decrease in spontaneous polarization,
There is a problem that the number of times of inversion of the branch is decreased and the leak current is increased.

An object of the present invention is to provide a semiconductor integrated circuit device which is highly integrated and is provided with a ferroelectric capacitor having high characteristics.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having a highly integrated and highly-characteristic ferroelectric capacitor.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0018]

The typical ones of the inventions disclosed in the present invention will be outlined below.

(1) In the semiconductor integrated circuit device of the present invention, the surface of the first insulating film, which is connected to either the semiconductor region serving as the source or the semiconductor region serving as the drain in the switch MISFET, and has a flat surface A first electrode having a flat surface provided thereon, a ferroelectric film provided on the first electrode, and a second electrode provided on the ferroelectric film. A ferroelectric capacitor composed of and is arranged in a selective region on the first insulating film, and is provided in contact with a side wall of the first electrode. And a second insulating film having a surface flush with the surface of the first electrode.

(2) In the method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a first insulating film on a semiconductor substrate including a switch MISFET, and a surface of the first insulating film are made flat. And a step of forming a second insulating film on the first insulating film, forming a first groove and a second groove in a selective region of the second insulating film, and 1
Forming a first contact hole in a part of the first insulating film below the trench of 1 to be a contact region of either the semiconductor region to be the source or the semiconductor region to be the drain, and A step of forming a second contact hole, which is a contact region of either the semiconductor region serving as the source or the semiconductor region serving as the drain, in a part of the first insulating film below the second groove. And the first contact hole, the second contact hole, the first groove, and the second
Forming a first electrode having a surface flush with the surface of the second insulating film by burying the first conductive film in the groove of Forming a ferroelectric film on the first electrode embedded in the first groove, and then forming a second conductive film on the ferroelectric film. .

[0021]

According to the above-described semiconductor integrated circuit device of the present invention, the first electrode of the ferroelectric capacitor is connected to either the semiconductor region serving as the source or the drain of the switch MISFET. And the surface provided on the surface of the flat first insulating film serves as a flat first electrode, which is arranged in a selective region on the first insulating film. Is provided in contact with the side wall of the first electrode and has a second insulating film having a surface that is flush with the surface of the first electrode. For example, the first electrode is difficult to process. Even if a single layer film made of platinum or the like or a laminated film made of platinum for the surface portion of the first electrode is used,
By embedding the first electrode in a groove that can be provided in the second insulating film by fine processing, it is possible to pattern the shape and size corresponding to the groove without etching. By processing, it can be provided in a small area in a highly integrated state.

Further, the first electrode having a flat surface and a surface flush with the surface of the second conductive film, and a strong electrode provided on the first electrode. Since the ferroelectric capacitor includes a dielectric film and a second electrode provided on the ferroelectric film, the first capacitor in contact with the second insulating film can be obtained.
Since the electrode has no step, the ferroelectric film provided on the first electrode is also provided without a step, so that the deterioration of the film quality of the ferroelectric film is suppressed and the characteristics are excellent. It is possible to provide the ferroelectric capacitor.

According to the method for manufacturing a semiconductor integrated circuit device of the present invention described above, after the first conductive film is embedded in the first groove and the second groove, the first conductive film is used to form the first conductive film. Forming the first electrode having a surface flush with the surface of the second insulating film;
Forming a second conductive film on the ferroelectric film after forming a ferroelectric film on the first electrode embedded in the groove of the first electrode. Even if the electrode is a single layer film made of platinum or the like, which is difficult to process, or a laminated film made of platinum on the surface of the first electrode, the first electrode is made to be the second insulating film. By embedding in the first groove that can be formed by microfabrication, the ferroelectric capacitor can be patterned with a shape and size corresponding to the first groove without etching. Therefore, the ferroelectric capacitor can be microfabricated in a small area. Can be manufactured in a highly integrated state.

Further, the first electrode having a flat surface which is flush with the surface of the second insulating film, and a ferroelectric formed on the first electrode. The first electrode that is in contact with the second insulating film because it is a ferroelectric capacitor including a body film and a second electrode formed on the ferroelectric film. Can be formed without a step, so that the ferroelectric film formed on the first electrode can also be formed without a step, the deterioration of the film quality of the ferroelectric film can be suppressed, and the characteristics are excellent. The ferroelectric capacitor can be manufactured.

[0025]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

(Embodiment 1) FIGS. 1 to 5 are sectional views showing a semiconductor integrated circuit device and a manufacturing process thereof according to an embodiment of the present invention, specifically, one switch MOSFE.
FIG. 6 is a cross-sectional view showing a semiconductor integrated circuit device including a nonvolatile RAM in which a plurality of ferroelectric capacitors are connected to T and a manufacturing process thereof. A semiconductor integrated circuit device of the present invention and a specific manufacturing method thereof will be described with reference to FIG. 1 to 5, the cross-sectional views shown on the left are parallel to the data lines, and the cross-sectional views shown on the right of the arrows are perpendicular to the data lines. It is sectional drawing of various directions.

First, as shown in FIG. 1, for example, an n-type impurity for forming a channel stopper is ion-implanted into an element isolation region on the surface of a semiconductor substrate 1 made of, for example, p-type silicon (Si) single crystal. By selectively thermally oxidizing the surface of the semiconductor substrate 1, the field insulating film 2 made of a thick silicon oxide film or the like is formed. During this thermal oxidation process, the n-type impurities introduced into the element isolation region are diffused to form a channel stopper layer (not shown) under the field insulating film.

After that, a gate insulating film 3 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1, and then a polycrystalline silicon film containing a conductive impurity is formed on the semiconductor substrate 1 by the CVD method. After that, the gate electrode 4 is formed by selectively removing the polycrystalline silicon film by photolithography.

Next, an n-type impurity is ion-implanted into a region where the surface of the semiconductor substrate 1 is exposed and diffused to form an n-type semiconductor region 5 serving as a source and an n-type semiconductor region 6 serving as a drain. Formed at the same time, a switch MOSFET is manufactured. It is also applicable when the semiconductor region 5 is the drain and the semiconductor region 6 is the source.

In FIG. 1, an n-channel switch M
Although the OSFET is shown, a p-channel switch MOSFET is provided in a region (not shown) of the semiconductor substrate 1.
T is also formed, and C is formed by using those MOSFETs.
It has a MOS (Complementary MOS) structure.

An insulating film (first insulating film) 7 is formed on the semiconductor substrate 1 so as to cover the upper part of the switch MOSFET.

The insulating film 7 is, for example, a silicon oxide film formed by a CVD method, a PSG (Phosho Silicate Glass) film which is a silicon oxide film containing phosphorus, or a BP which is a silicon oxide film containing boron and phosphorus.
The insulating film 7 is formed by a single-layer film made of an SG (Boron Phosho Silicate Glass) film or a laminated film in which these are deposited, and then a flattening process is performed to flatten the surface of the insulating film 7.

This flattening treatment is performed by reflowing the PSG film or BPSG film containing a high concentration of phosphorus (P) by heat treatment at a high temperature. However, as the flattening treatment, a mode in which the surface of the insulating film 7 is flattened by an etch back method or a chemical mechanical polishing (CMP) method can be adopted.

Next, an insulating film (second insulating film) 8 is formed on the insulating film 7.

The insulating film 8 is formed to function as an etching stopper film, and is made of, for example, a silicon nitride film or an aluminum oxide film formed by the CVD method, but the etching rate is different from that of the insulating film 7. Other types of insulating films may be used as long as they are insulating films made of the above material.

The flattening process of the insulating film 8 can be omitted by performing the flattening process of the insulating film 8.
In Example 1, since the insulating film 7 is planarized, the insulating film 8 is not planarized. That is, either the insulating film 7 or the insulating film 8 may be planarized, and the surface of the insulating film 8 after the insulating film 7 is formed by the planarizing process may be flat.

Next, the openings 9 and 10 are formed in the insulating film 8 by the photolithography technique using the photoresist film as a mask.

The opening 9 is used when forming a contact hole for connecting the semiconductor region 5 in the switch MOSFET and a ferroelectric capacitor described later.

The opening 10 is used to form a contact hole for connecting the semiconductor region 6 in the switch MOSFET to the data line.

Next, an insulating film (third insulating film) 11 made of, for example, a silicon oxide film is formed on the insulating film 8. The film thickness of the insulating film 11 is the same as the film thickness of the first electrode of the ferroelectric capacitor described later. Insulating film 11 is insulating film 7
It is formed by the same method as.

Next, as shown in FIG. 2, the insulating film 11 is selectively removed by etching using a photolithography technique using a photoresist film as a mask to form a groove 12 and a groove 13. In this case, the insulating film 8
Is an etching stopper film.

The groove 12 becomes a first electrode forming region of a ferroelectric capacitor described later, and the groove 13 is a switch MOSFET.
It becomes the drain electrode formation region of T.

Thereafter, by using the photoresist film and the insulating film 8 as a mask, the insulating film 7 is removed by etching to form contact holes 14 and 15 at the same time so that a part of the semiconductor regions 5 and 6 are exposed. Also in this case,
The insulating film 8 serves as an etching stopper film.

Next, an operation for removing the unnecessary photoresist film is performed.

Next, as shown in FIG. 3, a first electrode 16 of a ferroelectric capacitor and a drain electrode 17 of the switch MOSFET, which will be described later, are formed in the grooves 12 and 13, respectively.

The first electrode 16 is a portion constituting a lower electrode of a ferroelectric capacitor described later, and is made of a material having a low reactivity with oxygen or the like such as platinum. The reason is that, if a highly reactive material is used as the material of the first electrode 16, an oxide film is formed on the first electrode 16, and as a result, the capacitance of the ferroelectric capacitor decreases. Is.

That is, even if a material having a very high non-dielectric constant is used for the first electrode 16, the first electrode 16
When an oxide film is formed on the upper surface, the insulating film for the capacitor is composed of the oxide film and the insulating film having a high non-dielectric constant.
Since it has a layered structure and two capacitors are connected in series in terms of a circuit, the capacitance of the entire capacitor is substantially the same as that of a capacitor including only an oxide film, and a ferroelectric film is used. Because it has no meaning.

By the way, in the first embodiment, the first electrode 16 and the drain electrode 17 are formed by framing the grooves 12 and 13, and the upper surface thereof is the upper surface of the third insulating film 11. It is formed to match.

That is, since the dimensions of the first electrode 16 and the drain electrode 17 are set by the dimensions of the grooves 12 and 13 which can be formed with relatively high dimensional accuracy, the first electrode 16 and the drain electrode 17 are set. Even if it is made of a material such as platinum, which has a low processing dimensional accuracy, it can be formed with high dimensional accuracy.

Further, since the method of patterning the first electrode 16 and the drain electrode 17 by a physical collision action such as the ion milling method is not used, no foreign matter is generated.

Moreover, in the first embodiment, the first electrode 16 of the ferroelectric capacitor, which will be described later, and the switch MO.
The drain electrode 17 of the SFET can be formed at the same time.

This is because, in the case of the first embodiment, the drain electrode 17 can also be dimensioned by setting the planar dimension of the groove 13, so that dimensional accuracy can be secured even if platinum, which is the same material as the first electrode 16, is used. Is.

Therefore, in the first embodiment, the first electrode 16 of the ferroelectric capacitor and the switch MOSFE are
It is possible to reduce the number of manufacturing steps of the semiconductor integrated circuit device as compared with the case where the drain electrode 17 of T is separately formed of different materials.

Furthermore, since the upper surfaces of the first electrode 16 and the drain electrode 17 and the upper surface of the insulating film 11 are aligned with each other, no step is formed at the ends of the first electrode 16 and the drain electrode 17. Therefore, it is possible to prevent problems such as deterioration of film quality of an insulating film for a capacitor, which will be described later, due to the step.

The first electrode 16 and the drain electrode 17 as described above are formed, for example, as follows. First, on the semiconductor substrate 1 shown in FIG. 2, for example, a first conductor film made of platinum or the like is deposited by a sputtering method or the like so as to cover the insulating film 11 so as to be thicker than the film thickness of the insulating film 11.

Next, a photoresist film or an SOG (Spin On Glass) film is deposited on the first conductive film to an extent that the upper surface thereof is substantially flat, and then etched back to a level higher than that of the surface of the insulating film 11. By removing the first conductive film on the upper side by etching, the first electrode 16 and the drain electrode 17 are formed so that the surfaces thereof coincide with the surface of the insulating film 11. The photoresist film is formed by a spin coating method using a spinner, and the SOG film is made of silicon oxide or the like formed by a spin coating method using a spinner. After forming them, the photoresist film or Even if the shape under the SOG film has irregularities, it has a flat surface.

However, as another method of planarizing the first conductive film, a chemical mechanical polishing (CMP) method is used to remove the first conductive film above the surface of the insulating film 11 so as to planarize the surface. It is possible to adopt a method of making

Next, as shown in FIG. 4, a ferroelectric capacitor C is formed on the semiconductor substrate 1. The ferroelectric capacitor C is composed of a first electrode 16 and a second electrode 19 formed on the first electrode 16 with a ferroelectric film 18 therebetween.

The ferroelectric film 18 is made of, for example, PZT (lead zirconate titanate) or the like. In addition, the second electrode 19
Is made of a material such as titanium, which is easily microfabricated. The material that can be finely processed can be used as the material of the second electrode 19 for the following reason.

That is, since the second electrode 19 can be formed in a non-oxidizing atmosphere such as a sputtering method, the second electrode 19 and the lower ferroelectric film 18 are formed during the formation. Since an oxide film is not formed between the second electrode 19 and the second electrode 19, it is not necessary to use a material having a low reactivity with oxygen or the like as platinum or the like, and a ferroelectric material. This is because the film 18 itself is originally a composite material containing oxygen, so that no new oxide film is formed on the upper surface thereof.

By the way, in the first embodiment, as described above, since the upper surface of the first electrode 16 coincides with the upper surface of the insulating film 11, no step is formed at the end of the first electrode 16. . Therefore, the ferroelectric film 1 formed on the upper surface thereof
8 also has no step at its end, so that the film quality does not deteriorate.

The ferroelectric film 18 and the second electrode 19 as described above are formed, for example, as follows.

First, a ferroelectric film made of, for example, PZT is formed on the semiconductor substrate 1 shown in FIG. 3, for example, by CVD.
Method, sputtering method or sol-gel method, a second conductive film made of titanium, for example, is deposited on the upper surface by sputtering method or the like.

Then, after forming a photoresist film on the second conductive film, a photolithography technique using the photoresist film as a mask is used to form the second conductive film and the ferroelectric material in the lower layer. By sequentially removing the film 18 by etching, the ferroelectric film 18 and the second electrode 1
9 is patterned.

At this time, the ferroelectric film and the conductive film on the drain electrode 17 are removed. The reason is that a data line, which will be described later, formed in the upper wiring layer is connected to the upper portion of the drain electrode 17.

After that, the work of removing the unnecessary photoresist film is performed.

Next, as shown in FIG. 5, an insulating film 20 is deposited on the ferroelectric capacitor.

As the insulating film 20, for example, a single layer film of a silicon oxide film or a silicon nitride film formed by a sputtering method or a plasma CVD method or a laminated film in which these are deposited is adopted.

Through holes 2 are formed in the insulating film 20 by using a photolithography technique using a photoresist film as a mask.
1 is formed.

Next, after removing the photoresist film, the third conductive film 22 to be the above-mentioned data line is deposited. As the third conductive film 22, for example, a single layer film of aluminum, titanium, tungsten or the like formed by a sputtering method or a CVD method or a laminated film in which these are deposited is adopted.

Next, the third conductive film 22 is selectively etched by the photolithography technique using the photoresist film as a mask to form a wiring pattern having a predetermined shape.

After that, the work of removing the photoresist film which has become unnecessary is performed.

Next, although not shown, a wiring layer and a passivation film above the passivation film or the third conductive film 22 are formed, the passivation film is selectively removed, and a bonding pad is formed in that region. A semiconductor integrated circuit device is manufactured by forming the semiconductor integrated circuit device.

In the first embodiment described above, the ferroelectric capacitor C composed of the first electrode 16 and the second electrode 19 and the ferroelectric film 18 sandwiched between them is used as a memory element. And a semiconductor integrated circuit device including a nonvolatile RAM. Further, it is composed of a switch MOSFET and the ferroelectric capacitor connected to the switch MOSFET, and one ferroelectric capacitor corresponds to 1 bit.

Then, by changing the direction of the spontaneous polarization generated in the ferroelectric film 18 depending on the direction of the voltage applied to the first electrode 16 and the second electrode 19 of the ferroelectric capacitor, "1" and "1" are obtained. Information of "0" is stored. Further, the direction of the spontaneous polarization generated in the ferroelectric film 18 remains even after the voltage applied to the first electrode 16 and the second electrode 19 is removed, so that information can be stored in a nonvolatile manner.

(Embodiment 2) A semiconductor integrated circuit device and a method of manufacturing the same according to another embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 5, the first electrode 16 is formed after the contact holes 14 and 15 in the first embodiment are filled with the conductor films 23 and 24.

First, as shown in FIG. 6, in a region where a field insulating film for element isolation is formed on the surface of a semiconductor substrate 1 made of, for example, p-type Si single crystal, a second conductivity type for forming a channel stopper is formed. For example, after ion implantation of n-type impurities, a selective region on the surface of the semiconductor substrate 1 is thermally oxidized to form a field insulating film 2 made of a thick silicon oxide film. In this case, the heat treatment diffuses the n-type impurities to form a channel stopper layer (not shown) made of an n-type diffusion layer.

After that, a gate insulating film 3 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1, and then a polycrystalline silicon film containing a conductive impurity is formed on the semiconductor substrate 1 by the CVD method. The gate electrode 4 is formed by selectively removing the polycrystalline silicon film by photolithography.

Next, an n-type impurity is ion-implanted into a region where the surface of the semiconductor substrate 1 is exposed and diffused to form an n-type semiconductor region 5 serving as a source and an n-type semiconductor region 6 serving as a drain. Formed at the same time, a switch MOSFET is manufactured.

In FIG. 6, an n-channel switch M
Although the OSFET is shown, a p-channel switch MOS is provided in a region (not shown) of the semiconductor substrate 1.
FETs are also formed, and those MOSFETs are used to form a CMIS structure.

An insulating film 7 is formed on the semiconductor substrate 1 so as to cover the upper part of the switch MOSFET.

The insulating film 7 is a single layer film made of a silicon oxide film formed by a CVD method or the like, a PSG film which is a silicon oxide film containing phosphorus, or a BPSG film which is a silicon oxide film containing boron and phosphorus. Alternatively, a flattening process is performed after the insulating film 7 is formed of a laminated film in which these are deposited to flatten the surface of the insulating film 7.

The planarization process is performed by reflowing the PSG film or the BPSG film containing a high concentration of phosphorus (P) by heat treatment at a high temperature. As the flattening treatment, it is possible to adopt a mode in which the surface of the insulating film 7 is flattened by an etch back method or a chemical mechanical polishing method.

Next, the insulating film 8 is formed on the insulating film 7.

The insulating film 8 is formed so as to function as an etching stopper film, and a silicon nitride film or an aluminum oxide film formed by the CVD method is used, but a material having an etching rate different from that of the insulating film 7 is used. Other types of insulating films may be used as long as the insulating films are made of.

By performing the flattening process on the insulating film 8, the flattening process on the insulating film 7 can be omitted.
In this embodiment, since the insulating film 7 is flattened, the insulating film 8 is not flattened. That is,
Only one of the insulating film 7 and the insulating film 8 may be flattened, and the surface of the insulating film 8 after the insulating film 7 is formed by the flattening process may be flat.

Next, the openings 9 and 10 are formed in the insulating film 8 by using the photolithography technique using the photoresist film as a mask, and then the insulating film 8 is etched using the insulating film 8 as a mask. By doing so, the contact hole 14 and the contact hole 15 are selectively removed.

The relation between the semiconductor region 5 serving as the source and the semiconductor region 6 serving as the drain is such that the semiconductor region 5 is adopted as the drain and the semiconductor region 6 is adopted as the source. You can

Next, as shown in FIG. 7, the conductive films 23 and 24 are simultaneously buried in the contact holes 14 and 15 by the selective deposition method of tungsten, for example. As a result, according to the second embodiment, the contact holes 14 and 15 can be miniaturized, and the element size can be reduced.

Next, the insulating film 11 is formed on the insulating film 8. The film thickness of the insulating film 11 is the same as the film thickness of the first electrode of the ferroelectric capacitor described later. The insulating film 11 is formed by the same method as the insulating film 7.

Next, using the photolithography technique using the photoresist film as a mask, the insulating film 11 is etched and selectively removed to form the grooves 12 and 13. In this case, the insulating film 8 serves as an etching stopper film.

The trench 12 serves as a region for forming a first electrode of a ferroelectric capacitor described later, and the trench 13 serves as a region of a contact hole on the surface of the conductive film 24, that is, the semiconductor region 6 serving as the first electrode and the drain of the switch MOSFET. This is a region of a contact hole for connecting the data line with. After that, the work of removing the photoresist film that is no longer needed is performed.

Next, as shown in FIG. 3, the groove 12 and the groove 1
The first electrode 16 and the drain electrode 17 are simultaneously formed in such a shape as to bury 3 and are connected to the first electrode of the ferroelectric capacitor and the conductive film 24 by using the first electrode 16 and the drain electrode 17. Contact electrodes are formed.

For the first electrode 16 and the drain electrode 17, platinum deposited by a sputtering method is used,
In order to improve the contact area with the insulating film 11, the film thickness of the first electrode 16 and the drain electrode 17 is made larger than the film thickness of the insulating film 11, and the shape is raised to the surface of the insulating film 11. I am trying.

Next, after a photoresist film or an SOG film is formed on the first electrode 16 and the drain electrode 17, the first electrode 16 and the drain electrode above the surface of the insulating film 11 are etched back. 17 is flattened by etching so that the surfaces of the first electrode 16 and the drain electrode 17 and the surface of the insulating film 11 are aligned with each other. The photoresist film is formed by a spin coating method using a spinner, the SOG film is made of silicon oxide formed by a spin coating method using a spinner, and after the formation, the photoresist film is formed. Alternatively, even if the shape under the SOG film is uneven, it has a flat surface.

In the flattening process of the first electrode 16 and the drain electrode 17, the first electrode 16 above the surface of the insulating film 11 is formed by the chemical mechanical polishing method.
Alternatively, a method of etching and flattening the drain electrode 17 can be adopted.

Next, as shown in FIG. 9, the first electrode 16
A ferroelectric film 18 is deposited on the semiconductor substrate 1 including the drain electrode 17. The ferroelectric film 18 uses PZT or the like formed by a CVD method, a sputtering method, a sol-gel method, or the like. Since the surfaces of the first electrode 16 and the drain electrode 17 are flattened, the ferroelectric film 18 is formed at the end portions of the first electrode 16 and the drain electrode 17.
Is not formed.

Next, a second electrode 19 which will be the second electrode of the ferroelectric capacitor is formed. It is not necessary to use platinum or the like described above for the second electrode 19, and a material such as titanium that is easy to perform fine processing can be used.

Next, the second electrode 19 and the ferroelectric film 18 are sequentially etched by using a photolithography technique using a photoresist film as a mask, whereby the ferroelectric capacitor can be formed.

In this case, the second electrode 19 and the ferroelectric film 18 on the first drain electrode 17 connected to the data line described later are removed. After that, the work of removing the photoresist film that is no longer needed is performed.

Next, as shown in FIG. 10, an insulating film 20 is deposited on the ferroelectric capacitor.

As the insulating film 20, a single layer film of a silicon oxide film or a silicon nitride film formed by a sputtering method or a plasma CVD method or a laminated film in which these are deposited is adopted.

Through holes 2 are formed in the insulating film 20 by using a photolithography technique using a photoresist film as a mask.
1 is formed.

Next, after removing the photoresist film, a third conductive film 22 to be a data line is deposited. Third
As the conductive film 22 of, a single layer film of aluminum, titanium, tungsten or the like formed by a sputtering method or a CVD method or a laminated film in which these are deposited is adopted.

Next, the third conductive film 22 is selectively etched by the photolithography technique using the photoresist film as a mask to form a wiring pattern having a predetermined shape. After that, the work of removing the photoresist film that is no longer needed is performed.

Next, although not shown, a wiring layer and a passivation film above the passivation film or the third conductive film 22 are formed, the passivation film is selectively removed, and a bonding pad is formed in that region. A semiconductor integrated circuit device is manufactured by forming the semiconductor integrated circuit device.

(Embodiment 3) As shown in FIG. 11, a semiconductor integrated circuit device and a method of manufacturing the same according to another embodiment of the present invention, as shown in FIG.
After the formation of the film, it is left as it is without performing the etching process, and the second film is selectively formed on a part of the surface of the ferroelectric film 18.
It is characterized in that a plurality of electrodes 19 are formed.

Ferroelectric film 1 in ferroelectric capacitor
Since the etching process for patterning 8 is not performed, the step of patterning the ferroelectric film can be omitted, and the step portion of the ferroelectric film 18 is not formed, and the deterioration of the film quality can be prevented. it can.

Since the other steps are the same as the manufacturing steps of the semiconductor integrated circuit device in the first embodiment described above,
Description is omitted.

(Embodiment 4) As shown in FIG. 12, a semiconductor integrated circuit device and a method of manufacturing the same according to another embodiment of the present invention, as shown in FIG. Non-volatile RAM connected to body capacitors and DRAM (Dynamic Random Access Mem
a non-volatile RAM in which one ferroelectric capacitor is connected to one switch MOSFET having the same structure as that of the above-mentioned (mory) is formed on the same semiconductor substrate 1.

In FIG. 12, the DRA is shown on the right side.
It is a nonvolatile RAM in which one switch MOSFET having the same structure as M is connected to one ferroelectric capacitor. In the figure, 25 is the same structure as the DRAM 1
It is a semiconductor region that serves as a source in one switch MOSFET. Reference numeral 26 is a first electrode in the ferroelectric capacitor, which is connected to the semiconductor region 25. 27 is a ferroelectric film of the ferroelectric capacitor. 28 is a second electrode of the ferroelectric capacitor.

Other than that, the structure and the manufacturing process thereof are the same as those of the semiconductor integrated circuit device in the first embodiment described above, and therefore the description thereof is omitted.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0114]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, for example, the first electrode is a single layer film made of platinum, which is difficult to process, or a laminated film made of platinum on the surface portion of the first electrode. However, since the first electrode can be patterned into a shape corresponding to the groove without etching by embedding the first electrode in the groove that can be provided in the second insulating film by fine processing, Since the shape and size of the first electrode can be defined by the shape and size of the fine pattern provided in the second insulating film, the ferroelectric capacitor can be highly integrated in a small area by fine processing. It can be provided in the state.

Further, the first electrode having a flat surface which is flush with the surface of the second insulating film, and the strong electrode provided on the first electrode. Since the ferroelectric capacitor includes a dielectric film and a second electrode provided on the ferroelectric film, the first capacitor in contact with the second insulating film can be obtained.
Since the electrode has no step, the ferroelectric film provided on the first electrode is also provided without a step, so that the deterioration of the film quality of the ferroelectric film is suppressed and the characteristics are excellent. It is possible to provide the ferroelectric capacitor.

(2) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after the first conductive film is embedded in the first groove and the second groove, the second conductive film is formed into the second conductive film. Forming the first electrode having a surface flush with the surface of the insulating film, and forming a ferroelectric film on the first electrode embedded in the first groove. After doing
By forming a second conductive film on the ferroelectric film, the first electrode is a single layer film made of platinum which is difficult to process, or the surface portion of the first electrode is made of platinum. Even when using a laminated film of the above, the first electrode is embedded in the first groove that can be formed in the second insulating film by microfabrication.
Since it can be patterned with a shape and dimensions corresponding to the first groove without etching the electrode of
Since the shape and size of the first electrode can be defined by the shape and size of the fine pattern provided on the second insulating film, the ferroelectric capacitor can be highly integrated in a small area by fine processing. It can be manufactured in the state of.

Further, the first electrode having a flat surface which is flush with the surface of the second insulating film, and the ferroelectric formed on the first electrode. The first electrode that is in contact with the second insulating film because it is a ferroelectric capacitor including a body film and a second electrode formed on the ferroelectric film. Can be formed without a step, so that the ferroelectric film formed on the first electrode can also be formed without a step, the deterioration of the film quality of the ferroelectric film can be suppressed, and the characteristics are excellent. The ferroelectric capacitor can be formed.

Furthermore, as the first insulating film,
By using a silicon oxide film or a silicon nitride film made of a material different from that of the insulating film and the second insulating film, the first groove and the second groove are formed in the second insulating film. At this time, since the first insulating film can function as an etching stopper film, fine processing can be performed and an easy manufacturing process can be adopted.

(3) According to the above (1) and (2), a semiconductor integrated circuit device such as a nonvolatile RAM provided with a highly integrated ferroelectric capacitor having high characteristics and high reliability is provided. In addition to being able to do so, it is possible to provide a manufacturing technique that can easily manufacture it.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 semiconductor region 6 semiconductor region 7 insulating film (first insulating film) 8 insulating film (second insulating film) 9 opening 10 opening 11 insulating film ( Third insulating film) 12 groove 13 groove 14 contact hole 15 contact hole 16 first electrode 17 drain electrode 18 ferroelectric film 19 second electrode 20 insulating film 21 through hole 22 third conductive film 23 conductive film 24 Conductive film 25 Semiconductor region 26 First electrode 27 Ferroelectric film 28 Second electrode C Ferroelectric capacitor

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 21/8242 27/108 21/8247 29/788 29/792 H01L 29/78 371

Claims (9)

[Claims] 1. A switch MISFET including a semiconductor region serving as a source and a semiconductor region serving as a drain, which are provided in a semiconductor substrate, and a semiconductor region serving as the source or the semiconductor serving as the drain in the switch MISFET. A first electrode that is connected to either one of the regions and that is provided on the surface of the first insulating film that has a flat surface; and a first electrode that has a flat surface and that is provided on the first electrode. A ferroelectric capacitor composed of a ferroelectric film and a second electrode provided on the ferroelectric film, and arranged in a selective region on the first insulating film. And a second insulating film which is provided in contact with the sidewall of the first electrode and has a surface flush with the surface of the first electrode. Half Body integrated circuit device. 2. A switch MISFET having a semiconductor region serving as a source and a semiconductor region serving as a drain provided on a semiconductor substrate, and a semiconductor region serving as the source or the semiconductor region serving as the drain in the switch MISFET. A first electrode having a flat surface provided on the surface of a first insulating film having a flat surface, and a strong electrode provided on the first electrode. A ferroelectric capacitor composed of a dielectric film and a plurality of second electrodes provided in selective regions on the ferroelectric film; and a ferroelectric capacitor on the first insulating film. A second insulating film, which is arranged in a selective region, is provided in contact with the sidewall of the first electrode, and has a surface flush with the surface of the first electrode. ing The semiconductor integrated circuit device according to claim and. 3. A switch MISFET having a semiconductor region serving as a source and a semiconductor region serving as a drain provided in a semiconductor substrate, and a semiconductor region serving as the source or the semiconductor serving as the drain in the switch MISFET. A first electrode having a flat surface provided on the surface of a first insulating film having a flat surface, which is connected to either one of the regions; and a selective region on the first electrode. A ferroelectric capacitor including a plurality of ferroelectric films provided on the plurality of ferroelectric films and a plurality of second electrodes provided on the plurality of ferroelectric films, respectively; It has a surface that is arranged in a selective region on the first insulating film, is provided in contact with the side wall of the first electrode, and is flush with the surface of the first electrode. You The semiconductor integrated circuit device, characterized in that a second insulating film. 4. The ferroelectric capacitor connected to one of the semiconductor region serving as the source and the semiconductor region serving as the drain in the switch MISFET, and the ferroelectric capacitor is not connected. A wiring film connected to either one of the semiconductor region serving as the source or the semiconductor region serving as the drain, which is provided on the second electrode via a third insulating film. 4. The semiconductor integrated circuit device according to claim 1, further comprising a third conductive film. 5. The first electrode is a single-layer film made of platinum or a laminated film made of platinum on the surface of the first electrode. 4. The semiconductor integrated circuit device according to 4. 6. A semiconductor region serving as a source and a semiconductor region serving as a drain are simultaneously formed on a semiconductor substrate, and a switch MISFET having the semiconductor region serving as the source and the semiconductor region serving as the drain as constituent elements is formed. A step of forming a first insulating film on the semiconductor substrate including the switch MISFET, a step of flattening a surface of the first insulating film, and a step of forming a first insulating film on the first insulating film. Forming a second insulating film, and forming a first groove and a second groove in a selective region of the second insulating film.
Forming a groove of the first groove, and forming the groove of the first groove in the lower part of the first groove.
Forming a first contact hole which is a contact region of either the semiconductor region serving as the source or the semiconductor region serving as the drain in a part of the insulating film of Forming a second contact hole in a part of the first insulating film to be a contact region of either the semiconductor region to be the source or the semiconductor region to be the drain; and the first contact hole After filling the second contact hole, the first groove and the second groove with the first conductive film, the second conductive film is used to form the second conductive film.
Forming the first electrode having a surface flush with the surface of the insulating film, and forming a ferroelectric film on the first electrode embedded in the first groove. And a step of forming a second conductive film on the ferroelectric film, the method for manufacturing a semiconductor integrated circuit device. 7. A semiconductor region serving as a source and a semiconductor region serving as a drain are simultaneously formed on a semiconductor substrate, and a switch MISFET having the semiconductor region serving as the source and the semiconductor region serving as the drain as constituent elements is formed. A step of forming a first insulating film on the semiconductor substrate including the switch MISFET, a step of flattening a surface of the first insulating film, and a step of forming a first insulating film on the first insulating film. Forming a second insulating film, and forming a first groove and a second groove in a selective region of the second insulating film.
Forming a groove of the first groove, and forming the groove of the first groove in the lower part of the first groove.
Forming a first contact hole which is a contact region of either the semiconductor region serving as the source or the semiconductor region serving as the drain in a part of the insulating film of Forming a second contact hole in a part of the first insulating film to be a contact region of either the semiconductor region to be the source or the semiconductor region to be the drain; and the first contact hole After filling the second contact hole, the first groove and the second groove with the first conductive film, the second conductive film is used to form the second conductive film.
Forming the first electrode having a surface flush with the surface of the insulating film, and forming a ferroelectric film on the first electrode embedded in the first groove. And then forming a second conductive film on the ferroelectric film, and selectively removing the second conductive film to form a plurality of second electrodes. A method of manufacturing a semiconductor integrated circuit device having a feature. 8. When forming the first electrode having a surface flush with the surface of the second insulating film,
8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the surface of the first conductive film is polished by a chemical mechanical polishing method. 9. The silicon oxide film or the silicon nitride film made of a material different from that of the insulating film and the second insulating film is used as the first insulating film. 7. A method for manufacturing a semiconductor integrated circuit device according to 7 or 8.