JPH0822413A - Information processor - Google Patents

Abstract

PURPOSE:To provide the information processor which is reduced in power consumption without any decrease in processing speed. CONSTITUTION:An instruction buffer for making an advanced read of an instruction is incorporated in a central processor 100. Plural memory banks 130 and 150 are composed of RAMs 120 and 140 which differ in power consumption and data are stored in the memory banks, one by one, in order from the memory bank with large power consumption. When the memory bank 130 having the larger power consumption between the memory banks 130 and 150 is accessed, the data stored in the other memory bank 150 are accessed by a memory control means 110 at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for reducing power consumption of an information processing apparatus, and more particularly to power saving when a memory is accessed by a central processing unit.

[0002]

2. Description of the Related Art In recent years, the portability of information processing apparatuses has become an important factor as the size of the information processing apparatuses has been reduced. In that case, it is necessary to reduce the power consumption of the information processing device as much as possible in order to extend the operation time when the battery is used. On the other hand, focusing only on reducing the power consumption of the information processing device causes a decrease in processing speed, which is not desirable.

Therefore, in a conventional information processing apparatus, as disclosed in Japanese Patent Laid-Open No. 230508/1992, a first memory that consumes normal power and a second memory that consumes less power are used to access. By storing frequently-used data in the normal first memory and turning off the power of the second memory, the power consumption of the memory is suppressed, and thus the power consumption of the information processing device is reduced.

[0004]

However, in the conventional technique, since the frequently accessed data is stored in the first memory, the memory is accessed only to the first memory. In this case, even if the power to the second memory that is not accessed is turned off, the power consumption in the memory is not so much because the power consumed when accessing the memory is the majority of the power consumption in the memory. We couldn't save much power.

In view of the above problems, it is an object of the present invention to provide an information processing apparatus that reduces power consumption without causing a reduction in processing speed.

[0006]

In order to achieve the above object, according to the invention of claim 1, a central processing unit having a built-in instruction buffer for prefetching an instruction and a plurality of RAMs having different power consumptions. A plurality of memory banks each configured to store data one by one in order from the memory bank with the highest power consumption, and the memory bank with the highest power consumption among the memory banks. Memory access means for simultaneously accessing data stored in the other memory banks when the above access is performed.

According to a second aspect of the present invention, the central processing unit further simultaneously outputs storable information indicating the number of instruction words that can be stored in the instruction buffer when reading an instruction, and the memory control means Further, when the instruction cannot be stored in the instruction buffer based on the storable information, the simultaneous access to the plurality of memory banks is prohibited.

According to a third aspect of the present invention, an instruction buffer for prefetching an instruction is built in, and when the instruction is read, storable information indicating the number of instruction words that can be stored in the instruction buffer is simultaneously output. Central processing unit, a first memory bank that is composed of a RAM that consumes normal power and stores data of an even or odd type of address, and a RAM that consumes less power than the first memory bank Is even or odd and the first
A second memory bank for storing data of an address other than the one stored in the memory bank, and the memory control means, wherein the memory control means provides an address for accessing the second memory bank. An address holding unit for holding, an instruction holding unit for holding an instruction read from the second memory bank, and an address accessed by the central processing unit, if the address holding unit stores it, holds it from the instruction holding unit. Read the specified instruction and access the first memory bank, and if the instruction can be stored in the instruction buffer based on the storable information, the second memory bank is simultaneously accessed and the second memory bank is accessed. While reading an instruction from, it is not contiguous with the address of the instruction currently being read and is not stored in the first memory bank. When the address is accessed, the reading from the second memory bank is continued, and after the reading from the second memory bank is completed, a control unit that stores the read instruction in the instruction holding unit is provided. To do.

According to another aspect of the present invention, there is provided a memory storing an instruction and a central processing unit for accessing the memory, wherein the access is an unconditional branch instruction whose branch destination can be specified. Using the central processing unit that outputs access attribute information indicating whether or not the memory is accessed, and the access control information and the instruction read from the memory, the central processing unit outputs an unconditional branch instruction from the memory. Memory control means for interrupting access to the memory after reading is performed until execution of an unconditional branch instruction is performed.

[0010]

According to the above structure, in the invention of claim 1, the instruction buffer for prefetching an instruction is built in the central processing unit. Multiple RAMs with different power consumption
Data is stored in the plurality of memory banks one by one in order of increasing power consumption. When access is made to the memory bank with the highest power consumption among the memory banks, the data stored in the other memory banks are simultaneously accessed by the memory control means.

According to a second aspect of the present invention, the central processing unit further simultaneously outputs storable information indicating the number of instruction words that can be stored in the instruction buffer when reading an instruction, and the memory control means. Further, when the instruction cannot be stored in the instruction buffer based on the storable information, the simultaneous access to the plurality of memory banks is prohibited.

According to the third aspect of the present invention, the instruction buffer for prefetching an instruction is built in the central processing unit and can be stored indicating the number of instruction words that can be stored in the instruction buffer when the instruction is read. The information is output simultaneously by the central processing unit. R that consumes normal power
In the first memory bank configured by AM, the data of the address of either even number or odd number is stored in the first
Stored by memory bank. A second memory bank configured by a RAM that consumes less power than the first memory bank, the first memory bank being an even number or an odd number.
Data of addresses other than those stored in the second memory bank are stored in the second memory bank. The memory control means is composed of an address holding unit, a data holding unit, and a control unit. The address for accessing the second memory bank is held by the address holding unit.
The instruction read from the second memory bank is held by the instruction holding unit. When the address accessed by the central processing unit is stored in the address holding unit, the central processing unit reads the instruction held in the instruction holding unit. , When the first memory bank is accessed and the instruction can be stored in the instruction buffer based on the storable information, the central processing unit simultaneously accesses the second memory bank. If the address of the instruction currently being read is not consecutive and the address stored in the first memory bank is accessed while the instruction is being read from the second memory bank, the second memory After the reading from the bank is continued and the reading from the second memory bank is completed, the read instruction is stored in the instruction holding unit by the control unit.

In the invention of claim 4, the instructions are stored in the memory. A central processing unit that accesses the memory, the access attribute information indicating whether the access is due to execution of an unconditional branch instruction that is an instruction whose branch destination can be specified. Output by. Using the access control information and the instruction read from the memory, the central processing unit reads the unconditional branch instruction from the memory until the execution of the unconditional branch instruction, access to the memory, It is interrupted by the memory control means.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an information processing apparatus according to the first embodiment of the present invention. This diagram includes a CPU 100, a memory control circuit 110, a memory bank 130, and a memory bank 150.

The CPU 100 is a central processing unit,
It has an internal instruction buffer so that instruction fetch can be performed prior to instruction execution. This instruction buffer contains
Up to two fetched instructions can be stored. Further, when accessing the memory for fetching an instruction, the CPU 100 outputs the address of the instruction to be fetched to the memory control circuit 110 through the address bus 101 and simultaneously outputs a control signal through the control signal line 103. Output to 110. Here, the control signal is a signal indicating the number of instruction words that can be stored in the instruction buffer, and is represented by Hi and Lo. One for Hi, Lo
In case of, it means that two instruction buffers can be stored. The fetched instruction is received from the memory control circuit 110 through the data bus 102 and stored in the instruction buffer. Further, the address bus 101, the control signal line 103, and the data bus 102 have the same bit width (hereinafter, this bit width is referred to as a word).

The memory bank 130 is a memory bank implemented by the RAM 120 and stores data of even word addresses having even addresses. R
The AM 120 is a RAM that operates with normal power consumption, and is a time corresponding to one cycle time such as C1, C2, ... You can read the data with.

The memory bank 150 is a memory bank implemented by the RAM 140, and stores data of odd word addresses whose addresses are odd. R
The AM 140 is a RAM that operates with less power consumption than the RAM 120, and as shown in FIG.
The data can be read in a time corresponding to two cycle times such as.

The memory control circuit 110 follows the memory access from the CPU 100 to the memory bank 130,
The memory bank 150 is accessed and data is read. Specifically, it is shown in the control flow chart of FIG. First, it is determined whether the address accessed by the CPU 100 is an even word address (step S8).
01-step S802). The address accessed by the CPU 100 is an even word address, and CP
If the control signal received from the U100 through the control signal line 103 is Lo, the memory banks 130 and 150 are accessed, and then the data is read from the memory bank 130 (steps S803 to S806). Here, access to the memory bank 130 is realized by sending an address value received from the CPU 100 through the address bus 101 through the address bus 111 and sending a control signal through the control line 114. Similarly, access to the memory bank 150 is realized by sending the value of the address received from the CPU 100 through the address bus 101 through the address bus 111 and sending the control signal through the control line 115. Data is read from the memory bank 130 via the data bus 112. The address accessed by the CPU 100 is an even word address, and the CPU
If the control signal received from 100 is Hi, only memory bank 130 is accessed and then memory bank 130 is accessed.
Data is read from (step S807, step S
808). On the other hand, if the address accessed by the CPU 100 is an odd word address and is continuous with the address of the instruction previously read by the CPU 100, data is read from the memory bank 150 (step S809,
Step S810). Here, reading of data from the memory bank 130 is performed through the data bus 112. If the address accessed by the CPU 100 is an odd word address and is not the address next to the address of the instruction previously read by the CPU 100, the memory bank 150 is accessed, and then the data is read from the memory bank 150 (steps S811 to S81).
3).

The operation of the information processing apparatus configured as described above when the CPU 100 accesses the memory banks 130 and 150 will be described with reference to timing charts 2 and 3. FIG. 2 is a timing chart showing the operation when the CPU 100 accesses continuous data from even word addresses.

In cycle C1, since the address output by the CPU 100 is an even word address (N) and the control signal line 103 is Lo, the memory bank 130
And access the memory bank 150. With respect to the memory bank 130, access is completed within one cycle time, and data is read. The memory bank 150 has a low access speed, and the access is not completed in one cycle and continues to the next cycle.

In cycle C2, the address output by the CPU 100 is an odd word address (N + 1),
Further, since it is continuous with the address read by the CPU 100 the previous time (cycle C1), the data is read from the memory bank 150. In this cycle, memory bank 1
No access is made to 30. In cycle C3,
Since the address output by the CPU 100 is an even word address (N + 2) and the control signal line 103 is Lo, the same operation is performed in the cycle C1.

In cycle C4, the address output by the CPU 100 is an odd word address (N + 3) and is continuous with the address read by the CPU 100 the previous time (cycle C3), so the same operation as in cycle C2 is performed. In cycle C5, since the address output by the CPU 100 is an even word address (N + 4) and the control signal line 103 is not Lo, the memory bank 130 is accessed. With respect to the memory bank 130, access is completed within one cycle time, and data is read.

Therefore, the average power consumption in the case of continuous access from an even address is represented by the power consumption of the accessed memory bank.
Power consumption + memory bank 150 power consumption) / 2. Therefore, the power consumption is lower than when only the memory bank 130 is accessed.

Next, FIG. 3 is a timing chart showing the operation when the CPU 100 accesses continuous data from odd word addresses. In cycle C1, since the address output by the CPU 100 is an odd word address (N + 1) and is not continuous with the address read by the CPU 100 last time, the memory bank 1
Access only 50. Memory bank 150
For, the access does not end in one cycle and continues to the next cycle.

In cycle C2, access to the memory bank 150 is completed in two cycles, and the data read in this cycle is read. In cycle C3, CPU1
The address output by 00 is an even word address (N +
2) and the control signal line 103 is Lo,
The operation after this cycle is the same as when the CPU 100 accesses continuous data from the even word address.

Therefore, the power consumption of the memory when the continuous access is performed from the odd word address is the same as that when the continuous access is performed from the even word address. In this embodiment, the RAM 140 has a lower power consumption than the RAM 120, but the same memory as the RAM 120 may be used to reduce the power consumption by reducing the power supply voltage.

In this embodiment, there are two types of memory banks, that is, the memory bank 130 and the memory bank 150. However, the number of memory banks is not limited to two, and a plurality of RAMs each having different power consumption may be used. There may be a memory bank. In this case, data is stored in each of these memory banks in order from the memory bank with the largest power consumption. Then, the memory control circuit 110 is configured to simultaneously access the data stored in the other memory banks when the memory bank with the largest power consumption among the memory banks is accessed.

As described above, according to this embodiment, the memory bank 130 and the memory bank 150 which consumes less power than the memory bank 130 are provided, and the access to the memory bank 150 is started in parallel with the access to the memory bank 130. By doing so, it is possible to read from the memory without degrading the performance, and it is possible to reduce the power consumption by using the memory bank 150 more efficiently than when accessing only the memory bank 130. . Further, by using the control signal line 103, excessive preceding access can be prohibited, and power consumption due to unnecessary memory access can be reduced.

FIG. 4 shows the configuration of the information processing apparatus in the second embodiment of the present invention. This figure shows the CPU 10
0, a memory control circuit 410, a memory bank 130, and a memory bank 150. Since the constituent elements in this figure are almost the same as those in FIG. 1, only different points will be described. The difference is that a memory control circuit 410 is provided instead of the memory control circuit 110 in the first embodiment, and an address bus 414 and an address bus 416 are provided instead of the address bus 111 in the first embodiment. It is a point.

As shown in FIG. 6, the memory control circuit 410 includes a control circuit 200, a comparison circuit 201, latches 202, 203, 204 and 206, and tri-state buffers 210, 211, 212, 213 and 214. 21
5, 216 and a selector 205.
The comparison circuit 201 is configured to compare the address (excluding the least significant bit) stored in the latch 202 with the address bus 10.
The address sent from 1 (excluding the least significant bit) is compared to determine whether they match.

The control circuit 200 performs access to the memory bank 130 and the memory bank 150 and reading of data by controlling each part of the memory control circuit 410 except the control circuit 200 in accordance with the memory access from the CPU 100. . Further, the control circuit 200 is
It has a status flag 230 inside. The status flag 230 is a flag indicating that the address and data are held in the latches 202 and 204. Specific control contents of the control circuit 200 are shown in the control flows of FIGS. 9 and 10. First, it is determined whether the state flag 230 is set when the CPU accesses the memory (steps S901 and S902). If the status flag 230 is not set, it is next determined whether or not the odd address is being accessed (step S906). If the odd address is not currently being accessed, the current address bus 101
Determines whether the address is an even word address (step S912). If the address indicated by the current address bus 101 is an even address, the same process as the process 1 of FIG. 8 is performed (step S913), and the memory bank 15
When accessing 0, the odd word address is stored in the latch 202/206 (step S914). In step S912, the address indicated by the address bus 101 is an odd address, and the CPU1
If 00 continues to the previously accessed address (step S915), the data is read from the memory bank 150 (step S916). In step S912, if the address indicated by the address bus 101 is an odd address and is not the address next to the address accessed by the CPU 100 last time, the memory bank 1
50 to read data (step S91)
7-step S919). In step S906,
If the odd address is currently being accessed, it is further determined that the address indicated by the address bus 101 is an even address and is not the address next to the address currently being accessed (steps S907 and S908). If the address indicated by the address bus 101 is not an even address or is continuous with the address currently being accessed, the process returns to step S906, and the loop is repeated until the state changes. If the address indicated by the address bus 101 is an even address and is not the address next to the address currently being accessed, the memory bank 130 is accessed (step S909),
Further, data is read from the memory bank 150 and stored in the latch 204 (step S
910). Then, the status flag 230 is set (step S911). If the status flag 230 is set in step S902, then the comparison circuit 20
1, the address indicated by the address bus 101 and the latch 20
2 is compared with the address held by 2 while ignoring the least significant bit (step S903). If they do not match, the process proceeds to step S906. Output and clear the status flag 230 (step S904, step S904
905).

The operation of the information processing apparatus configured as described above when the CPU 100 accesses the memory banks 130 and 150 will be described with reference to timing charts. Here, when the continuous data is accessed, the description is omitted because it is the same as that in FIGS. 2 and 3 described in the first embodiment, and when the continuous access to the instruction is performed,
A case where data at another address is accessed will be described with reference to the timing chart shown in FIG.

In cycle C1, since the address output by the CPU 100 is an even word address (N) and the control signal line 103 is Lo, the memory bank 130
In addition to accessing the memory bank 150, the address accessing the memory bank 150 is stored in the latch 202 and the latch 206. In cycle C2, the CPU 100 outputs the even word address (M) prior to the access to the instruction of the odd word address (N + 1) in this cycle, and thus starts reading the data of the even word address (M). This means that the memory bank 150 is read in parallel (cycle C
1) The address held in the latch 206 is sent, and reading is continued. Although the access to the two memory banks ends in this cycle, the data of the odd word address (N + 1) read from the memory bank 150 is stored in the latch 204 and the latch 202.
And state flag 230, which indicates that the address and data are held in 204.

In cycle C3, since the status flag 230 is set, the comparison circuit 201 causes the latch 20 to operate.
In the cycle C1 held in 2, the odd-numbered word address accessed by the CPU 100 in the memory bank 150 and the address indicated by the address bus 101 are compared with each other by ignoring the least significant bit. Is not accessed, and the data is read from the latch 204.

Since the cycle C4 and the subsequent steps are the same as the cycle C1 and the cycle C2 of the timing chart shown in FIG. 2 in the first embodiment, the description thereof will be omitted. As described above, according to the present embodiment, by providing the latch 204 in the memory control circuit 410, even when the memory bank 130 is accessed after the preceding access to the memory bank 150 is started, the read data is read. Since it is not wasted, the power consumption can be suppressed.

FIG. 7 shows the configuration of the information processing apparatus in the third embodiment of the present invention. This figure shows the CPU 30
0, a memory 310, and a memory control circuit 320. The CPU 300 is a central processing unit (CPU) having a fixed length instruction format, and has an internal instruction buffer so that instruction fetch can be performed prior to execution of an instruction. This instruction buffer can store a plurality of instructions that have been read in advance, and when the CPU 300 executes a branch instruction and branches, all the stored instructions are C
Discard according to the instruction of PU300. When accessing the memory to fetch the instruction, the address of the instruction to be fetched is stored in the memory 3 via the address bus 301.
At the same time, the access attribute information is output to the memory control circuit 320 via the control line 302, and the control information is output to the memory control circuit 320 via the control line 303. Here, the access attribute information is the CPU 300.
It is information indicating whether the access to the memory 310 by is an access by executing an unconditional branch instruction whose branch destination can be specified. The control information is information for selecting a memory chip used in the memory 310 and starting an operation. Next, the fetched instruction is received through the data bus 304 and stored in the instruction buffer.
The bit width of the data bus 304 is a multiple of the instruction length of the CPU 300.

The memory 310 is a memory controlled by the memory control circuit 320. The memory control circuit 320 includes a permission flag control circuit 330 and a memory access permission flag 3.
40, a control circuit 350, and a decoder 360. The memory access permission flag 340 is a flag indicating that the memory can be accessed when this flag is set. It is assumed that the flag is set in the initial state.

The decoder 360 determines whether the instruction read by the CPU 300 is an unconditional branch instruction. If it is an unconditional branch instruction, a signal indicating that the memory access permission flag 340 should be cleared is sent to the permission flag control circuit 330 through the control line 322. The permission flag control circuit 330 clears the memory access permission flag 340 when receiving a signal from the decoder 360 to clear the memory access permission flag 340. Also,
The access attribute information is received from the CPU 300 through the control line 302, and if the information is the access by executing the unconditional branch instruction, the memory access permission flag 340 is set.

The control circuit 350 controls the access from the CPU 300 to the memory 310 by referring to the memory access permission flag 340. Specifically, FIG.
Is shown in the control flow. First, it is determined whether the CPU 300 has accessed the memory 310 by fetching an instruction (step S111). If the access is being performed, it is further determined from the access attribute information received from the CPU 300 whether the access is an unconditional branch instruction or the memory access permission flag 340 is set (step S112,
Step S113). If the access is an access by an unconditional branch instruction or the memory access permission flag 340 is set, the instruction is read from the memory 310 by the access (step S11).
5). If the access is an unconditional branch instruction and the permission flag is not set, the access ends the bus cycle without reading the memory (step S114).

As described above, according to this embodiment, when an unconditional branch instruction is fetched from the memory, the memory access permission flag 340 is executed until the branch destination instruction is fetched by executing the new unconditional branch destination instruction. Reset,
After that, when the memory access permission flag 340 is reset, by prohibiting the memory control circuit 320 from accessing the memory, it is possible to prohibit unnecessary memory access for the processing of the CPU 300, and to maintain the memory in a low power consumption state. Power can be suppressed. In addition, the memory control circuit 32 detects the unconditional branch instruction prior to the CPU 300.
Since it is 0, control can be performed at an earlier stage than fetch control in the CPU, and more power consumption can be suppressed.

In this embodiment, the central processing unit having a fixed length instruction is used, but the memory control circuit 320 decodes the instruction format so that the central processing unit also has a variable length instruction format. It is possible.

[0042]

As described above, according to claim 1 of the present invention,
By concurrently accessing a plurality of memory banks configured for each of a plurality of RAMs having different power consumptions, it is possible to provide an information processing device that reduces the power consumptions without lowering the processing speed. According to the second aspect of the present invention, the central processing unit outputs the storable information when the instruction is read out, and the memory control means prohibits the simultaneous access to the memory bank based on it, thereby avoiding unnecessary memory access. By prohibiting it, the power consumption of the information processing device can be reduced without lowering the processing speed.

According to the third aspect of the present invention, the memory control means is provided with the address holding section, the instruction holding section and the control section, so that the first section is provided while the instruction is being read from the second memory bank. Even if the memory bank is accessed, the read data is not wasted, so unnecessary access can be avoided, and the power consumption of the information processing device can be reduced without lowering the processing speed. be able to.

According to the fourth aspect of the present invention, after the unconditional branch instruction is read from the memory, the central processing unit performs the fetching of the branch destination instruction by the execution of the unconditional branch instruction in the central processing unit. Since the access is stopped, it is possible to reduce the power consumption of the information processing device without inhibiting the processing speed by prohibiting the unnecessary access.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an information processing apparatus according to a first embodiment.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is a configuration diagram of an information processing apparatus according to a second embodiment.

FIG. 5 is a timing chart showing the operation of the second embodiment.

FIG. 6 is a configuration diagram of a memory control circuit according to a second embodiment.

FIG. 7 is a block diagram of an information processing apparatus in a third embodiment.

FIG. 8 is a flowchart showing the control contents of the memory control circuit 110 in the first embodiment.

FIG. 9 is a flowchart showing the control contents of the control circuit 200 in the second embodiment.

FIG. 10 is a continuation of FIG. 9;

FIG. 11 is a flowchart showing the control contents of the control circuit 350 in the third embodiment.

[Explanation of symbols]

 100 CPU 110 memory control circuit 120 RAM 130 memory bank 140 RAM 150 memory bank 410 memory control circuit 200 control circuit 201 comparison circuit 230 status flag 300 CPU 310 memory 320 memory control circuit 330 permission flag control circuit 340 memory access permission flag 350 control circuit 360 decoder

Claims (4)

[Claims] 1. A central processing unit having a built-in instruction buffer for prefetching instructions, and a plurality of memory banks configured for each of a plurality of RAMs having different power consumption, the memory having a large power consumption. A plurality of memory banks in which data is stored in order from the bank, and when the memory bank with the highest power consumption among the memory banks is accessed, the data is stored in the other memory banks. An information processing apparatus, comprising: a memory control unit for simultaneously accessing existing data. 2. The central processing unit further outputs storable information indicating the number of instruction words that can be stored in the instruction buffer at the same time when the instruction is read, and the memory control unit further stores the storable information. 2. The information processing apparatus according to claim 1, wherein simultaneous access to the plurality of memory banks is prohibited when an instruction cannot be stored in the instruction buffer based on information. 3. A central processing unit having a built-in instruction buffer for prefetching an instruction and simultaneously outputting storable information indicating the number of instruction words that can be stored in the instruction buffer when the instruction is read. A first memory bank configured by a RAM that consumes normal power and storing data of an even or odd type of address; and a RAM that consumes less power than the first memory bank
A second memory bank configured to store even-numbered or odd-numbered data of an address other than that stored in the first memory bank, and memory control means, wherein the memory control means comprises: An address holding unit holding an address for accessing the second memory bank, an instruction holding unit for holding an instruction read from the second memory bank, and an address accessed by the central processing unit are stored in the address holding unit. If the stored instruction is read from the instruction storage unit and the first memory bank is accessed, and if the instruction can be stored in the instruction buffer based on the storable information, the second memory bank , While simultaneously reading the instructions from the second memory bank,
If the address of the instruction currently being read is not consecutive and the address stored in the first memory bank is accessed, the reading from the second memory bank is continued and the instruction from the second memory bank is continued. After reading,
An information processing apparatus, comprising: a control unit that stores a read instruction in an instruction holding unit. 4. A memory that stores instructions and a central processing unit that accesses the memory, and indicates whether the access is due to execution of an unconditional branch instruction whose branch destination can be specified. After the central processing unit reads the unconditional branch instruction from the memory using the central processing unit that outputs access attribute information when accessing the memory and the access control information and the instruction read from the memory An information processing device, comprising: a memory control unit that suspends access to the memory until execution of an unconditional branch instruction.