JPH08223240A - Frequency offset compensation circuit - Google Patents

Abstract

PURPOSE: To allow a frequency offset compensation circuit compensating automatically a frequency error between transmission and reception of a digital signal to attain frequency offset compensation for an MLSE equalizer with high accuracy at a high speed. CONSTITUTION: The circuit is made up of a correlation detector 2 that stores a known transmission signal over a time N, provides a phase rotation to an output signal by a frequency offset, multiplies the result with a reception signal corresponding to the output signal and integrates the output signal over a time N, a frequency offset estimate device 3 that detects a change in a square sum of output signals of the correlation detector 2 with respect to phase fluctuation within a time caused by the frequency offset, that updates the estimated phase fluctuation so that the square sum is maximized and estimates the phase fluctuation within a time, and a phase compensation section 4 that eliminates the frequency offset of the reception signal based on the phase fluctuation within a time being an output of the frequency offset estimate device 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset compensating circuit for automatically compensating a frequency error between a transmitter oscillator and a receiver oscillator in digital signal transmission.

[0002]

2. Description of the Related Art In transmitting a digital signal, it is necessary to convert the frequency of the signal into a carrier band. At this time, a difference in frequency between the local oscillator on the transmitting side and the local oscillator on the receiving side ( It is inevitable that a frequency error will occur. As means for compensating for this frequency error, Costas-type carrier reproduction with a secondary loop, a method for compensating for a stationary phase error caused by frequency offset after differential detection, and estimating the phase fluctuation between one symbol and using this as the basis There is a method for compensating for the frequency offset.

The structure of the Costas type carrier reproducing circuit is shown in FIG. In the figure, numeral numerals, 39 is an input terminal, 47 is an output terminal, 40 is a distributor, 41 and 42 are multipliers, 43 is a phase error extractor, 43-1 is an adder, 43
-2 is a subtractor, 44 is a π / 2 phase shifter, 46 is a loop filter, and 45 is a voltage controlled oscillator (Voltage Controlled Osc).
illator: VCO).

In the figure, the modulated signals in the carrier band are input from the terminal 39, and VCs having different π / 2 phases are provided.
Multiply detection is performed by the O output signal and output from the terminal 47. On the other hand, the phase error extractor removes the modulation component by multiplying the signal after the multiplicative detection by 4 to detect the phase error between the VCO output signal and the carrier wave of the modulation wave.

By feeding back this phase error component to the VCO via the loop filter, it is possible to form a secondary PLL loop and suppress the frequency error and the phase error at the same time. That is, the VCO, the phase error extraction, and the loop filter reproduce the carrier wave whose phase matches the carrier wave of the modulated wave to realize the demodulation operation.

FIG. 5 shows a configuration to which the above method is applied. In the figure, reference numeral 48 is an input terminal, 51 is an output terminal, 49 is a differential detection circuit, and 50 is a phase error compensator for compensating for a stationary phase error after differential detection. In the figure, the modulated signal whose frequency is converted to the baseband is the terminal 4
8 is input, and this input signal is multiplied by the input signal before-symbol in the differential detection circuit and output to the phase error compensator.

In this configuration, the frequency error in the input signal appears as a stationary phase error for the demodulated signal, and significantly deteriorates the demodulation characteristics. Therefore, the phase error compensator can equivalently compensate the frequency error by compensating for the steady phase error.

FIG. 6 shows an example of the configuration to which the above method is applied.
In the figure, RLS (Recurisive L
east Squares) algorithm is applied to estimate the frequency offset only in the training section.

In the figure, 51a is an input terminal, 59 is an output terminal, 52 is a complex multiplier, 53 is a training signal input terminal, 54 is a phase estimator according to the RLS algorithm, 55 is a phase integrator, and 58 is a complex multiplier. Is. In this configuration, after removing the modulation component from the input signal, the phase variation between one symbol is estimated by the RLS algorithm, and the phase opposite to the phase variation due to the frequency offset is estimated by integrating this, and this is input to the input signal. The effect of frequency offset is removed by multiplication.

On the other hand, the characteristic deterioration due to the waveform distortion of the transmission line becomes remarkable with the increase of the bit rate, and the application of the adaptive equalizer is being studied to compensate for this. Adaptive equalizers include linear equalizers, decision feedback equalizers, and maximum likelihood sequence estimation (Mzximum Likelihood Sequence Estimation:
MLSE) type equalizers are known. In particular, the MLSE type equalizer has a maximum likelihood sequence estimator that minimizes the bit error rate, and therefore exhibits a significantly higher equalization capability than the other two methods. The structures of these equalizers are shown in FIGS.

In general, an adaptive equalizer applies fractional samples in order to avoid characteristic deterioration due to a sampling phase error with respect to a received signal. When compensating for frequency offset in a system using this adaptive equalizer,
Since the above methods basically assume symbol sampling, they cannot be applied to the fractional sampling system.

On the other hand, the above method can be realized by providing a linear equalizer for fractional sampling or a decision feedback equalizer in the Costas loop. The configuration in this case is shown in FIG.

In the figure, 77 is an input terminal, 84 is an identification result output terminal, 78 is a distributor, 79 and 80 are multipliers, 8
1 is an adaptive equalizer, 82 and 83 are discriminators, 85 is a complex correlator, 86 is a loop filter, 87 is a VCO, 88 is π /
A two phaser is shown. The complex correlator 85 uses the equalizer output signal Ur + jUi and the identification signal Dr + jDi to perform the operation shown in "Equation 1".

[0014]

[Equation 1]

The frequency offset estimation is possible with this configuration because the linear equalizer and the decision feedback equalizer only remove the waveform distortion by using the received signal or the past identification signal of the equalizer. That is, this is because the equalizer output signal can be regarded as a demodulation signal by synchronous detection in a transmission line having no waveform distortion.

That is, a signal from which the influence of delay distortion has been removed is output as the output 64 in FIG. 8 and the output 70 in FIG. However, since the MLSE type equalizer has a configuration of estimating a transmission code sequence having the highest likelihood with respect to a received signal rather than demodulating the signal, it is different from a linear equalizer or a decision feedback type equalizer. No demodulation signal is generated inside the equalizer.

Therefore, it is difficult to apply the MLSE equalizer in the loop. Further, as another configuration, there is a configuration in which a frequency offset is detected by a matched filter and frequency offset compensation is performed based on this.

In the matched filter, delay distortion can remove the influence of noise, so that accurate frequency offset compensation becomes possible. The structure is shown in FIG. In the figure, 89 is an input terminal, 98 is an output terminal, 90 is a distributor, 91 and 92 are multipliers, 93 is a π / 2 phase shifter, 94 is a VCO, and 95 is 1
The next filter, 96 is a delay circuit, and 97 is a frequency offset compensator.

FIG. 12 shows the configuration of the frequency offset estimating section. In the figure, 99 is an input terminal, 100 and 101 are oscillators with frequencies of −δ and + δ, 104 and 105 are matched filters, 106 is a delay circuit, 107 is a complex multiplier,
108 is a complex adder, 109 and 110 are absolute value arithmetic circuits, and 111 is a subtractor.

This frequency offset estimator utilizes the fact that the value of the correlation peak differs depending on the frequency offset in principle, but there is a problem that the imbalance of the frequencies of the oscillators 100 and 101 affects the estimation accuracy. is there.

Further, since this configuration is basically feedback control to the VCO, there is a trade-off relationship between the band of the loop filter and the frequency offset estimation accuracy, and the estimation accuracy is lowered in order to obtain a fast convergence characteristic. There is a problem of causing it.

Therefore, when the MLSE type equalizer to which the fractional sample is applied is applied, it is difficult to estimate the frequency offset with high accuracy, and there is a problem that the transmission characteristic is deteriorated by the frequency offset.

[0023]

In digital signal transmission using carrier band frequencies, there is a frequency error between the local oscillators of the transceiver. In order to demodulate an accurate signal even when phase modulation or frequency modulation is applied, it is necessary to compensate for this frequency error.

On the other hand, the adaptive equalizer is effective for compensating the waveform distortion caused by the delay dispersion, but the MLSE equalizer having a higher equalizing ability is effective. Further, in order to reduce the sampling phase error sensitivity, it is desirable to apply a fractional sampling MLSE equalizer.

However, as described above, the MLSE type equalizer only estimates the transmission sequence having the highest likelihood even for the received signal, and does not correspond to the demodulation operation. The MLSE type equalizer cannot be applied to.

Further, the method of feeding back the frequency error information from the matched filter to the VCO to establish frequency synchronization enables frequency offset compensation without using an adaptive equalizer in a frequency selective fading environment. There is a drawback that the frequency estimation accuracy is lowered in order to obtain a fast convergence characteristic.

Therefore, when the MLSE type equalizer to which the fractional sampling is applied is used, it is difficult to accurately estimate the frequency offset at high speed, and there is a problem that the characteristic deteriorates due to the frequency offset estimation error.

In view of these problems, it is an object of the present invention to provide a highly accurate and high speed frequency offset compensation method for an MLSE type equalizer to which fractional samples are applied.

[0029]

According to the invention, the aforesaid problems are solved by the means defined in the claims.

That is, the invention of claim 1 includes a correlation detector for detecting a correlation value between a reception signal and a transmission signal, and a frequency offset estimator for estimating a phase variation between sampling periods due to a frequency offset from the output signal. A frequency offset compensating circuit comprising a phase compensating unit for removing the frequency offset of the received signal based on the estimated frequency offset,

A known transmission signal for N hours is stored, a phase rotation is applied to the output signal 1 by a frequency offset, and the received signal corresponding to the output signal 1 is multiplied, and the output signal 2 is output for N hours. Correlation detector that integrates across, the output signal of the correlation detector for phase fluctuations within one time due to the frequency offset, detects the amount of change in the sum of squares,

The estimated value of the phase fluctuation is updated so that the sum of squares becomes maximum, and the frequency offset estimator for estimating the phase fluctuation within one hour and the phase fluctuation within one hour which is the output of the frequency offset estimator are used as the basis. The frequency offset compensating circuit is composed of a phase compensating unit for removing the frequency offset of the received signal.

According to a second aspect of the present invention, in the above-mentioned first aspect, the correlation detector estimates the phase variation corresponding to the amount of phase change of the known transmission signal at time K stored in the memory over K time. The value is multiplied by the Kth power, the received signal is multiplied by this, and the result is output.
I went to

These output signals are integrated and the result is used as the output of the correlation detector. The frequency offset estimator outputs K- to the known transmission signal at time K, which is the output of the memory provided in the correlation detector. The amount of phase change over 1 hour is given and output, and this is output over N-1 hour, and this output is integrated, and this is multiplied by the output signal of the correlation detector, and this is the amount of phase fluctuation within one time. Estimate the phase variation as the update amount of the estimated value of, and output this to the correlation detector,

The correlation detector and the frequency offset estimator perform the above-mentioned operation based on the updated amount of phase fluctuation, and after repeating this operation a plurality of times, the phase compensating unit transfers the received signal at time L to time L. The frequency offset compensating circuit is configured to remove the frequency offset by multiplying the phase fluctuation amount.

According to a third aspect of the present invention, a correlation detector for detecting a correlation value between a received signal and a transmitted signal, a frequency offset estimator for estimating a phase variation between sampling periods due to a frequency offset from the output signal, and an estimation In the frequency offset compensation circuit configured by the phase compensator for removing the frequency offset of the received signal based on the frequency offset,

The correlation detector inputs a register circuit for storing a reception signal for N times, a series memory circuit for storing a known transmission signal pattern for N times, and an output signal from the frequency offset estimator. And a vector phase compensation circuit that outputs N rows of vectors in two sequences, a first multiplier column that receives the first output vector and the output vector from the sequence memory circuit, and the output vector and the output of the register circuit. It is composed of a second multiplier string that inputs a vector and an adder that adds the elements of this output vector, and this adder output signal is the correlator output signal,

The vector phase compensation circuit comprises N multipliers for multiplying the input signal by the output signal from the frequency offset estimator, and each multiplier receives the output of the other multiplier as an input, and outputs the output. Connected to the input of another multiplier, the N output signals of each multiplier being the first vector output, and the N input signals of the multiplier being the second vector output,

The frequency offset estimator has a second vector output of the vector phase compensating circuit and a third multiplier row which receives the output vector input of the series memory circuit of the correlation detector, and an element of the output vector, respectively. A summing adder, a first multiplier that multiplies the output signal by the correlator output signal, a memory circuit that stores a scaling coefficient, and a memory circuit that multiplies the memory circuit output signal by the first multiplier output It is composed of two multipliers and an integrating circuit that cumulatively adds this output,

The output of the accumulator circuit is used as the output of the frequency offset estimator, and the multiplier array receives two vectors having the same dimensions as inputs, and performs multiplication by the number of dimensions for performing multiplication between elements of corresponding rows of each vector. And outputs a vector whose elements are the output signals of this multiplier,

The phase compensator multiplies the output signal of the frequency offset compensating circuit by one input and the output signal of one time before as the other input, and the output signal by the input signal. It is a frequency offset compensating circuit which is composed of a fourth multiplier and uses the output signal of the fourth multiplier as a final output signal.

[0042]

When the transmission code sequence is x _k , the fractionally sampled transmission signal S _k is given by "Equation 2".

[0043]

[Equation 2]

In "Equation 2", the subscript k represents time, and h
_i represents the impulse response of the transmission band limiting filter. However, in the case of a fractional sample, time k
Is represented by a rational number rather than an integer. Also, x _k and S
_k is generally represented by a complex number. Here, when the received signal is r _k , the output signal y _k of the correlator over the interval of time L is given by “Equation 3”.

[0045]

(Equation 3)

In formula (3), * means to take a complex conjugate. If there is no frequency offset, the received signal r _k is equal to S _k . At that time, the output signal y _k of the correlator has only the real part and takes the maximum value. When the frequency offset ω / (2π) is present, the output y _{k of the} correlator is as shown in "Equation 4".

[0047]

[Equation 4]

Here, for simplification, the case where sampling is performed at twice the symbol period is shown. Further, in Expression (4), Ts represents a sampling period, and L / 2 (ae
ven + aodd) indicates the output of the correlator when there is no frequency offset.

Therefore, by correcting the phase of the input signal so that the output signal of the correlator is maximized, the frequency offset can be estimated for an arbitrary sampling rate. Here, when the phase variation term due to the frequency offset between the sampling periods is set to w, the output signal y _k of the frequency offset-compensated correlator is given by "Equation 5".

[0050]

(Equation 5)

The optimum weighting factor W _opt is given as the solution of " _Equation 6". Although this equation is a non-linear equation, it is possible to actually obtain the solution by applying the LMS algorithm.

[0052]

(Equation 6)

In this case, the tap coefficient W is controlled by the LMS algorithm so that y _k ² becomes maximum as described above. The frequency offset estimation algorithm of the present invention to which LMS is applied is shown below.

[0054]

(Equation 7)

In "Equation 7", μ is a step size parameter indicating the step size of the update. By repeating “Equation 7”, that is, when n → ∞, w _n → w _opt
Converge to. W _opt estimated by this algorithm
The frequency offset compensation can be realized by using Eq.

However, it is assumed that W0 = 1 + j · 0.

[0057]

(Equation 8)

[0058]

FIG. 1 is a diagram showing an embodiment of the present invention. A configuration example of the present invention is shown in FIG. This figure shows a configuration in which frequency offset estimation is performed using only a unique word pattern at the beginning or middle of a burst in burst signal transmission.

In the figure, numeral 1 is an input terminal, 5 is an output terminal, 6 to 8 are burst and data switching switches, 2 is a correlator, 3 is a frequency offset estimator, 4 is a phase compensator, and 9 is Transmission signal sequence memory, 10 is a vector phase compensator, 11 and 13 are multiplier rows, 12, 14, 21,
25, 26, 31, 33 are complex multipliers, 19 and 24 are N
Input complex adder, 29 is a 2-input complex adder, 17 is an N-stage shift register, 18 and 28, 32 are delay circuits, 27
Indicates a coefficient memory circuit.

During the training period, the switch 6 is in the "ON" state and the input signal is stored in the shift register 17. On the other hand, the output of the transmission signal sequence memory in which the transmitted complex conjugate of the unique word pattern is stored is input to the multiplier array 11 and is multiplied by the output vector of the vector phase compensator.

Since the vector phase compensator performs phase compensation on each received signal based on the estimated frequency offset, the output signal of this multiplier train outputs the transmission code sequence when there is a frequency offset. . next,
The correlation operation between the output of the shift register 17 and the output of the multiplier array 11 is performed by the multiplier array 13 and the complex adder 19.

The correlator output signal is input to the frequency offset estimator. The frequency offset estimator calculates the correlation between the elements of the phase compensation vector and the transmission signal sequence vector of the vector phase compensator by the multiplier array 20 and the complex adder 24.
To do. This complex adder output signal is multiplied with the correlator output signal.

Next, this output signal is weighted by the signal from the gain memory 27 and input to the integrator composed of the adder and the delay circuit. The output signal of the integrator becomes the frequency offset estimation result and is input to the vector phase compensator provided in the correlator. An accurate frequency offset can be estimated by repeating this series of calculations.

Next, in the data section, the switches 7 and 8 are in the "ON" state, and the data is input to the phase compensator 4. In the phase compensator 4, the frequency offset estimator output signal is input to the phase integration circuit composed of the multiplier 31 and the delay circuit 32, this is converted into a phase change amount, and the result is multiplied by the input signal in the multiplier 22. Frequency offset compensation is performed by matching them.

FIG. 2 shows an example of the configuration of the vector phase compensator. In the figure, 33 is a complex conjugate converter, 34 is a memory circuit of coefficient "1", 37-1 is an output vector into the correlator, 37-2 is an output vector to the frequency offset estimator 36 is a complex multiplier, 38 is a coefficient memory, and 35 is a signal input terminal from the frequency offset estimator.

Here, the frequency is converted into a phase by estimating and raising the frequency offset to the power, and this is output as a vector for each time. On the other hand, the vector corresponding to the differential term is output to 37-2. As an application example of the present invention, FIG. 3 shows a configuration in the case of being coupled with an MLSE type equalizer.

In the figure, 113 is an input terminal, 119 is an output terminal, 114 is a distributor, 115 and 116 are multipliers,
117 is the frequency offset compensator of the present invention, 118 is M
LSE type equalizer, 120 is a π / 2 phase shifter, and 121 is a fixed oscillator. The input carrier band modulation signal is quasi-synchronized by the fixed oscillator 121 and is input to the frequency offset estimator 117 as a signal having a beat component.

The beat component of this signal is removed by the frequency offset estimator and is input to the MLSE type equalizer. The MLSE type equalizer estimates the transmission sequence with the highest likelihood for this received signal and outputs it to 119.

[0069]

Since the present invention utilizes a configuration using a matched filter, the influence of intersymbol interference due to the influence of delay distortion can be removed and the frequency offset can be estimated with high accuracy. In addition, the accuracy can be further improved by increasing the number of times of estimation. Therefore, there is an advantage that the frequency offset can be compensated with high accuracy from the first burst received. Further, since the sampling frequency of the matched filter is not limited at all, there is an advantage that it can correspond to an arbitrary sampling speed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the configuration of a vector phase compensator.

FIG. 3 is a diagram showing a configuration when the present invention is combined with an MLSE type equalizer.

FIG. 4 is a diagram showing an example of a configuration of a Costas type carrier reproducing circuit.

FIG. 5 is a diagram showing a configuration example of frequency offset compensation by differential detection and steady phase error compensation.

FIG. 6 is a diagram showing a configuration example of frequency offset compensation based on estimation of phase fluctuation between one symbol.

FIG. 7 is a diagram showing a configuration example of carrier reproduction when an equalizer is provided in a loop.

FIG. 8 is a diagram showing a configuration example of a linear equalizer.

FIG. 9 is a diagram showing a configuration example of a decision feedback equalizer.

FIG. 10 is a diagram showing a configuration example of an MLSE type equalizer.

FIG. 11 is a diagram showing a configuration example of frequency offset compensation by a matched filter.

FIG. 12 is a diagram illustrating a configuration example of a frequency offset estimation unit.

[Explanation of symbols]

1,35,48,51a, 77,60,65,71,8
9,99,113 Input terminals 5,37-1,37-2,47,51,59,84,6
4, 70, 74, 98, 112, 119 Output terminal 2 Correlator 3 Frequency offset estimator 4 Phase compensator 10 Vector phase compensator 9 Transmission signal sequence memory 27, 34, 38 Coefficient memory 6, 7, 8 Switch 11, 13, 20 Multiplier sequence 12, 21, 22, 31, 36, 41, 42, 52, 5
6, 58, 79, 80, 62, 67, 91, 92, 10
7,115,116 Multiplier 19,24,29,43-1, 63,68,72 Adder 43-2 Subtractor 18,28,32,57,61,66,96,106
Delay circuit 40, 77, 90, 114 Distributor 44, 88, 93, 120 π / 2 phase shifter 45, 87, 94 VCO 100, 103, 121 Fixed oscillator 45, 86, 95 Loop filter 43 Phase error extraction circuit 49 Delay detection circuit 50 Phase error compensator 54 Phase estimator 55 Phase accumulator 81 Adaptive equalizer 69, 82, 83 Discriminator 85 Complex correlator 75 Tapped delay line filter 76 Transmission path estimator 73 Maximum likelihood sequence estimator 97 Frequency offset estimator 104, 105 Matched filter 117 Frequency offset compensator 118 MLSE type equalizer

Claims (3)

[Claims] 1. A correlation detector that detects a correlation value between a received signal and a transmitted signal, a frequency offset estimator that estimates a phase variation between sampling periods due to a frequency offset from the output signal, and an estimated frequency offset based on the estimated frequency offset. Is a frequency offset compensating circuit configured by a phase compensating unit for removing the frequency offset of the received signal, in which a known transmission signal for N hours is stored, and a phase rotation due to the frequency offset is given to this output signal 1. , A correlation detector that multiplies the received signal corresponding to the output signal 1 and integrates the output signal 2 over N hours, and an output signal of the correlation detector for the phase fluctuation within one time due to the frequency offset. Detects the amount of change in the sum of squares, updates the estimated value of the phase fluctuation to maximize the sum of squares, and estimates the phase fluctuation within one hour Frequency Off Tsu DOO estimator and frequency offset compensation circuit, characterized in that it is composed of a phase compensation unit for removing a frequency offset of the received signal based on the phase variation within one hour, which is the output of the frequency offset estimator. 2. The correlation detector multiplies a known transmission signal at time K stored in the memory by the Kth power of an estimated value of the phase variation corresponding to the amount of phase change over K time, and the received signal is multiplied by the multiplication result. The result is multiplied and output over the memory address section N, these output signals are integrated, and the result is taken as the output of the correlation detector. The frequency offset estimator is the output of the memory provided in the correlation detector. A known transmission signal at time K, which is an output, is given a phase change amount over K-1 hours and output, and this is performed over N-1 hours, and this output is integrated, and the output of the correlation detector is added to this. The signal is multiplied, the phase fluctuation is estimated by using this as the update amount of the estimated value of the phase fluctuation amount within one time, and this is output to the correlation detector, and the correlation detector based on the updated phase fluctuation amount and Frequency offset The frequency detector removes the frequency offset by performing the above-described operation, repeating the operation a plurality of times, and then multiplying the received signal at time L by the amount of phase fluctuation over time L in the phase compensator. Frequency offset compensation circuit. 3. A correlation detector that detects a correlation value between a received signal and a transmitted signal, a frequency offset estimator that estimates a phase variation between sampling periods due to a frequency offset from the output signal, and an estimated frequency offset based on the estimated frequency offset. A frequency offset compensating circuit configured by a phase compensating unit for removing a frequency offset of a received signal, wherein the correlation detector is a register circuit for accumulating a received signal for N times, and a known transmission signal for N times. A sequence memory circuit for storing a pattern, a vector phase compensation circuit for inputting an output signal from the frequency offset estimator and outputting two sequences of N rows of vectors, an output from the first output vector and the sequence memory circuit A first multiplier string that inputs a vector, and a second multiplier string that inputs this output vector and the output vector of the register circuit A multiplier array and an adder that adds up the elements of this output vector, and this adder output signal is the correlator output signal, and the vector phase compensation circuit outputs the input signal from the frequency offset estimator. There are N multipliers for multiplying the signals, each multiplier being connected with the output of the other multiplier as the input and its output as the input of the other multiplier, and the N multipliers of each multiplier The output signal is the first vector output, the N input signals of the multiplier are the second vector outputs, and the frequency offset estimator is the second vector output of the vector phase compensation circuit and the correlation detector. A third multiplier string that receives the output vector of the series memory circuit, an adder that adds the elements of the output vector, and a first multiplier that multiplies the output signal by the correlator output signal. A multiplier, a memory circuit set aside a scaling factor,
A second multiplier that multiplies a scale circuit output signal by the first multiplier output, and an integrating circuit that cumulatively adds the output, and this integrating circuit output is the frequency offset estimator output, and the multiplier array Is provided with two vectors having the same dimension as inputs, and is provided with a multiplier for the number of dimensions for performing multiplication between elements of corresponding rows of each vector, and outputs a vector having the output signal of the multiplier as an element, The compensator includes a third multiplier which uses the output of the frequency offset compensation circuit as one input and an output signal one time before as the other input, and a fourth multiplier which multiplies this output signal by the input signal. A frequency offset compensating circuit, characterized in that the output signal of the fourth multiplier is used as a final output signal.