JPH08223227A - Data receiving device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a small-sized, simple data receiving device with a small amount of calculation. [Structure] The input analog received signal is
The digital converting means 2 converts into a digital signal based on a clock signal having a frequency N times the baud rate. This digital signal is subjected to frequency domain equalization, time domain equalization and precursor equalization by the transversal filter type equalization means 3 and 4, and at this time, based on the second clock signal, etc. The digitized signal is made to have a frequency at the baud rate. Data symbols are regenerated from this equalized signal by the received symbol determination means 5. In addition, the phase extraction means 7 evaluates the optimum phase in the analog reception signal from the equalized signal and the precursor information in the reproduction code string to form a phase control signal, and various clock signals are phased according to the phase control signal. Is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus for extracting a timing of a received signal and identifying a data symbol, for example, data incorporated in a data transceiver for ping-pong transmission type two-wire metallic cable subscriber line transmission. It is applicable to a receiving device.

[0002]

[Prior art]

Reference 1 "Komi, Mano, Yamano, Kumozaki", Multimedia Network Series "Digital Access Method", 1
Published by Ohmsha Co., Ltd. on Oct. 1, 993, pp.92-95, Reference 2, “Kawakami, Komazaki, Gunji, Furukawa,“ SC biquadratic basic circuit and its application to √f equalizer ”, 1983 IEICE General Conference, No. 535] Reference 3 “Fukasawa, Hosoda, Ando, Miyamoto, Kawaguchi”, “DSP
Bridge Tap Equalizer ", 1983 IEICE General Conference, No. 538] Reference 4 “Japanese Patent Application Laid-Open No. 4-157586” In the related art, a data receiving apparatus incorporated in a data transceiver for subscriber line transmission of this type is, as shown in Reference 1, a frequency domain equalizer and a time domain equalizer. And a region equalizer. The frequency domain equalizer has a so-called √f equalization function for compensating for the loss of the transmission line. For example, the frequency domain equalizer has an SC (switched capacitor) biquadratic basic circuit as described in Reference 2. Can be applied. The time domain equalizer has a so-called bridge tap equalization function (BT equalization function) that compensates for reflection from a bridge tap, which is a distribution configuration from a transmission line to each home, and is described in, for example, Document 3. The decision feedback type as described above can be applied. Further, Document 4 describes that this decision feedback type is provided with a pre-cursor generation function to facilitate timing extraction.

Looking at these equalizer configurations in a recent data receiving apparatus from the viewpoint of operating speed and filter configuration, in general, the √f equalizer operates at an operating speed of 2 to 8 times the baud rate. The tap IIR filter has a configuration of one to two stages, while the BT equalizer has a configuration of a few-tap FIR filter operating at a baud rate and a subtractor for its feedback. And these equalizers are connected by an analog time continuous signal.

[0004]

As mentioned above, the IIR
In a data receiving device that requires a calculation function of a filter or a FIR filter, an analog / digital conversion function and a digital signal processor (hereinafter, referred to as DSP) are applied to improve equalization performance, LSI.
It is expected that the chip size will be reduced, the size will be simplified, and various additional functions will be easily added. Also, from the perspective of LSI development costs, there are many types of general-purpose products,
Very advantageous.

The advantages of applying the DSP are described in, for example, Document 5 "IF Selection" Mastering the DSP ", CQ Publishing Co., Ltd., first edition issued August 1, 1989, pp.34-39". Has been done.

However, the data receiving device having the √f equalizing function and the BT equalizing function is easy to be configured with a switched capacitor filter (SCF) or a logic circuit, and is not necessarily suitable for realization with a DSP. There wasn't.
This is because the amount of calculation per unit time inside the DSP becomes enormous.

For example, when the DSP is applied to the equalization filter in the data receiving device incorporated in the data transceiver for the subscriber line transmission for the ping-pong transmission system of 320 kbps, the arithmetic processing of about 70 to 200 MIPS is required. However, it is only an amount that can be finally reached by the latest DSP, and therefore, in terms of power consumption and LSI manufacturing cost, it is not satisfactory as a data receiving device incorporated in a data transceiver for subscriber line transmission.

The cause of increasing the calculation amount per unit time inside the DSP is the √f equalizer and the BT.
When an analog time continuous signal that connects equalizers is expressed inside the DSP, the sampling rate of the data handled internally becomes about 2 to 4 times the baud rate, and the IIR filter that constitutes the frequency domain equalizer is It is conceivable that the filter calculation must be executed at an operating speed of about 2 to 8 times the baud rate.

Therefore, there is a demand for a small-sized, simple data receiving apparatus capable of compensating the optimum reception timing and having a structure suitable for applying a DSP.

[0010]

In order to solve the above problems, the present invention receives and processes an analog reception signal having transmission distortion including transmission line loss and bridge tap reflection.
A data receiving apparatus for extracting the timing of a received signal and reproducing a data symbol is characterized by including the following means.

That is, (1) analog / digital conversion means for converting an analog received signal into a digital signal based on a first clock signal having a frequency N times the baud rate, and (2) a converted digital signal. for,
A transversal filter type or the like, which performs frequency domain equalization, time domain equalization, and pre-cursor equalization, and outputs the discrete equalized signal at a baud rate cycle based on a second clock signal having a baud rate frequency Means of conversion,
(3) Evaluate the optimum phase in the analog received signal from the received symbol determination means that reproduces the data symbol based on the equalized signal, and (4) Precursor information in the output signal from the equalized signal and the received symbol determination means. However, the present invention is characterized by having a phase extracting means for outputting a phase control signal and (5) a clock forming means for forming first and second clock signals having phases according to the phase control signal.

[0012]

In the data receiving apparatus of the present invention, the input analog received signal is converted into a digital signal by the analog / digital converting means based on the first clock signal having a frequency N times the baud rate, and this conversion is performed. The frequency-domain equalization, the time-domain equalization and the pre-cursor equalization are performed on the digitalized signal by the transversal filter type equalization means, based on the second clock signal having the frequency of the baud rate. Then, the equalized signal is made to have the frequency of the baud rate, and the received symbol determination means reproduces the data symbol based on the equalized signal. Also, by the phase extraction means,
From the pre-cursor information in the equalized signal and the reproduced code string, the optimum phase in the analog reception signal is evaluated to form a phase control signal, and the first and second clock signals have phases corresponding to this phase control signal. Is formed as.

As described above, the frequency domain equalization, the time domain equalization, and the pre-cursor equalization are executed by one transversal filter type equalizer so that the symbols can be reproduced. Can be compensated for, the overall configuration can be made small and simple, and the overall calculation amount can be reduced.

Since the calculation amount can be reduced and the transversal filter type equalizer is applied, it is easy to apply the digital signal processor, and when the digital signal processor is applied to the part to which the digital signal processor can be applied. It can be made even smaller and simpler.

[0015]

【Example】

(A) First Embodiment Hereinafter, a first embodiment of the data receiving apparatus according to the present invention will be described in detail with reference to the drawings. Here, FIG. 1 is a block diagram showing the overall configuration of the data receiving apparatus of the first embodiment.

In FIG. 1, the data receiving apparatus of the first embodiment comprises an analog / digital converter 2, a transversal filter type equalizer 3 (see FIG. 2), a decimator 4, a received symbol judging device 5, and a phase extraction. It comprises a device 7, a digital PLL circuit 8 and a frequency multiplier 9.

The analog / digital converter 2 converts the analog reception signal given from the input terminal into a frequency multiplier 9
On the basis of the clock signal from, the signal is sampled, converted into a digital signal, and output to the transversal filter type equalizer 3.

The transversal filter type equalizer 3 is
The tap coefficients w0, ..., WM are preset so as to be optimum according to the conditions of the transmission line in which the data receiving device is installed. Through this setting operation, the transversal filter type equalizer 3 adjusts the gain and √f.
Equalization, BT equalization, and pre-cursor equalization can be performed. Transversal filter type equalizer 3
The output signal (equalized signal) from is supplied to the decimator 4.

FIG. 2 is a block diagram showing a detailed configuration example of the transversal filter type equalizer 3. In FIG. 2, this transversal filter type equalizer 3 includes M 1-sampling period delay elements 10-0 connected in cascade.
-10- (M-1) and M + 1 tap coefficient multipliers 1
1-0 to 11-M and M adders 12-0 to 12-
And (M-1). This transversal filter type equalizer 3 includes a delay element 10- for one sampling period.
Digital coefficient data (sample data) of M + 1 taps which are made different by one sampling period by the delay operation of groups 0 to 10- (M-1), and tap coefficient multipliers 11 corresponding to the data, respectively. -0,
..., 11-M is the set tap coefficient w0, ...,
The sum of all digital data multiplied by wM and multiplied by tap coefficients w0, ..., WM is obtained by a group of adders 12-0 to 12- (M-1) connected in cascade to obtain an equalized signal. To form.

The decimator 4 is a digital PLL circuit 8
On the basis of the clock signal from the reversal filter type equalizer 3, and re-sampling the output signal from the transversal filter equalizer 3 to convert the sampling rate of the signal to 1 / N (here, N is 2). Is. The output signal from the decimator 4 is sent to the reception symbol determiner 5 and the phase extractor 7.

The received symbol determiner 5 determines the received symbol by comparing the output signal level from the decimator 4 with an internally held threshold level for determination. As shown in FIG. 1, the clock signal may be input, or the clock signal may not be input. For example, if the transmission code is an AMI code, it is determined to be 1, 0, or -1. The reproduced symbol obtained by the received symbol determiner 5 is sent to the external device as an output of the data receiving device via the output terminal 6 and is given to the phase extractor 7.

The phase extractor 7 evaluates the optimum reception timing from the output signal from the decimator 4 and the output signal from the reception symbol determination unit 5 by, for example, the precursor method, and outputs the clock signal from the digital PLL circuit 8. The phase shift with respect to the input analog reception signal of is extracted and given to the digital PLL circuit 8. For example, if the transmission code is an AMI code, the optimum reception timing is evaluated at the timing of changing from 0 to 1 and the timing of changing from 0 to −1.

The detailed structure of the precursor method and the phase extractor is described in, for example, Reference 5 “Yamada and Hayashi,
"Examination of Timing Extraction Method in Digital Subscriber Line Transmission System", 1988 IEICE Spring National Convention, B-524 ".

The digital PLL circuit 8 is provided as a clock recovery circuit, and basically forms a clock signal having the baud rate of the analog received signal. At that time, the phase extractor 7 The phase of the output clock signal is adjusted based on the given phase shift signal. The clock signal from the digital PLL circuit 8 is given to the decimator 4, the reception symbol determination unit 5 and the frequency multiplier 9.

The frequency multiplier 9 forms a clock signal having a frequency N times that frequency based on the clock signal from the digital PLL circuit 8 and outputs the clock signal to the analog / digital converter 2.

For example, if the data receiving device is 320 kb
This is for the ps ping-pong transmission system, and when the value of N is selected as 2, the digital PLL circuit 8 has 3
The clock signal of 20 kHz is output, and the frequency multiplier 9 outputs the clock signal of 640 kHz. The transversal filter type equalizer 3 operates at 640 kHz because the sampling data series of 640 kHz is input.

Next, the operation of the data receiving apparatus of the first embodiment, which is composed of the above-mentioned respective parts, will be described in detail with reference to the signal waveform diagrams of FIGS. Here, FIG. 3 is a signal waveform diagram of each part of the first embodiment, and FIG. 4 is a signal waveform diagram for explaining the operation of the transversal filter type equalizer 3. It should be noted that these drawings show the case where the value of N is 2 and the transmission code is the AMI code.

The analog reception signal shown in FIG. 3 (B) input from the input terminal 1 is the analog / digital converter 2
3A is converted into a digital signal as shown in FIG. 3C based on the clock signal from the frequency multiplier 9 shown in FIG. 3A and inputted to the transversal filter type equalizer 3. The signal is equalized by the Versal filter type equalizer 3 and converted into a signal as shown in FIG.

Here, in the analog reception signal as shown in FIGS. 4A and 3B, √f received on the transmission line.
It includes distortion (transmission loss) and distortion such as reflection (BT reflection) from a bridge tap which is a switching configuration between the transmission line and each home, and these distortions are compensated by the transversal filter type equalizer 3. At the same time, waveform shaping (precursor equalization) of the precursor is performed in order to effectively perform timing extraction. As a result, the equalized signal from the transversal filter equalizer 3 is shown in FIG.
Also, as shown in FIG. 3D, the distortion is suppressed and the pre-cursor 21 immediately before the main cursor 22 is clarified.

In FIG. 4, the input received signal shown in FIG. 4A, which is an isolated waveform (isolated pulse) that is distorted on the transmission line, is shaped (equalized) by the transversal filter type equalizer 3. 4B), the post-waveform shaping signal shown in FIG. 4 (B) has the intersymbol interference removed at the reception timing as shown in FIG. 4 (C), and as a result, FIG. As shown in (D), a reproduction code string which takes "1" only at one reception timing (isolated pulse) is obtained.

The signal (waveform-shaped signal) after such equalization processing is performed by the decimator 4 based on the clock signal from the digital PLL circuit 8 shown in FIG.
FIG. 3 (F) in which the sampling rate is 1/2 (= 1 / N)
Is converted into a signal and input to the reception symbol judging device 5, which is compared with the judgment threshold level and reproduced into a code string as shown in FIG. 6 to the external device.

The reproduction code string shown in FIG. 3 (G) and the output signal from the decimator 4 shown in FIG. 3 (F) are input to the phase extractor 7, and by this phase extractor 7, a pre-cursor portion exists. By comparing the reproduction code string having only the main cursor portion with the output signal from the decimator 4 having the pre-cursor portion and the main cursor portion, the reception timing with respect to the input reception signal (see FIG.
(E)) Phase shift (FIG. 3 (H)) is extracted, and this phase shift signal is fed back to the digital PLL circuit 8 to adjust the timing of the clock signal from the digital PLL circuit 8 which defines the reception timing. Together with the frequency multiplier 9 which doubles the frequency (= N times)
The timing of the clock signal from is also adjusted.

FIG. 3 (H) shows a case where the phase shift signal changes to the + side because the phase of the clock signal from the digital PLL circuit 8 is ahead of the optimum reception timing.

Therefore, according to the first embodiment, one transformer is used instead of the frequency domain equalizer for compensating the transmission line loss and the time domain equalizer for compensating the BT reflection in the conventional data receiving apparatus. Since the Versal filter type equalizer is applied, and this transversal filter type equalizer also has the function of precursor equalization, it is possible to reduce the necessary calculation processing amount, and the configuration is small, Can be simple. Further, according to the first embodiment, the DSP having various merits can be applied to each unit.

The part excluding the analog / digital converter 2, the digital PLL circuit 8 and the frequency multiplier 9 is a part that can be realized by a DSP, and all of the plurality of parts that can be realized by these DSPs are one DSP. It is also possible to realize with.

According to the data receiving apparatus of the first embodiment, the amount of calculation processing can be reduced for the following reasons.

Since there is only one equalizer, it is not necessary to represent an analog time continuous signal between the frequency domain equalizer and the time domain equalizer, and the sampling rate of the data to be handled is a very small integer multiple of the baud rate (eg, (2 times), the amount of calculation processing can be reduced.

The conventional frequency domain equalizer and time domain equalizer are not completely uncorrelated, but have a redundant part. For example, the time domain equalizer has a redundant function of compensating for insufficient equalization of the frequency domain equalizer.
In the first embodiment, these two equalizers are combined into one transversal filter type equalizer, so that the redundant portion can be reduced and the total processing amount can be reduced.

This reason is based on the premise that the DSP is applied, and can be regarded as a reason for the modified example of the first embodiment (similar to FIG. 1 when made into a drawing). In the description of FIG. 1, the operating speed of the transversal filter type equalizer 3 is twice the baud rate. However, since the decimator 4 discards half of the output data of the transversal filter type equalizer 3, it is possible not to calculate the discarded data.
Transversal filter type equalizer 3 and decimator 4
If the above is realized by one DSP, the speed of the final output of this DSP is the baud rate, and therefore the operation speed of the equalizer 3 can also be a baud rate, and the amount of calculation in this DSP can be reduced. For example, when the sum of products operation executed by the transversal filter type equalizer is performed at the baud rate, a baud rate equalized signal can be obtained without providing a decimator. This is possible because it is a transversal filter (FIR type), and since the filter output is fed back in the IIR type applied to the frequency domain equalizer, the filter output signal must be calculated every time.

It should be noted that the inventor of the present invention has shown by simulation that in the case of a relatively short distance line of 320 kbps ping-pong transmission system, a transversal filter type equalizer 3 having about 5 to 15 taps has sufficient equalizing ability. I'm confirming. That is, the eye opening ratio in the simulation result is about 60%, which is about the same as that of the conventional data receiving apparatus. Also, in the case of a relatively short distance line of 320 kbps ping-pong transmission system, the transversal filter type equalizer 3, the reception symbol determination unit 5 and the phase extractor 7 are provided.
Is realized by DSP, the calculation amount is 20
It is about MIPS, which is significantly improved as compared with the conventional 70 to 200 MIPS.

As described above, it is easy to implement by applying one DSP to the DSP applicable portion, and in view of power consumption and LSI manufacturing cost, a data receiving device for subscriber line transmission. Can be fully applied to.

By applying the DSP to the data receiving device for the subscriber line transmission, the following merits (i)-
(iii) occurs.

(I) The DSP has been widely used for a long time, and there are many kinds of general-purpose products. If a general-purpose product is applied, development cost can be reduced and a cheaper data receiving device can be realized.

(Ii) In the DSP, since the intended structure and coefficient of the digital filter can be set by software, it is easy to design and realize each filter corresponding to various transmission line conditions. By designing individual filters, it is possible to realize a data receiving apparatus with higher quality.

(Iii) Since all operations of the DSP can be set by software, applications other than the online operation of the data transceiver can be easily realized without adding hardware. For example, it is possible to easily realize the generation of a training pattern in the training sequence at startup, the training type of the second embodiment described later, and the like. That is, it is possible to realize a data receiving device having a simpler configuration.

(B) Second Embodiment Next, a second embodiment of the data receiving apparatus according to the present invention will be described in detail with reference to the drawings. FIG. 5 is a functional block diagram of the second embodiment, which is the same as FIG. 1 according to the first embodiment.
Corresponding parts are designated by the same reference numerals and the description thereof is omitted.

The data receiving apparatus of the second embodiment is shown in FIG.
As shown in, the first training means 30 and the second training means 31 are provided in addition to the configuration of the first embodiment. The data receiving apparatus of the second embodiment is
The training sequence is performed when communication is started with the data transmitting device on the other side, and
Training means 30 and second training means 3
1 functions in this training sequence.

The first training means 30 sequentially switches the phase steps of the clock signal output from the digital PLL circuit 8 and sets the digital PLL to the phase step in which the output signal of the analog / digital converter 2 becomes maximum.
The phase of the clock signal output from the circuit 8 is set.

The second training means 31 takes in the output signal from the analog / digital converter 2 for a certain period of time, searches for a tap coefficient that optimizes the equalization characteristic of the transversal filter type equalizer 3, and taps the tap coefficient. It sets the coefficient. Therefore, in the second embodiment, a transversal filter type equalizer 3 having a variable tap coefficient is applied.

In the training sequence, FIG.
As shown in (1), the phase of the clock signal output from the digital PLL circuit 8 is first set by the first training means 30 (step 100), and in this phase set state, the optimum tap by the second training means 31 is performed. A coefficient search and set are executed (step 101).

Next, the phase setting process of the clock signal output from the digital PLL circuit 8 by the first training means 30 will be described. First training means 3
0 may be configured by software, and
It may be configured as hardware, but in the following,
Such processing will be described with reference to the flowchart shown in FIG.

When the training sequence is started and such processing is started, an initial value 0 is set to the output signal peak parameter Peak and an initial value 0 is set to the phase step parameter i (step 150). Then, the phase step from the digital PLL circuit 8 is changed to #i.
(Step 151).

Here, FIG. 8 shows the types of phase steps. The phase of each phase step # 0, ..., # (M-1) is different for each phase angle obtained by equally dividing the period of the clock signal from the digital PLL circuit 8 by M (M is the number of phase steps), and its waveform is , The waveform of the clock signal itself. FIG. 8 shows the case where the number of phase steps is eight. In the process of FIG. 7, the phase steps are sequentially switched from # 0 to # (M-1).

In this phase step #i, the maximum value of the k sample data converted into a digital signal by the analog / digital converter 2 is stored in the A register (step 152).

Here, the sample number k is the sample number corresponding to the period in which one or more points having the maximum amplitude of the transmission code (training pattern) in the training sequence are included. For example, the mark rate is 1/8
AMI code is used as a training pattern, and N =
When the frequency multiplier 9 of 2 is applied, k is 16 or more.

After that, the value of the A register and the output signal peak parameter Peak are compared in magnitude. When the output signal peak parameter Peak is smaller than the value of the A register, the output signal peak parameter Peak is updated to the value of the A register, and , After storing the phase step parameter i in the phase candidate parameter Phase (step 15
4), the phase step parameter i is incremented by 1 (step 155), and the output signal peak parameter Pea is obtained.
When k is equal to or larger than the value of the A register, the phase step parameter i is immediately incremented by 1 (step 1
55).

When the phase step # 0 is a candidate, the output signal peak parameter Peak has an initial value of 0 and a positive result is always obtained in step 153, so the processing of step 154 is always executed. .

Next, by comparing the phase step parameter i with the total number of phase steps, whether or not the confirmation of the peak of the output signal has been completed for all the phase steps # 0 to # (M-1). It is determined whether or not (step 156), and if not completed, the process returns to step 151 described above.

When the confirmation of the output signal peaks for all the phase steps # 0 to # (M-1) is completed through such loop processing, the phase step #Phase defined by the phase candidate parameter Phase is set to the digital P
The phase of the clock signal from the LL circuit 8 is set and the series of processing is completed.

As a result, the second training means 31
Is moved to a state in which it performs processing. So, in the following,
The processing by the second training means 31 will be described.

The second training means 31 may be configured by software or hardware, but in any case, it is schematically shown in the flowchart of FIG. Perform processing.

First, a timer is started to start counting a predetermined time (step 200), and until the timer times out, a transversal filter type equalization based on the sample data from the analog / digital converter 2 is performed. Repeat the calculation of the optimum tap coefficient of the device 3 (step 20
(1, 202), when the timer times out, the taps obtained by the calculation are set and the series of processing ends (step 203). When the timer times out, if the optimum tap coefficient has already been set for each tap in the processing of steps 201 and 202,
The process of step 203 is omitted.

When the processing of the second training means 31 is finished, the first and second training means 30 and 31 have finished their functions, and therefore it is almost absent, and the data receiving apparatus of the second embodiment is also present. , After this,
It operates similarly to the data receiving apparatus of the first embodiment.

As a method of searching for the optimum tap coefficient executed by the second training means 31, a normalized LMS (least squares method) algorithm can be applied. That is, the reference optimal equalization waveform of the training pattern is generated, and the tap coefficient is updated so that the square error between the output waveform of the transversal filter equalizer 3 and the reference optimal equalization waveform is minimized. Algorithms can be applied.

FIG. 10 is a hardware representation of the second training means 31 for executing the normalized LMS algorithm. Further, FIG. 11 is a flowchart showing a processing procedure of the normalized LMS algorithm.
Further, FIG. 12 is an example of a signal waveform diagram of each part related to the second training means 31 to which the normalized LMS algorithm is applied.

In FIG. 10, the second training means 31 to which the normalized LMS algorithm is applied is the optimum equalized waveform generator 40, the subtractor 41 and the tap coefficient controller 4.
It consists of two.

The optimum equalized waveform generator 40 follows the timing based on the reproduction code in the training period.
An optimal equalization waveform as shown in FIG. 12D for the training pattern and a tap update signal as shown in FIG. 12F that is on during a period determined according to the level change of the optimal equalization waveform are output. To do.

The subtractor 41 obtains an error between the output of the transversal filter type equalizer 3 whose timing is adjusted and the optimum equalized waveform.

Although the signal line is not shown in the drawing, the tap coefficient control unit 42 is also provided with sample data of each tap before the multiplication of the tap coefficient, and at the time when the tap update signal is on and the error is larger than the threshold value, Normalized tap coefficient LMS
It is updated by law.

Next, the processing of the second training means 31 to which the normalized LMS algorithm is applied, which is expressed as shown in FIG. 10 when expressed in the form of a functional block diagram, will be described.
This will be described with reference to FIG.

First, a timer is started to start measuring a predetermined time (step 250), and sample data u (0) to u of each tap of the transversal filter type equalizer 3 is started.
While (-M) is cleared (step 251), each tap coefficient w0 of the transversal filter type equalizer 3 is
wM is also cleared (step 252), and time parameter n
Is set to an initial value 0 (step 253). Then, the process proceeds to the process of updating the optimum tap coefficient at time n after step 254.

Then, new input data u (n) is taken in (step 254), and the optimum equalized waveform d (n) at the time n is taken in (step 255). Next, the equalized output y that is the product sum value of the sample data u (n) to u (n−M) of each tap and the corresponding tap coefficient w0 to wM is obtained (step 256), and the sample data of each tap is obtained. The square sum x of u (n) to u (n-M) is obtained (step 257), and the error e of the equalized output y from the optimum equalized waveform d (n) at the time n is obtained (step 257). 25
8).

Thereafter, it is determined whether or not the tap update signal is on at the time n (step 25).
9). If it is off, the time parameter n is incremented by 1 (step 262), it is confirmed that the timer has not overflowed (step 263), the process returns to step 254 described above and proceeds to the processing of the next time.

On the other hand, when the tap update signal is on,
Further, the error e at the current time n is the range Δe between the positive and negative thresholds
-It is determined whether or not it is within Δe (step 2
60). That is, it is determined whether or not the error e is small enough.

If it is within this range Δe to -Δe (if the error e is small enough to be acceptable), the time parameter n is incremented by 1 (step 26).
2) After confirming that the timer has not overflowed (step 263), the process returns to step 254 described above to proceed to the processing at the next time. Error e is within the allowable range Δe to −Δe
If it is outside, sample data u (n) of each tap, ...,
A value u (n) / which is obtained by normalizing u (n−M) by its sum of squares x.
x, ..., u (n−M) / x, the contribution rate e · u to the error e
, (N) / x, ..., Eu (n−M) / x are distributed, and the tap coefficients w0, ..., WM are updated accordingly (step 261), and then the time parameter n is incremented by 1 ( In step 262), it is confirmed that the timer has not overflowed (step 263), the process returns to step 254 described above, and proceeds to the processing at the next time.

While repeating such processing,
When the timer overflows, the series of processing ends.

Here, the reason why the tap update signal is provided to limit the period for performing the tap update operation is to prevent meaningless tap update. Although many training patterns have isolated pulses, what matters here is whether or not the pattern undergoes a predetermined change. Therefore, the pre-cursor, main cursor and after-cursor shown in FIG. The level of the cursor period or the like is a problem, and if the equalization level in these periods is appropriate, the tap coefficient can be determined to be appropriate. If the tap coefficient is updated in a period other than these, the equalized waveform in the isolated pulse becomes strange, which is not preferable. Therefore, the tap update signal is provided to limit the period for performing the tap update operation.

Next, FIG. 12 will be briefly described. The training pattern shown in FIG. 12 subjected to transmission distortion is
As shown in FIG. 12 (B), the signal is converted into a digital signal and input to the transversal filter type equalizer 3, and is equalized by the transversal filter type equalizer 3, and as shown in FIG. 12 (C). Converted to an equalized output signal. The error of this equalized output signal with respect to the optimum equalized waveform shown in FIG. The obtained error shown in FIG. 12 (E) is a period in which the error exceeds the allowable range.
In the period in which the tap update signal shown in (F) is on, FIG.
The tap is updated as shown in (G).

In the example shown in FIG. 12, in the first updating process, the tap coefficient is updated so that the waveform in the pre-cursor period becomes clearer in the equalized output, and the second updating process is performed. In, the tap coefficient is updated so that the waveform in the after cursor period becomes 0 in the equalized output.

Therefore, according to the second embodiment, in addition to the configuration of the first embodiment, the phase steps of the clock signal output from the digital PLL circuit 8 are sequentially switched to output the output signal of the analog / digital converter 2. The first training means 30 for setting the phase of the clock signal output from the digital PLL circuit 8 and the output signal from the analog / digital converter 2 are fetched for a certain period of time in a phase step that maximizes Since the tap coefficient for optimizing the equalization characteristic of the equalizer 3 is searched and the second training means 31 for setting the tap coefficient is provided, the same effect as that of the first embodiment is obtained, and further, The effect that the code string can be reproduced more accurately can be obtained.

In the first embodiment, the tap coefficients inside the transversal filter type equalizer 3 are set in advance. In general operation, these tap coefficients are designed for some reference lines. It is considered that the values should be made into a menu and selected from them (the menu-based selection method for the √f equalizer is described on page 93 of the above-mentioned document 1), so that for all lines Appropriate but not always optimal. In the second embodiment, since the optimum tap coefficient can be used for all transmission lines, the effect that the code string can be reproduced with higher accuracy can be obtained as described above.

(C) Other Embodiments In the above embodiment, the digital PLL circuit and the frequency multiplier are shown separately, but the frequency multiplier function may be incorporated in the digital PLL circuit.
FIG. 13 shows a modified part in this case. FIG.
3, the first frequency divider 51 divides the frequency of the reference clock signal from the reference oscillator 50 and outputs it to the analog / digital converter 2, and the clock signal from the first frequency divider 51 is changed to the second frequency. The frequency divider 52 further divides the frequency (divides by N) and outputs it to the decimator 4. At this time, the phase reference of the first and second frequency dividers 51 and 52 is controlled by the phase switching controller 53 according to the phase shift signal from the phase extractor 7, and the first frequency divider 51 is The frequency division ratio of the phase extractor 7
Is controlled by the phase switching controller 53 according to the phase shift signal from.

Further, although the digital PLL circuit is applied as the clock recovery circuit in the first embodiment, an analog PLL circuit may be applied.
In the case of the second embodiment, the first training means 31
It is difficult for the analog PLL circuit to respond to the switching of the phase steps performed by the above, and it is difficult to apply the analog PLL circuit.

Further, the above embodiment is made in consideration of a data receiving device incorporated in a data transceiver for ping-pong transmission type two-wire metallic cable subscriber line transmission, but similar BT reflection or transmission is performed. It can also be applied to a data receiving device of a data transmission system in which loss is a problem. Therefore, the code is not limited to the AMI code.

[0085]

As described above, according to the present invention, one transversal filter type equalizer executes frequency domain equalization, time domain equalization and precursor equalization to reproduce a symbol. Since this is done, the overall configuration can be made small and simple while compensating for the optimization of the reception timing, and the overall calculation amount can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is a block diagram showing a transversal filter type equalizer of the first embodiment.

FIG. 3 is a signal waveform diagram of each part of the first embodiment.

FIG. 4 is a functional explanatory diagram of a transversal filter type equalizer of the first embodiment.

FIG. 5 is a block diagram showing a configuration of a second embodiment.

FIG. 6 is a flowchart of a training sequence processing procedure of the second embodiment.

FIG. 7 is a processing flowchart of the first training means of the second embodiment.

FIG. 8 is an explanatory diagram of a phase step of the second embodiment.

FIG. 9 is a schematic processing flowchart of a second training means of the second embodiment.

FIG. 10 is a functional block diagram of a second training means of the second embodiment.

FIG. 11 is a detailed processing flowchart of the second training means of the second embodiment.

FIG. 12 is a signal waveform chart of each part in the training sequence according to the second training means of the second embodiment.

FIG. 13 is a block diagram showing the configuration of the main part of another embodiment.

[Explanation of symbols]

2 ... Analog / digital converter, 3 ... Transversal filter type equalizer, 4 ... Decimator, 5 ... Received symbol judging device, 7 ... Phase extractor, 8 ... Digital PLL circuit, 9 ... Frequency multiplier, 30 ... 1st training means, 31 ... 2nd training means.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H04L 7/033 H04L 7/02 B (72) Inventor Shoji Kobayashi 1-7 Toranomon, Minato-ku, Tokyo 12 Oki Electric Industry Co., Ltd. (72) Inventor Chiyomi Nakano 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Mikishi Okuno 1-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Tetsuya Onoda 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (3)

[Claims] 1. An analog received signal having a transmission distortion including a transmission line loss and a bridge tap reflection is received and processed,
In a data receiving apparatus for extracting timing of a received signal and reproducing a data symbol, analog / digital conversion means for converting an analog received signal into a digital signal based on a first clock signal having a frequency N times the baud rate, Frequency domain equalization for the converted digital signal,
A transversal filter type equalizing means for performing time domain equalization and pre-cursor equalization, which outputs the discrete equalized signal at a baud rate cycle based on a second clock signal having a baud rate frequency; Based on the pre-cursor information in the received symbol determination means for reproducing the data symbol based on the equalized signal and the equalized signal and the output signal from the received symbol determination means, the optimum phase in the analog received signal is evaluated to obtain the phase control signal. And a clock forming means for forming the first and second clock signals having a phase according to the phase control signal. 2. In the first half of the training sequence, first training means for setting the phase of the first clock signal to a phase where the digital signal from the analog / digital conversion means becomes maximum, and the second half of the training sequence. 2. The data receiving apparatus according to claim 1, further comprising a second training unit that searches for and sets an optimum value of the tap coefficient of the transversal filter type equalization unit. 3. At least one of the transversal filter type equalizing means, the received symbol determining means, the phase extracting means, the first training means and the second training means is constituted by a digital signal processor. Claim 1 characterized by the above.
Or the data receiving device according to 2.