JPH08222729A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH08222729A JPH08222729A JP7023258A JP2325895A JPH08222729A JP H08222729 A JPH08222729 A JP H08222729A JP 7023258 A JP7023258 A JP 7023258A JP 2325895 A JP2325895 A JP 2325895A JP H08222729 A JPH08222729 A JP H08222729A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- concentration
- field effect
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 230000005669 field effect Effects 0.000 claims abstract description 11
- 238000013459 approach Methods 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 5
- 239000010408 film Substances 0.000 claims 2
- 239000010409 thin film Substances 0.000 claims 1
- 230000005685 electric field effect Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 9
- 229910052796 boron Inorganic materials 0.000 description 9
- 239000010410 layer Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
- H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
- H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】
【目的】出力抵抗が大きく、かつ、その値をバイアス条
件によらず一定に保つことのできるＭＩＳ型電界効果ト
ランジスタを有する半導体装置を提供すること。
【構成】第１導電型のチャネル領域に第１導電型の高濃
度領域５を設け、チャネル領域の表面不純物濃度がドレ
イン領域４ｂ側からソース領域４ａに近付くに従って高
くなるようにしたＭＩＳ型電界効果トランジスタを有す
る半導体装置。
(57) [Summary] [Object] To provide a semiconductor device having a MIS field effect transistor which has a large output resistance and whose value can be kept constant regardless of a bias condition. A MIS-type electric field effect is provided in which a first-conductivity-type high-concentration region 5 is provided in a first-conductivity-type channel region, and the surface impurity concentration of the channel region increases as the drain region 4b approaches the source region 4a. A semiconductor device having a transistor.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アナログ回路に用いる
のに適したＭＩＳ型ＦＥＴ（金属−絶縁膜−半導体型電
界効果トランジスタ）を有する半導体装置及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MIS type FET (metal-insulating film-semiconductor type field effect transistor) suitable for use in an analog circuit and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来のＭＩＳ型ＦＥＴの断面図を図３に
示す。シリコン基板１表面のゲート絶縁膜１０上にゲー
ト電極３を設け、ここに電圧を印加することでチャネル
層を誘起させる。チャネル領域表面の不純物濃度は、ソ
ース領域４ａとドレイン領域４ｂの間で一定であり、所
望のしきい値が得られる濃度に設定されている。図にお
いて、２は素子分離絶縁膜、８は層間絶縁膜、９は金属
配線である。2. Description of the Related Art A sectional view of a conventional MIS type FET is shown in FIG. A gate electrode 3 is provided on the gate insulating film 10 on the surface of the silicon substrate 1, and a voltage is applied thereto to induce a channel layer. The impurity concentration on the surface of the channel region is constant between the source region 4a and the drain region 4b, and is set to a concentration at which a desired threshold value can be obtained. In the figure, 2 is an element isolation insulating film, 8 is an interlayer insulating film, and 9 is a metal wiring.
【０００３】なお、この種の技術に関連するものとし
て、Ｓ．Ｍ．Ｓｚｅ著「半導体デバイスの物理（Physic
s of Semiconductor Devices）」John Wiley&Sons 社発
行、４３３〜４３４頁（１９８１年）等が挙げられる。As a technique related to this type of technology, S. M. Sze, "Physic of Semiconductor Devices (Physic
s of Semiconductor Devices) ”, John Wiley & Sons, pp. 433-434 (1981) and the like.
【０００４】[0004]
【発明が解決しようとする課題】上記従来の技術は、素
子を微細化して高性能アナログ回路に使用する場合に問
題があった。つまり、アナログ回路では入出力の比例関
係、すなわち、リニアリティが重要である。フィードバ
ック回路を前提に考えると利得が大きく、かつ、リニア
リティのあるものが要求される。アンプの利得はトラン
ジスタの相互コンダクタンスと出力抵抗（ドレインコン
ダクタンスの逆数）の積で決定されるので、出力抵抗が
大きく、かつ、バイアス条件に対して一定である必要が
ある。従来の構造の素子を用いたアナログ回路では、微
細化すると出力抵抗が減少するため、許す限り長チャネ
ルのＭＩＳ型ＦＥＴを用いていたが、高速作動のために
はやはり微細化が必要である。微細化したＭＩＳ型ＦＥ
Ｔではドレイン出力抵抗が減少するため、微細化に見合
った利得の向上ができず、また、ドレイン電圧により出
力抵抗が大きく変化するため、リニアリティが悪化する
という問題があった。The above-mentioned conventional technique has a problem when the element is miniaturized and used in a high-performance analog circuit. That is, in analog circuits, the proportional relationship between input and output, that is, linearity is important. Considering a feedback circuit, it is required to have a large gain and linearity. Since the gain of the amplifier is determined by the product of the transconductance of the transistor and the output resistance (the reciprocal of the drain conductance), the output resistance must be large and constant with respect to the bias condition. In an analog circuit using an element having a conventional structure, the output resistance decreases as the device is miniaturized. Therefore, a long channel MIS FET is used as much as possible, but miniaturization is still necessary for high speed operation. Miniaturized MIS type FE
In T, the drain output resistance decreases, so that the gain cannot be improved in proportion to the miniaturization, and the output resistance largely changes depending on the drain voltage, which causes a problem that linearity deteriorates.
【０００５】本発明の第１の目的は、出力抵抗が大き
く、かつ、その値をバイアス条件によらず一定に保つこ
とのできるＭＩＳ型ＦＥＴを有する半導体装置を提供す
ることにある。本発明の第２の目的は、そのような半導
体装置の製造方法を提供することにある。A first object of the present invention is to provide a semiconductor device having a MIS type FET which has a large output resistance and can keep its value constant regardless of a bias condition. A second object of the present invention is to provide a method of manufacturing such a semiconductor device.
【０００６】[0006]
【課題を解決するための手段】上記第１の目的を達成す
るために、本発明の半導体装置のＭＩＳ型電界効果トラ
ンジスタは、そのチャネル領域を第１導電型とすると
き、チャネル領域の表面不純物濃度がドレイン領域側か
らソース領域側に近付くに従って高くなる第１導電型の
高濃度不純物領域を設けるようにしたものである。In order to achieve the first object, the MIS field effect transistor of the semiconductor device of the present invention has a surface region impurity of the channel region when the channel region has the first conductivity type. A first-conductivity-type high-concentration impurity region whose concentration increases from the drain region side toward the source region side is provided.
【０００７】この高濃度不純物領域は、チャネル領域の
ドレイン領域側あることが好ましい。この高濃度不純物
領域の表面不純物濃度の最大値は、チャネル領域の他の
部分の表面不純物濃度の１．２倍から２倍の範囲の値と
することが好ましい。チャネル領域のソース領域側の表
面不純物濃度は、所望のしきい値が得られる濃度とす
る。また、ドレイン領域と接する部分の表面不純物濃度
も、ソース領域側のそれとほぼ等しい濃度とすることが
好ましい。This high-concentration impurity region is preferably on the drain region side of the channel region. It is preferable that the maximum value of the surface impurity concentration of the high-concentration impurity region is in the range of 1.2 to 2 times the surface impurity concentration of the other part of the channel region. The surface impurity concentration on the source region side of the channel region is set to a concentration at which a desired threshold value can be obtained. Further, it is preferable that the surface impurity concentration of the portion in contact with the drain region is substantially equal to that on the source region side.
【０００８】また、上記第２の目的を達成するために、
本発明の半導体装置の製造方法は、第１導電型の半導体
基板上に、ゲート電極を形成し、ゲート電極のソース領
域が形成される側から、第１導電型の不純物を斜イオン
打ち込みして第１導電型の高濃度不純物領域を形成し、
上記の半導体装置を製造するようにしたものである。In order to achieve the second object,
According to the method of manufacturing a semiconductor device of the present invention, a gate electrode is formed on a semiconductor substrate of the first conductivity type, and impurities of the first conductivity type are obliquely ion-implanted from the side where the source region of the gate electrode is formed. Forming a high-concentration impurity region of the first conductivity type,
The above semiconductor device is manufactured.
【０００９】さらにまた、上記第２の目的を達成するた
めに、本発明の半導体装置の製造方法は、第１導電型の
半導体基板の表面近傍に、チャネル領域を構成するため
の第１導電型の不純物を導入し、ゲート絶縁膜とゲート
電極を形成し、ゲート電極のドレイン領域が形成される
側から、第１導電型の不純物を斜イオン打ち込みして高
濃度不純物領域を形成し、上記の半導体装置を製造する
ようにしたものである。Further, in order to achieve the above-mentioned second object, the method of manufacturing a semiconductor device of the present invention comprises a first conductivity type for forming a channel region near the surface of a first conductivity type semiconductor substrate. Is introduced to form a gate insulating film and a gate electrode, and first-conductivity-type impurities are obliquely ion-implanted from the side where the drain region of the gate electrode is formed to form a high-concentration impurity region. A semiconductor device is manufactured.
【００１０】[0010]
【作用】ドレイン出力抵抗を決める第１の要素はドレイ
ン電圧印加時のチャネル長変調である。これはドレイン
電圧とチャネルのピンチオフ点の間に印加される電圧に
よりチャネル領域が空乏化し、実質的なチャネル長が減
少してドレイン電流が増加するためである。本発明では
チャネル領域の、好ましくはドレイン領域側に、チャネ
ル領域よりも高濃度な不純物領域が存在するため、ドレ
イン電圧を印加しても空乏層が広がりにくく、ドレイン
電圧を印加するに従い、空乏層はより高濃度のチャネル
領域に広がっていくのでさらに空乏化がしにくくなる。
従ってドレイン電圧が高い領域でも出力抵抗の低下を抑
さえて、ドレイン電圧によらない一定の出力抵抗を得る
ことができる。The first factor that determines the drain output resistance is the channel length modulation when the drain voltage is applied. This is because the channel region is depleted by the voltage applied between the drain voltage and the pinch-off point of the channel, the substantial channel length is reduced, and the drain current is increased. In the present invention, since the impurity region having a higher concentration than that of the channel region exists in the channel region, preferably on the drain region side, the depletion layer hardly spreads even when the drain voltage is applied, and the depletion layer is increased as the drain voltage is applied. Is spread over a higher concentration channel region, so depletion becomes more difficult.
Therefore, it is possible to suppress a decrease in output resistance even in a region where the drain voltage is high, and to obtain a constant output resistance independent of the drain voltage.
【００１１】[0011]
【実施例】以下、本発明の実施例を図面を用いて説明す
る。実施例ではシリコンＭＯＳＦＥＴを用いて説明する
が、他の半導体材料を用いたＭＩＳ型ＦＥＴでも動作原
理は同じである。また、実施例では主にｎ形ＭＯＳＦＥ
Ｔを例に説明したが、用いる不純物を反対導電形に変え
れば、同様にｐ形ＭＯＳＦＥＴを形成することができ
る。Embodiments of the present invention will be described below with reference to the drawings. Although a silicon MOSFET is used for description in the embodiments, the operating principle is the same for MIS type FETs using other semiconductor materials. In the embodiment, the n-type MOSFE is mainly used.
Although T has been described as an example, a p-type MOSFET can be similarly formed by changing the impurities used to have opposite conductivity types.
【００１２】〈実施例１〉本発明の第１の実施例の半導
体装置の断面図を図１に示す。チャネル領域のドレイン
領域側に高濃度領域５が設けられ、ドレイン領域側から
チャネル領域の中央部にかけて基板表面の不純物濃度が
高くなっている。なお、高濃度領域５のソース側の端は
チャネル領域の中央部近傍よりソース領域側に寄ったと
ころにあってもよい。<First Embodiment> FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The high-concentration region 5 is provided on the drain region side of the channel region, and the impurity concentration on the substrate surface increases from the drain region side to the central portion of the channel region. The source-side end of the high-concentration region 5 may be located closer to the source region than the vicinity of the center of the channel region.
【００１３】この半導体装置の製造方法を図２を用いて
説明する。ｐ型のシリコン基板１を用い、通常のＭＯＳ
ＦＥＴと同様に素子分離領域２を形成する。通常ではこ
こでしきい値調整用のイオン打ち込みをウェーハ全面に
ウェーハに垂直に行なうが、本実施例ではそれを行なう
ことなく、熱酸化によりゲート絶縁膜１０を形成し、次
ぎにポリシリコンを２００ｎｍ堆積し、リンをイオン打
ち込みして高濃度ｎ型ポリシリコンとし、加工して幅
０．５μｍのゲート電極３とする。その後、ソース領域
が形成される側からボロンの９０ｋｅＶの４５度の斜め
イオン打ち込み行なう。イオン打ち込み量は２×１０12
／ｃｍ2とした。この工程により、しきい値調整を行な
うと同時に高濃度領域５が形成される。次ぎに、ソース
領域４ａ、ドレイン領域４ｂをヒ素のイオン打ち込みに
より形成し、以下、通常の通り、ＳｉＯ2を堆積して層
間絶縁膜８を形成し、金属配線９を形成する。A method of manufacturing this semiconductor device will be described with reference to FIG. Normal MOS using p-type silicon substrate 1
The element isolation region 2 is formed similarly to the FET. Normally, ion implantation for threshold adjustment is performed here on the entire surface of the wafer perpendicularly to the wafer, but in the present embodiment, without doing so, the gate insulating film 10 is formed by thermal oxidation, and then polysilicon of 200 nm is formed. After being deposited, phosphorus is ion-implanted to form high-concentration n-type polysilicon, and processed to form a gate electrode 3 having a width of 0.5 μm. Then, 45 ° oblique ion implantation of boron of 90 keV is performed from the side where the source region is formed. Ion implantation amount is 2 × 10 12
/ Cm 2 . By this step, the high concentration region 5 is formed at the same time when the threshold value is adjusted. Next, the source region 4a and the drain region 4b are formed by ion implantation of arsenic, and thereafter, as usual, SiO 2 is deposited to form the interlayer insulating film 8 and the metal wiring 9.
【００１４】このようにして形成された本実施例のチャ
ネル領域の表面不純物濃度を図４に示す。従来例ではチ
ャネル領域の表面不純物濃度は図４に点線で示すように
一定であるが、本実施例ではドレイン側からチャネル中
央方向にかけて基板表面濃度が高くなる濃度分布が形成
される。FIG. 4 shows the surface impurity concentration of the channel region of the present embodiment thus formed. In the conventional example, the surface impurity concentration of the channel region is constant as shown by the dotted line in FIG. 4, but in the present example, a concentration distribution in which the substrate surface concentration increases from the drain side to the channel center direction is formed.
【００１５】また、本実施例の電流電圧特性を図５に示
す。従来例ではドレイン電流が飽和領域内で大きく増加
し、かつ、高いドレイン電圧ではその増加が大きくなっ
ているのに対し、本実施例ではドレイン電流の増加が少
なく、かつ、一定であることが分かる。The current-voltage characteristics of this embodiment are shown in FIG. It can be seen that in the conventional example, the drain current greatly increases in the saturation region and increases at a high drain voltage, whereas in the present example, the increase in the drain current is small and constant. .
【００１６】図５の特性から出力抵抗とドレイン電圧と
の関係を抽出したのが図６である。本実施例では出力抵
抗が従来例の２倍近くあり、ドレイン電圧依存性も少な
い。これは高濃度領域５によりドレイン端からチャネル
の中央部にかけて濃度が増加する濃度分布が得られたた
めである。FIG. 6 shows the relationship between the output resistance and the drain voltage extracted from the characteristics shown in FIG. In this embodiment, the output resistance is almost twice as large as that of the conventional example, and the drain voltage dependency is small. This is because the high concentration region 5 provides a concentration distribution in which the concentration increases from the drain end to the central portion of the channel.
【００１７】〈実施例２〉本発明の第２の実施例の半導
体装置の断面図を図７に示す。本実施例は長チャネルの
ＭＯＳＦＥＴの例である。この半導体装置の製造方法の
実施例１と異なる点は次ぎの通りである。ゲート電極３
を形成する前にしきい値決定用のボロンのイオン打ち込
みを全面に行なう。ドーズ量は１．６×１０12／ｃｍ2
とした。ゲート絶縁膜１０、ゲート電極３を形成後、高
濃度領域５をドレイン側からボロンを４０ｋｅＶで４５
度斜めイオン打ち込みして形成する。ドーズ量は１×１
０12／ｃｍ2とした。この場合、しきい値はチャネルの
大部分を占めるソース側の領域で決定される。また、ゲ
ート電極幅は１μｍとした。本実施例によれば長チャネ
ルのＭＯＳＦＥＴでもドレイン側からチャネル中央部に
かけて濃度が高くなる分布が形成され、出力抵抗の向上
とバイアス依存性の低減が可能になる。<Embodiment 2> FIG. 7 shows a sectional view of a semiconductor device according to a second embodiment of the present invention. This embodiment is an example of a long channel MOSFET. The difference from the first embodiment of the method for manufacturing the semiconductor device is as follows. Gate electrode 3
Before the formation of boron, ion implantation of boron for threshold value determination is performed on the entire surface. Dose amount is 1.6 × 10 12 / cm 2
And After forming the gate insulating film 10 and the gate electrode 3, the high concentration region 5 is doped with boron at 40 keV from the drain side at 45 keV.
Formed by oblique ion implantation. Dose amount is 1 × 1
It was 0 12 / cm 2 . In this case, the threshold is determined in the source-side region which occupies most of the channel. The width of the gate electrode was 1 μm. According to this embodiment, even in a long-channel MOSFET, a distribution in which the concentration increases from the drain side to the central portion of the channel is formed, so that it is possible to improve the output resistance and reduce the bias dependence.
【００１８】〈実施例３〉本発明の第３の実施例の半導
体装置の断面図を図８に示す。本実施例ではパンチスル
ーストッパとして高濃度埋込層６を設け、さらに出力抵
抗を向上し、バイアス依存性を低減するため、高濃度領
域５を設けた。この半導体装置の製造は次ぎのようにし
て行なう。ゲート電極３を形成前に、高濃度埋込層６を
ボロンの１００ｋｅＶ、３×１０12／ｃｍ2のイオン打
ち込みで形成し、その後ゲート絶縁膜１０、ゲート電極
３を形成して、しきい値調整用に、ボロンをソース領域
側から９０ｋｅＶ、１×１０12／ｃｍ2で４５度斜めイ
オン打ち込みを行なう。これにより微細化しても出力抵
抗が大きく、かつ一定であり、パンチスルーを抑えて出
力抵抗の低減を防いだ半導体装置を得ることができた。<Embodiment 3> A sectional view of a semiconductor device according to a third embodiment of the present invention is shown in FIG. In this embodiment, the high-concentration buried layer 6 is provided as the punch-through stopper, and the high-concentration region 5 is provided to further improve the output resistance and reduce the bias dependence. This semiconductor device is manufactured as follows. Before the gate electrode 3 is formed, the high-concentration buried layer 6 is formed by ion implantation of boron with 100 keV and 3 × 10 12 / cm 2 , and then the gate insulating film 10 and the gate electrode 3 are formed to form a threshold voltage. For adjustment, boron is obliquely ion-implanted from the source region side at 90 keV and 1 × 10 12 / cm 2 at 45 °. As a result, it is possible to obtain a semiconductor device in which the output resistance is large and constant even when miniaturized, and punch-through is suppressed to prevent the output resistance from being reduced.
【００１９】〈実施例４〉本発明の第４の実施例とし
て、ＳＯＩ構造の半導体装置の例を図９に示す。本実施
例では基板絶縁膜７を持つＳＯＩ基板を用いてまず素子
分離領域２を形成し、次にゲート絶縁膜１０を形成す
る。ポリシリコンをウェーハ全面に堆積してイオン打ち
込みを行なった後、ゲート電極３に加工する。しきい値
調整用と高濃度領域５の形成のために、ソース側からボ
ロンの９０ｋｅＶ、４５度斜めイオン打ち込みを行な
う。ドーズ量は２×１０12／ｃｍ2とした。これにより
微細化しても出力抵抗が大きく、かつ一定であり、パン
チスルーを抑えて出力抵抗の低減を防いだ半導体装置を
得ることができた。<Embodiment 4> As a fourth embodiment of the present invention, an example of a semiconductor device having an SOI structure is shown in FIG. In this embodiment, the SOI substrate having the substrate insulating film 7 is used to first form the element isolation region 2 and then the gate insulating film 10. After depositing polysilicon on the entire surface of the wafer and performing ion implantation, the gate electrode 3 is processed. In order to adjust the threshold value and to form the high-concentration region 5, a 45 ° oblique ion implantation of boron is performed from the source side at 90 keV. The dose amount was 2 × 10 12 / cm 2 . As a result, it is possible to obtain a semiconductor device in which the output resistance is large and constant even when miniaturized, and punch-through is suppressed to prevent the output resistance from being reduced.
【００２０】〈実施例５〉本発明の第５の実施例とし
て、ＣＭＯＳ（相補型ＭＯＳトランジスタ）構造の例を
図１０に示す。この半導体装置の製造方法は、通常のＣ
ＭＯＳプロセスに従い、ｐウェル領域１１とｎウェル領
域１２を形成した後、素子分離領域２を形成する。ゲー
ト酸化で酸化膜１０を形成後、ポリシリコンをウェーハ
全面に堆積してホトリソグラフィにより、ＮＭＯＳには
リンでイオン打ち込みを行ない、ＰＭＯＳにはボロンで
イオン打ち込みを行なって、それぞれ高濃度ｎ型、ｐ型
ポリシリコンとした後にゲート電極３に加工する。<Fifth Embodiment> FIG. 10 shows an example of a CMOS (complementary MOS transistor) structure as a fifth embodiment of the present invention. This semiconductor device manufacturing method is based on the conventional C
According to the MOS process, after the p well region 11 and the n well region 12 are formed, the element isolation region 2 is formed. After the oxide film 10 is formed by gate oxidation, polysilicon is deposited on the entire surface of the wafer and photolithography is performed to ion-implant the NMOS with phosphorus and ion-implant the PMOS with boron. After forming the p-type polysilicon, the gate electrode 3 is processed.
【００２１】しきい値調整用と同時に高濃度領域５、１
３を形成するために、ＮＭＯＳではボロンを９０ｋｅ
Ｖ、２×１０12／ｃｍ2の条件でソース側から４５度斜
めイオン打ち込みを行ない、ＰＭＯＳではリンを２２０
ｋｅＶ、２×１０12／ｃｍ2の条件でソース側から４５
度斜めイオン打ち込みを行なう（図１０（ａ））。High density regions 5 and 1 for threshold adjustment
In order to form 3, the boron is 90 ke in the NMOS.
Under the condition of V, 2 × 10 12 / cm 2 , oblique ion implantation is performed at 45 ° from the source side, and phosphorus is 220
keV, 45 from the source side under the condition of 2 × 10 12 / cm 2
Angled ion implantation is performed (FIG. 10A).
【００２２】次にゲート電極をマスクとして、ＮＭＯＳ
には砒素をイオン打ち込みしてソース領域４ａ、ドレイ
ン領域４ｂを形成し、ＰＭＯＳにはインジウムをイオン
打ち込みしてソース領域１４ａ、ドレイン領域１４ｂを
形成する（図１０（ｂ））。Next, using the gate electrode as a mask, the NMOS
Arsenic is ion-implanted into the source region 4a and the drain region 4b, and indium is ion-implanted into the PMOS to form the source region 14a and the drain region 14b (FIG. 10B).
【００２３】その後層間絶縁膜８を堆積し、コンタクト
穴を開け、金属配線９を付けて完成する（図１０
（ｃ））。本実施例によれば、出力抵抗が大きく、かつ
バイアス条件に対しても一定で、アナログ回路に適した
ＣＭＯＳ構造を提供することができた。After that, an interlayer insulating film 8 is deposited, contact holes are opened, and metal wiring 9 is attached (FIG. 10).
(C)). According to the present embodiment, it is possible to provide a CMOS structure having a large output resistance and a constant bias condition, which is suitable for an analog circuit.
【００２４】[0024]
【発明の効果】以上に説明したように、本発明によれ
ば、微細化した半導体装置においても出力抵抗が大き
く、かつバイアス条件に寄らず一定の値が得られるの
で、高速で利得が大きく、かつリニアリティの高いアナ
ログ回路の動作が可能になる。また、このような半導体
装置を容易に製造することができる。As described above, according to the present invention, even in a miniaturized semiconductor device, the output resistance is large and a constant value can be obtained regardless of the bias condition, so that the gain is high at a high speed, In addition, it is possible to operate an analog circuit with high linearity. Further, such a semiconductor device can be easily manufactured.
【図１】本発明の第１の実施例の半導体装置の断面図で
ある。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.
【図２】第１の実施例の半導体装置の製造方法を示す図
である。FIG. 2 is a diagram showing the method of manufacturing the semiconductor device according to the first embodiment.
【図３】従来の半導体装置の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device.
【図４】表面不純物濃度のチャネル方向の分布を示す図
である。FIG. 4 is a diagram showing a distribution of surface impurity concentrations in a channel direction.
【図５】第１の実施例と従来の半導体装置のドレイン電
流−ドレイン電圧特性を示す図である。FIG. 5 is a diagram showing drain current-drain voltage characteristics of the first embodiment and the conventional semiconductor device.
【図６】第１の実施例と従来の半導体装置の出力抵抗の
ドレイン電圧依存性を示す図である。FIG. 6 is a diagram showing the drain voltage dependence of the output resistance of the first embodiment and the conventional semiconductor device.
【図７】本発明の第２の実施例の半導体装置の断面図で
ある。FIG. 7 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
【図８】本発明の第３の実施例の半導体装置の断面図で
ある。FIG. 8 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
【図９】本発明の第４の実施例のＳＯＩ構造を適用した
半導体装置の断面図である。FIG. 9 is a sectional view of a semiconductor device to which the SOI structure of the fourth embodiment of the present invention is applied.
【図１０】本発明の第５の実施例のＣＭＯＳ構造を適用
した半導体装置の断面図である。FIG. 10 is a sectional view of a semiconductor device to which a CMOS structure of a fifth embodiment of the present invention is applied.
１…シリコン基板 ２…素子分離領域 ３…ゲート電極 ４ａ、１４ａ…ソース領域 ４ｂ、１４ｂ…ドレイン領域 ５、１３…高濃度領域 ６…高濃度埋込層 ７…基板絶縁膜 ８…層間絶縁膜 ９…金属配線 １０…ゲート絶縁膜 １１…ｐウェル領域 １２…ｎウェル領域 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Element isolation region 3 ... Gate electrode 4a, 14a ... Source region 4b, 14b ... Drain region 5, 13 ... High concentration region 6 ... High concentration embedding layer 7 ... Substrate insulating film 8 ... Interlayer insulating film 9 Metal wiring 10 Gate insulating film 11 P well region 12 N well region
Claims (8)
間に形成された第１導電型のチャネル領域の表面不純物
濃度が、上記ドレイン領域側から上記ソース領域側に近
付くに従って高くなる高濃度不純物領域を具備するＭＩ
Ｓ型電界効果トランジスタを有することを特徴とする半
導体装置。1. A high concentration in which a surface impurity concentration of a channel region of a first conductivity type formed between a source region and a drain region of a second conductivity type becomes higher as it approaches from the drain region side to the source region side. MI with impurity region
A semiconductor device having an S-type field effect transistor.
高濃度不純物領域の表面不純物濃度の最大値は、チャネ
ル領域の他の部分の表面不純物濃度の１．２倍から２倍
の範囲の値であることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the maximum value of the surface impurity concentration of the high-concentration impurity region is 1.2 times to 2 times the surface impurity concentration of the other part of the channel region. A semiconductor device characterized by:
て、上記高濃度不純物領域は、上記チャネル領域のドレ
イン領域側にあることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the high concentration impurity region is on the drain region side of the channel region.
体装置において、上記チャネル領域の下に、第１導電型
の高濃度不純物層を有することを特徴とする半導体装
置。4. The semiconductor device according to claim 1, further comprising a first-conductivity-type high-concentration impurity layer below the channel region.
体装置において、上記ＭＩＳ型電界効果トランジスタ
は、同一基板上に少なくとも２個配置され、その内の１
個のＭＩＳ型電界効果トランジスタはｐチャネル絶縁ゲ
ート型電界効果トランジスタであり、他の１個のＭＩＳ
型電界効果トランジスタはｎチャネル絶縁ゲート型電界
効果トランジスタであることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein at least two MIS field effect transistors are arranged on the same substrate, and one of them is arranged.
One MIS field effect transistor is a p-channel insulated gate field effect transistor, and the other MIS field effect transistor is
Type field effect transistor is an n-channel insulated gate field effect transistor.
体装置において、上記ＭＩＳ型電界効果トランジスタ
は、半導体基板上に配置された絶縁膜上の半導体薄膜に
設けられたことを特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein the MIS field effect transistor is provided in a semiconductor thin film on an insulating film arranged on a semiconductor substrate. Semiconductor device.
を形成する工程と、該ゲート電極のソース領域が形成さ
れる側から、第１導電型の不純物を斜イオン打ち込み
し、チャネル領域に第１導電型の高濃度不純物領域を形
成する工程とを有し、請求項１から６のいずれか一に記
載の半導体装置を製造することを特徴とする半導体装置
の製造方法。7. A step of forming a gate electrode on a semiconductor substrate of the first conductivity type, and obliquely ion-implanting impurities of the first conductivity type from the side where the source region of the gate electrode is formed to form a channel region. And a step of forming a high-concentration impurity region of the first conductivity type, the method for manufacturing a semiconductor device according to claim 1.
ャネル領域を構成するための第１導電型の不純物を導入
する工程と、ゲート絶縁膜とゲート電極を形成する工程
と、該ゲート電極のドレイン領域が形成される側から、
第１導電型の不純物を斜イオン打ち込みし、チャネル領
域に高濃度不純物領域を形成する工程とを有し、請求項
１から６のいずれか一に記載の半導体装置を製造するこ
とを特徴とする半導体装置の製造方法。8. A step of introducing an impurity of the first conductivity type for forming a channel region near the surface of a semiconductor substrate of the first conductivity type, a step of forming a gate insulating film and a gate electrode, and the gate. From the side where the drain region of the electrode is formed,
Forming a high-concentration impurity region in the channel region by obliquely implanting a first conductivity type impurity, and manufacturing the semiconductor device according to claim 1. Manufacturing method of semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7023258A JPH08222729A (en) | 1995-02-13 | 1995-02-13 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7023258A JPH08222729A (en) | 1995-02-13 | 1995-02-13 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08222729A true JPH08222729A (en) | 1996-08-30 |
Family
ID=12105585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7023258A Pending JPH08222729A (en) | 1995-02-13 | 1995-02-13 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08222729A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007287945A (en) * | 2006-04-18 | 2007-11-01 | Mitsubishi Electric Corp | Thin film transistor |
| JP2008060216A (en) * | 2006-08-30 | 2008-03-13 | New Japan Radio Co Ltd | Semiconductor device, and its manufacturing method |
| JP2011165764A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Method of manufacturing semiconductor device, and semiconductor device |
| CN104900529A (en) * | 2015-04-23 | 2015-09-09 | 中国电子科技集团公司第十三研究所 | Method and structure for improving linearity of grid control transistor |
-
1995
- 1995-02-13 JP JP7023258A patent/JPH08222729A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007287945A (en) * | 2006-04-18 | 2007-11-01 | Mitsubishi Electric Corp | Thin film transistor |
| JP2008060216A (en) * | 2006-08-30 | 2008-03-13 | New Japan Radio Co Ltd | Semiconductor device, and its manufacturing method |
| JP2011165764A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Method of manufacturing semiconductor device, and semiconductor device |
| CN104900529A (en) * | 2015-04-23 | 2015-09-09 | 中国电子科技集团公司第十三研究所 | Method and structure for improving linearity of grid control transistor |
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