JPH08221982A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To reduce current consumption in a DRAM when rewriting and precharging. CONSTITUTION: A pair of switch circuits TG1, TG2 connected between bit lines BL, the inverse of BL and sense nodes S, the inverse of S of a sense amplifier SA is provided, and the switch circuit, e.g. the TG1 of the bit line BL to which a selected memory cell MC is connected is made to be on-state, and the other side switch circuit TG2 is made to be off-state, and thereafter, the rewrite of the memory cell is performed by amplifying a voltage outputted from the memory cell MCn to the bit line BL is amplified by the sense amplifier SA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for reducing current consumption during rewriting and precharging of memory cells.

[0002]

2. Description of the Related Art Generally, semiconductor memory devices (DRAM, etc.)
As shown in FIG. 3, the memory cell MC is composed of one capacitor and one cell transistor, and data is stored depending on the presence / absence of charges accumulated in the capacitor. Then, reading or rewriting is performed by the word line W.
In response to the rise of L, the cell transistor of the selected memory cell MC is turned on, and the bit lines BL, * B
This is performed by amplifying the minute voltage output to L by the sense amplifier SA.

Conventionally, in order to shorten the access time,
A pair of MOS transistors QT1 and QT2 are inserted between the bit lines BL and * BL and the sense amplifier SA.
That is, as shown in FIG. 4, when the data is read to the bit lines BL and * BL and the sensing operation starts, the control signal φT falls to turn off QT1 and QT2.

As a result, the sense amplifier SA and the bit lines BL and * BL are separated, the sensing operation is performed at a high speed, and then the control signal φT is raised again, so that the QT
The memory cell is rewritten by turning on 1 and QT2 and connecting the bit lines BL and * BL.

[0005]

However, at the time of rewriting, the sense amplifier SA causes the two bit lines BL and * BL to fully swing (Vss or Vcc).
In addition, after the rewriting is completed, it is necessary to precharge again to the initial 1/2 Vcc, which causes a problem that the current consumption is very large.

[0006]

According to the present invention, in order to solve the above-mentioned problems, as shown in FIG. 1, bit lines BL, * B are provided.
A pair of switch circuits TG1 and TG2 connected between L and the sense nodes S and * S of the sense amplifier SA are provided,
Bit line B to which the selected memory cell MC is connected
The switch circuit of L, for example, TG1 is turned on, the other switch circuit TG2 is turned off, and then the voltage output from the memory cell MCn to the bit line BL is amplified by the sense amplifier SA, whereby I tried to rewrite.

The present invention also relates to the switch circuits TG1 and T
By using the lowest address for G2, the switch circuit TG1 of the bit line BL to which the selected memory cell MCn is connected is turned on.

[0008]

According to the present invention, the selected memory cell MCn
Only the bit line BL connected to the switch circuit T
It is connected to the sense amplifier SA via G1 and the other bit line * BL remains disconnected. Therefore, as shown in FIG. 2, the other bit line * BL maintains 1/2 Vcc at the time of precharging, and only the bit line BL swings to Vss or Vcc according to the stored data. Therefore, the current consumption during rewriting and precharging can be reduced by half.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, the semiconductor memory device according to the present embodiment has bit lines BL, *
A pair of switch circuits TG1 and TG2 are provided between BL and the sense nodes S and * S of the sense amplifier SA, and a switch circuit of the bit line BL to which the selected memory cell MCn is connected, for example, TG1 is turned on. At the same time, the other switch circuit TG2 is turned off, and then the voltage output from the memory cell MCn in the figure to the bit line BL is amplified by the sense amplifier SA to rewrite the memory cell. It is a thing.

On / off control of the switch circuits TG1 and TG2 is performed by using the lowest addresses A and * A as a control signal to switch the switch circuit TG1 of the bit line BL to which the selected memory cell MC is connected. Only tried to turn on. That is, in the memory cell, MCn is BL, MCn + 1 is * BL, MCn + in the order of addresses.
If 2 is connected to BL, MCn + 3 is connected to * BL, etc., and the bit lines BL and * BL are alternately connected, the memory selected depending on whether the lowest address A is "0" or "1". It becomes possible to selectively turn on the switch circuit of the bit line to which the cell is connected.

The rewriting operation of the above semiconductor memory device will be described in detail with reference to FIG. First, prior to rewriting, the bit lines BL and * BL are set to 1/2 Vcc (power supply voltage Vc by a bit line precharge circuit (not shown).
c) and the ground voltage Vss). Then, the word line WL selected by the address signal
(N) rises, the memory cell MCn is selected, and data is output to the bit line BL.

At this time, the switch circuit TG1 is turned on and the switch circuit TG2 is turned off according to the change of the lowest address A, * A, so that only the bit line BL is connected to the sense node S of the sense amplifier SA. Connected.
Then, the activation signals SAD, * SA of the sense amplifier SA
In response to the change in D, the sense amplifier SA amplifies the voltage of the bit line BL to Vss or Vcc, and the memory cell MCn is rewritten. On the other hand, the other bit line * BL maintains the level of 1/2 Vcc.

Therefore, since the sense amplifier SA only needs to amplify one bit line, the current consumption at the time of rewriting can be halved, and the current consumption at the time of precharging can also be halved. Further, since the switch circuits TG1 and TG2 are composed of CMOS transfer gates, they are not easily affected by the back gate bias effect. Therefore, when the bit line BL and the sense amplifier SA are connected, the sensing operation can be performed at high speed. . Therefore, it is particularly suitable for a DRAM having a low power supply voltage of about 3V.

[0014]

As described above, according to the semiconductor memory device of the present invention, only the bit line BL to which the memory cell MCn selected at the time of rewriting of the memory cell is connected, via the switch circuit TG1. Is connected to the sense amplifier SA and the bit line * BL on the other side is disconnected from the sense amplifier to perform the sensing operation, and the bit line * BL on the other side maintains 1/2 Vcc at the time of precharging. Only the line BL has V depending on the stored data.
Swing to ss or Vcc. Therefore, the current consumption at the time of rewriting and at the time of precharging can be halved, and the generation of noise can be prevented.

Furthermore, according to the present invention, the switch circuit T
Since the on / off control of G1 and TG2 is performed using the lowest address signal, there is an advantage that the circuit configuration is simple. Furthermore, the switch circuits TG1, TG2
Since it is composed of a CMOS transfer gate, it is unlikely to be affected by the back gate bias effect. Therefore, when the bit line BL and the sense amplifier SA are connected, there is an advantage that the sensing operation can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor memory device according to the example of the present invention.

FIG. 3 is a circuit diagram illustrating a semiconductor memory device according to a conventional example.

FIG. 4 is a waveform diagram illustrating an operation of a semiconductor memory device according to a conventional example.

[Explanation of symbols]

 BL, * BL Bit line SA Sense amplifier S, * S Sense node SAD, * SAD Sense amplifier control signal MCn Memory cell WLn Word line TG1, TG2 Switch circuit A, * A Lowest address signal

Claims (3)

[Claims] 1. A plurality of memory cells, a pair of bit lines connected to the plurality of memory cells, a sense amplifier connected between the bit lines, and the bit line and a sense node of the sense amplifier. A pair of switch circuits connected to the bit line, the switch circuit of the bit line to which the selected memory cell is connected is turned on and the other switch circuit is turned off, and then the bit line from the memory cell is turned on. A memory cell is rewritten by amplifying the voltage output to the memory cell by the sense amplifier. 2. A plurality of memory cells, a pair of bit lines in which the plurality of memory cells are alternately connected in the order of addresses, a sense amplifier connected between the bit lines, and the bit line and the sense amplifier. A pair of switch circuits connected to a sense node, and a lowest address line controlling the pair of switch circuits, and a bit to which a selected memory cell is connected according to the lowest address The switch circuit of the line is turned on and the other switch circuit is turned off, and then the voltage output from the memory cell to the bit line is amplified by the sense amplifier to rewrite the memory cell. A characteristic semiconductor memory device. 3. The dynamic semiconductor memory device according to claim 1, wherein the pair of switch circuits are composed of CMOS transfer gates.