JPH08221277A - Emulation device - Google Patents

Abstract

(57) [Summary] [Purpose] To reduce overhead and increase emulation speed. [Structure] A plurality of processors 0, 1, ..., M-1 each of which translates / executes an instruction and one instruction of a machine language instruction sequence TI executed by a target computer is extracted,
A plurality of processors 0, 1, ..., M-1 are provided so that instructions whose execution order is continuous are assigned to different processors.
And a plurality of processors 0, 1,
..., parallel emulation means 101 for operating M-1 in parallel, and execution synchronization control means 102 for controlling the instruction execution timing in each processor so that the instructions are executed in the order in which they should be executed .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention extracts an instruction from a machine language level instruction sequence executed by a computer to be emulated (hereinafter referred to as a target computer), translates the instruction one by one, and executes the instruction to operate the target computer. The present invention relates to an emulation device that simulates.

[0002]

2. Description of the Related Art When an instruction sequence of a target computer is translated and executed by an emulation device having a different instruction set architecture such as instruction set content, data expression format, interrupt mechanism, etc., to simulate the operation of the target computer. , Its emulation method is
An interpret method that sequentially extracts and translates machine language instructions one by one from the machine language instruction sequence executed on the target computer, and first retrieves and translates all machine language instruction sequences executed on the target computer. , And the compilation method to be executed.

FIG. 10 is a flow chart showing an emulation procedure by a conventional emulation device adopting the interpret method. The conventional emulation device is composed of a computer having one processor and software for emulation, and extracts one instruction from a machine language level instruction sequence executed in the target computer (S31) and translates the instruction (S32). The translated instruction is executed (S33). The above steps S31 to S33 are repeated for all the instructions to end the emulation.

FIG. 11 is a sequence diagram of emulation by a conventional emulation device when the instruction sequence of the target computer is, for example, eight instructions executed in the order of 0, 1, 2, ... The left side is the time axis. In this sequence diagram, the basic unit of time is 1t, and by the time the execution of one instruction is completed, it takes 1t for instruction fetch, 24t for translation of instruction, and 8t for execution of instruction, 33t in total. , Then instructions 0-7
It takes 264t (= 33t × 8) to complete.
That is, as is apparent from the figure, the emulation time in the conventional emulation device increases in proportion to the number of instructions in the instruction sequence of the target computer.

[0005]

As described above, the conventional emulation device has a problem that the emulation speed is low because the overhead of fetching and translating an instruction is large compared to the execution time of the instruction. is there.

The present invention has been made in order to solve such a problem, and by emulating in parallel using a plurality of processors, the overhead of fetching and translating an instruction with respect to the execution time of the instruction. It is intended to provide an emulation device having a small size and a high emulation speed.

[0007]

An emulation apparatus according to the first aspect of the present invention extracts instructions one by one from a machine language level instruction sequence executed by a computer to be emulated, translates the instructions, and sequentially executes the instructions in the order in which they should be executed. In the emulation device that simulates the operation of the computer to be emulated, a plurality of processors each of which translates and executes an instruction, and one instruction from the instruction sequence
Each instruction is fetched one by one, and each instruction of the instruction sequence is assigned to a processor different from the processor to which the instruction to be executed immediately before the instruction is assigned. Means for allocating one of the plurality of processors, means for operating the plurality of processors in parallel, and controlling the execution timing of instructions in each of the plurality of processors so that the instruction sequence is executed in the order in which it should be executed. And means.

The emulation apparatus of the second invention extracts the instructions one by one from the machine language level instruction sequence executed by the computer to be emulated, translates them, and sequentially executes them in the order in which they should be executed. In an emulation device simulating the operation of a computer, each has means for extracting an instruction from the instruction sequence one by one, and means for translating and executing each instruction and acquiring an instruction to be executed by itself.
The means for acquiring an instruction is a means for not acquiring an instruction in the next execution order of the acquired instruction, a means for operating the plurality of processors in parallel, and the instruction sequence is executed. Means for controlling the execution timing of instructions in each of the plurality of processors so that the instructions are executed in a power order.

The emulation device of the third invention is the first emulation device.
Alternatively, in the second invention, the means for controlling the execution timing of the instruction of each processor includes means for detecting the completion of execution of the instruction in each processor, and the execution of the instruction by each processor is executed immediately before the instruction. It is a means for controlling to be started after the execution of the instruction to be executed is completed.

[0010]

The emulation apparatus of the first invention takes out one instruction at a time from the machine language level instruction sequence executed by the computer to be emulated, and each instruction is assigned the instruction to be executed immediately before that. Each instruction is assigned to one of a plurality of processors so that it can be assigned to a processor different from the processor, and the plurality of processors are operated in parallel to translate and execute the assigned instructions, and each processor is While each processor is executing one instruction, it interprets the instruction assigned to itself, which is in the execution order after the instruction being executed, and controls the execution timing of the instruction in each processor, The emulation is performed so that one processor continuously executes the instruction sequence in the order of execution. Therefore, the overhead other than the execution of instructions is reduced, and emulation is performed at high speed.

The emulation apparatus of the second invention takes out one instruction at a time from the machine language level instruction sequence executed by the computer to be emulated and acquires the instruction from each processor side. Instructions are acquired so as not to acquire instructions whose execution order is continuous, and a plurality of processors operate in parallel to translate and execute the acquired instructions, and each processor executes one instruction by another processor. During execution, it translates the instructions assigned to itself and in the order of execution after the instruction being executed, and controls the execution timing of the instructions in each processor so that one processor processes the instruction sequence. Emulation is performed as if they were continuously executed in the order in which they should be executed. Therefore, the overhead other than the execution of instructions is reduced, and emulation is performed at high speed.

The emulation apparatus of the third invention further controls the completion of execution of an instruction by the processor which is executing the instruction in the execution order immediately preceding the instruction to be executed when controlling the execution timing of the instruction in each processor. Detect and
The execution of the instruction by each processor is controlled to start after the execution of the instruction to be executed immediately before is completed. As a result, even if the instruction sequence includes an instruction that performs an operation based on the execution result of the immediately preceding instruction, the correct execution result can be obtained.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a block diagram showing the configuration of an emulation device of the present invention (hereinafter referred to as the device of the present invention). In the figure, TI is a machine language level instruction sequence executed by the target computer, and the instruction sequence TI is 0, 1, 2,
, N-1 are executed in the order of N-1, and each instruction is managed by an instruction number corresponding to the execution order of the instruction. The apparatus of the present invention has M processors, each of which translates and executes instructions, where M processors are 0 to
It is managed by the processor number of (M-1). The multiprocessor emulation means 10 fetches the instruction sequence TI one instruction at a time in the order of execution, that is, in the order of instruction numbers, and retrieves each instruction.
In order to assign the instruction to be executed immediately before each instruction to a processor different from the assigned processor, for example, they are assigned to processors 0 to (M-1) in the order of the processor numbers.

Multiprocessor emulation means 10
Is a parallel emulation means 101 for operating a plurality of processors 0 to (M-1) in parallel to realize parallel emulation; and a plurality of instruction emulations in order to be executed. Processor 0- (M-
The execution synchronization control means 102 for controlling the execution timing of the instruction in each of 1) is included. FIG. 2 is a schematic flowchart of the emulation procedure of the device of the present invention. The multiprocessor emulation means 10 fetches instructions one by one from the instruction sequence TI in the order of execution (S1), for example, sequentially assigns the fetched instructions in processor number order, that is, executes each instruction one instruction before each instruction. The instruction to be assigned is assigned to a processor different from the assigned processor (S2). FIG. 3 is a conceptual diagram of the allocation state when the instructions are allocated in order of processor number. The parallel emulation means 101 operates a plurality of processors 0 to (M-1) in parallel (S3), and the execution synchronization control means 102 controls the instruction execution timing in each processor (S).
4).

On the other hand, the processors 0 to (M-1) have instruction acquiring means 0a, 1a, 2a, ..., (M-1) a, respectively, and the instruction numbers to be assigned to themselves are used for emulation. Based on the number and own processor number,
It is calculated by a definition formula described later and obtained from the multiprocessor emulation means 10. Furthermore, processors 0 to
(M-1) is a command translation means 1 for translating the acquired command.
, (M-1) b, and instruction executing means 1c, 2c, ..., (M-1) c for executing the translated instruction.

The definition formula for the instruction acquisition means 0a, 1a, 2a, ..., (M-1) a to determine the acquisition instruction is p
s, processor number pn (starting from 0), translation of 1 instruction
When the step number of the process in each processor that has one step of execution is sn (starting from 0), ps × sn + pn
It is represented by. FIG. 4 is a diagram showing a procedure in which when the number of processors used for emulation is four, the processor with the processor number 2 obtains an instruction to be executed by itself based on the above-described definition formula. In step 0, ps × sn + pn = 0 × 4 + 2 = 2 is obtained from the above definition formula, so that the instruction 2 is acquired, and the instruction translation means 2b and the instruction execution means are acquired.
2c translates and executes instruction 2. Further, in the next step 1, ps × sn + pn = 1 × 4 + 2 from the above definition formula.
= 6, the instruction 6 is acquired, and the instruction translation means 2b and the instruction execution means 2c translate and execute the instruction 6. Therefore, the respective instruction acquisition means 0a of the processors 0 to (M-1),
1a, 2a, ..., (M-1) a do not continuously acquire the next instruction in the execution order after the acquired instruction.

The instruction execution timing has a dependency relationship between instructions, such as when a certain instruction performs an operation based on the execution result of the immediately preceding instruction, and the instruction execution order must be accurately maintained. Control is necessary when the next instruction cannot be executed until the previous instruction is completed. Therefore, the execution synchronization control means 102 is an instruction execution means.
Before or after the instruction execution by 1c, 2c,…, (M-1) c, whether the completion of the previous order instruction execution by another processor is detected and whether its own processor may start the instruction execution "Instruction execution start procedure" for confirming, and "Instruction execution completion procedure" for notifying other processors of completion of instruction execution
Is executed by the processor that is going to execute the instruction, so that the execution timing of the instruction in each processor is controlled. The “instruction execution start procedure” and the “instruction execution completion procedure” are executed by each processor each time each processor emulates each instruction.

Further, the execution synchronization control means 102 is such that, when a certain processor attempts to execute an instruction, an instruction being executed by another processor is executed before the instruction which one processor tries to execute. In order to confirm whether or not the instruction is a necessary instruction, a signed integer type synchronization control table 102a composed of a number of elements corresponding to the number of processors 0 to (M-1) is set to a plurality of processors 0 to (M- 1) All values of each element of the synchronization control table 102a defined in the "synchronization control table definition procedure" and the "synchronization control table definition procedure" defined in the mutually referable storage area are set to "0". Perform the "synchronization control table initialization procedure" to initialize the values of the elements of the synchronization control table 102a,
Updated every time the "command execution completion procedure" is performed. The "synchronization control table definition procedure" and the "synchronization control table initialization procedure" are executed only once at the beginning of emulation. FIG. 5 shows the synchronization control table 10 when the number of processors used for emulation is four.
It is a conceptual diagram of 2a.

FIG. 6 is a diagram showing a procedure for translating / executing an instruction acquired by the processor having the processor number 2 to emulate it when the number of processors used for emulation is four. In step 0, command acquisition means
2a calculates an instruction number to be obtained and obtains it from the multiprocessor emulation means 10, the instruction translation means 2b translates the obtained instruction, and the instruction execution means 2c firstly provides the "instruction provided by the execution synchronization control means 102". Execution start procedure "
And executing the translated instruction at the timing when the execution of the instruction can be started, and then the execution synchronization control means 102
By executing the “instruction execution completion procedure” provided by, the other processors are notified of the completion of execution of the instruction.

FIG. 7 is a flowchart showing the procedure of the "instruction execution start procedure". The variable i is a variable for substituting the instruction number, the variable e is a variable for substituting the processor number (starting from zero), and the variable v is a variable for substituting the values of the elements of the synchronization control table 102a. "Number of instruction to execute-1"
Is assigned to the variable i (S11), and it is determined whether the number of the processor which is to execute the instruction is "0" or "other than 0" (S11).
12). When the processor number is "0", "the number of processors-1" is assigned to the variable e (S13), while when the processor number is "other than 0", "processor number-1" is assigned to the variable e. Yes (S14).

Next, the value of the e-th element of the synchronization control table 102a, that is, the value of the element corresponding to the number of the processor that should execute the instruction immediately before the instruction to be executed is set to the variable v.
(S15), and the value of the variable i is compared with the value of the variable v (S16). When the value of the variable v is larger than the value of the variable i (i ≧ v is false), that is, when the execution of the instruction to be executed immediately before has been completed, the execution of the instruction is started. When the value of the variable v is equal to or smaller than the value of the variable i (i ≧ v is true), that is, when the execution of the instruction to be executed immediately before is not completed, the value of the variable v is The execution of the instruction is waited until it becomes larger than the value of the variable i (S17).

FIG. 8 is a flow chart showing the procedure of the "instruction execution completion procedure". The processor number of its own is substituted into the variable e (S21), and "the instruction number of the executed instruction + the number of processors" is substituted into the variable v (S22). V is set in the e-th element of the synchronization control table 102a (S23), and the procedure ends. That is, since the value of the element of the synchronization control table 102a is updated to the instruction number to be executed in the next step of the processor at the time when the execution of the instruction is completed, each processor has the above-mentioned “instruction execution start procedure”. At
By referring to the value of the element of the synchronization control table 102a corresponding to the processor that should execute the instruction immediately before, it is possible to confirm whether or not the execution of the instruction immediately before is completed.

Next, the specific emulation time of the device of the present invention when the four processors shown in FIG. 9 are used is a sequence diagram of the conventional device using one processor which has already been described with reference to FIG. This will be described in comparison with the emulation time in. Similar to the above, assuming that the basic unit of time is 1t, 3t is used to obtain an emulation target instruction, and 1t is used to fetch an emulation target instruction.
It requires a total of 44t, 24t for translating instructions, 5t for "instruction execution start procedure", 8t on average for executing instructions, and 3t for "instruction execution completion procedure".

In the conventional device, for emulation of each instruction
Since 33t is required, the overhead other than the execution of the instruction is 76% (= (33-8) / 33). In addition, since the conventional device requires 264t to complete the execution of 8 instructions 0 to 7, the overhead is 75% (= (264-
8 × 8) / 264). If the instruction fetch time is R, the average time to translate the instruction is T, the average time to execute the translated instruction is E, and the number of instructions is N, the overhead is ((R + T) × N). / ((R + T +
E) × N). Therefore, in the conventional device, it can be seen that the overhead is constant regardless of the number of executed instructions.

Since the device of the present invention requires 44t to emulate each instruction, it requires 11t more time than the conventional device, and the overhead is 82% (= (44-
8) / 44)). This is because the “instruction execution start procedure” and the “instruction execution completion procedure” which are not available in the conventional apparatus are performed. However, 1 is required to complete the execution of 8 instructions 0 to 7.
Only 21t time is required, and it is possible to reduce the time by 143t compared to the conventional device, and the overhead is 47% (= (121-8
× 8/121)) and can be kept low. The above is the time to acquire an instruction, the time to fetch an instruction is R, the average time to translate an instruction is T, the average time to execute a translated instruction is E, and the "instruction execution start procedure" is executed. If the time is S, the time to execute the “instruction execution completion procedure” is F, and the number of instructions is N, the overhead is (G + R + T +
S + (F × N)) / (G + R + T + S + (E + F) ×
N). Therefore, in the device of the present invention, it can be seen that the overhead decreases as the number of executed instructions increases.

[0026]

As described above, since the device of the present invention emulates in parallel using a plurality of processors, the overhead of fetching and translating an instruction with respect to the execution time of the instruction is small, and the emulation speed is high. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a device of the present invention.

FIG. 2 is a schematic flowchart of an emulation operation of the device of the present invention.

FIG. 3 is a conceptual diagram of an assignment state when instructions are assigned in the order of processor numbers in the device of the present invention.

FIG. 4 is a diagram showing a procedure in which the device of the present invention obtains an instruction to be executed by itself.

FIG. 5 is a conceptual diagram of a synchronization control table of the device of the present invention.

FIG. 6 is a diagram showing an emulation procedure of the device of the present invention.

FIG. 7 is a flowchart showing a procedure of an “instruction execution start procedure” of the device of the present invention.

FIG. 8 is a flowchart showing a procedure of an “instruction execution completion procedure” of the device of the present invention.

FIG. 9 is a specific emulation sequence diagram of the device of the present invention.

FIG. 10 is a flowchart showing an emulation procedure of a conventional device.

FIG. 11 is a specific emulation sequence diagram of a conventional device.

[Explanation of symbols]

 0a, 1a, ..., (M-1) a Instruction acquisition means 0b, 1b, ..., (M-1) b Instruction translation means 0c, 1c, ..., (M-1) c Instruction execution means 10 Multiprocessor emulation means 101 Concurrent emulation means 102 Execution synchronization control means 102a Synchronization control table TI Machine language instruction sequence

Claims (3)

[Claims] 1. An operation of a computer to be emulated is simulated by fetching and translating instructions one by one from a machine language level instruction sequence executed by the computer to be emulated and sequentially executing them in the order in which they should be executed. In the emulation device, a plurality of processors each of which translates and executes an instruction, and one instruction from the instruction sequence, and each instruction of the instruction sequence,
Means for assigning each instruction to one of the plurality of processors so that the instruction is assigned to a processor different from the processor to which the instruction to be executed immediately before each instruction is assigned; An emulation apparatus comprising: means for operating in parallel; and means for controlling the execution timing of instructions in each of the plurality of processors so that the instruction sequence is executed in the order in which it should be executed. 2. An operation of a computer to be emulated is simulated by fetching and translating instructions one by one from a machine language level instruction sequence executed by the computer to be emulated and sequentially executing them in the order in which they should be executed. In the emulation device, one instruction from the instruction sequence
Each unit has a unit for fetching an instruction and a unit for translating and executing the instruction and for acquiring an instruction to be executed by itself. The unit for acquiring the instruction is the next execution order of the acquired instruction. A plurality of processors that are means for not acquiring instructions, a means for operating the plurality of processors in parallel, and an execution of instructions in each of the plurality of processors so that the instruction sequence is executed in the order in which the instructions should be executed. An emulation device comprising: means for controlling timing. 3. The means for controlling the execution timing of an instruction of each processor comprises means for detecting the completion of execution of an instruction in each processor, and the execution of the instruction by each processor is executed immediately before the instruction. 3. The emulation device according to claim 1, which is a means for controlling to be started after completion of execution of a power instruction.