JPH08213633A - Thin film transistor and its formation - Google Patents

Abstract

PURPOSE: To improve the crystallizability of source and drain regions turned into amorphous by a method wherein a trace catalyst material is added to an amorphous silicon film to accelerate the crystallization of the silicon film, the crystallizing temperature of the silicon film is reduced and the crystallizing time of the silicon film is shortened. CONSTITUTION: A crystalline silicon active layer on an insulating surface layer 101 is constituted of a lightly doped impurity region 106 between a channel formation region 104 and source and drain regions 105 and 108 and a lightly doped region 107 between the source and drain regions 105 and 108 and the region 104. A gate insulating film 102 and a gate electrode 103 are formed on the active layer. An interlayer insulator film 109 is provided in such a way as to cover the electrode 103. Electrodes 110 and 111, which are respectively provided on the regions 105 and 108, are respectively formed in contact holes formed in the interlayer insulator film 109. A catalyst element is mainly introduced into the regions 105 and 108 and the concentration of the element is set at 1×10<7> atom/cm<2> or higher. Thereby, a crystallization of the regions 105 and 108 is accelerated and the crystallizability of the source and drain regions turned into amorphous is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) used in a liquid crystal display device and the like and a method for manufacturing the same. Further, the present invention relates to a method for manufacturing a thin film transistor having a step of activating the source / drain regions by thermal annealing. The thin film transistor according to the present invention is formed on an insulating surface. In the present invention, on the insulating surface is
Not only on an insulating substrate such as glass, but also on an insulating coating provided on a semiconductor substrate such as single crystal silicon.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film semiconductor layer (also referred to as an active layer or an active region) provided on an insulating surface. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. The TFT is used for controlling pixels of a display device such as a liquid crystal having a matrix structure formed on an insulating substrate, a driving circuit of a matrix circuit, or an integrated circuit having a three-dimensional structure in which semiconductor integrated circuits are formed in multiple layers. Is used for. TFTs are distinguished according to the material and crystal state of the semiconductor used, such as amorphous silicon TFTs and crystalline silicon TFTs.

Generally, a semiconductor in an amorphous state has a small electric field mobility, and therefore, a TFT which is required to operate at high speed.
Not available for. Also, with amorphous silicon,
Since the P-type electric field mobility is extremely small, a P-channel type TFT (PMOS TFT) cannot be manufactured,
Therefore, N-channel TFT (NMOS TFT)
In combination with, complementary MOS circuit (CMOS circuit)
Cannot be formed.

On the other hand, crystalline semiconductors have a larger electric field mobility than amorphous semiconductors and can operate at high speed. Furthermore, crystalline silicon is not only the TFT of NMOS,
Since a PMOS TFT can also be manufactured, CMO
It is possible to make S circuits. For example, in an active matrix type liquid crystal display device, not only an active matrix circuit but also a peripheral circuit (driver or the like) for driving the active matrix circuit can be formed on the same substrate by a CMOS circuit of a crystalline TFT, which is a so-called monolithic structure. Obtainable.

Recently, for the purpose of reducing deterioration due to hot carriers, it is required to provide a low concentration impurity region adjacent to the source / drain regions and having a lower N-type or P-type impurity concentration than the source / drain regions. ing. To form the source / drain regions and the low-concentration impurity regions, an ion implantation method or an ion doping method is adopted. Usually, the silicon film is formed by accelerating the impurity ions imparting N-type or P-type conductivity. Have been injected into.

[0006]

However, since the impurity ions are accelerated and implanted into the silicon film, the ion bombardment at that time causes the silicon film to become amorphous. In such an amorphous state, the sheet resistance of the source / drain region becomes very large.

TFT whose semiconductor active layer is in an amorphous state
In the first place, since the field effect mobility is small,
Sheet resistance of drain region is 10kΩ / □ to 1MΩ / □
It can be put to practical use if it is of a degree. However, since the crystalline TFT has a high electric field effect mobility, sufficient characteristics as the crystalline TFT cannot be utilized unless the sheet resistance is 10 kΩ / □ or less. Therefore, it is necessary to enhance (activate) the crystallinity of the source / drain regions in the amorphous state. Further, in the activation process, many parts of the element of the TFT including the gate electrode are formed, and therefore it is required not to damage them.

A method by thermal annealing can be used for activation. The thermal annealing method has an advantage that there is little variation between batches. The temperature and time required for activation depend on the concentration of implanted impurities. Therefore, in the low-concentration impurity region, activation can be performed by thermal annealing at a relatively low temperature for a short time, whereas in order to activate a region having a high impurity concentration such as the source / drain region, high temperature is required. Long-term thermal annealing is required.

Usually, about 600 ° C. is required to activate the region into which the impurity having a concentration of 1 × 10 ²⁰ atoms / cm ³ or more (converted into a dose amount of 1 × 10 ¹⁴ atoms / cm ³ or more) is implanted. Long thermal anneal at temperatures of 1000 or 1000
Thermal annealing at a high temperature of ℃ or more for a short time is required. 1
If the thermal annealing method at 000 ° C. or higher is adopted, the usable substrate is limited to quartz, and the substrate cost becomes very high. On the other hand, in the thermal annealing method at a temperature of about 600 ° C., there is more room for selection of usable substrates, but it takes a long time, which leads to a decrease in productivity. Further, high temperature and long-time thermal annealing may have a great influence on the gate electrode, the substrate and the like. Therefore, thermal effects on other parts of the device (for example, shrinkage of the substrate, pattern shift due to deformation, etc.)
In order to minimize the temperature, activation by a lower temperature and shorter time thermal annealing is required.

An object of the present invention is to solve the above problems and to provide a crystalline thin film transistor having excellent characteristics. In addition, another object of the present invention is to eliminate the above-mentioned problems and to perform low-temperature thermal annealing for a short time,
It is an object of the present invention to provide a method for manufacturing a thin film transistor capable of activating a source / drain region.

[0011]

As a result of the research conducted by the present inventors, the addition of a trace amount of a catalyst material to a silicon film in a substantially amorphous state promotes crystallization, lowers the crystallization temperature, and shortens the crystallization time. It became clear that it can be shortened.

The present inventor has paid attention to the effect of this catalytic element and found that by utilizing it, the crystallinity of the amorphized source / drain regions can be improved. In the present invention, thermal annealing is performed after implanting the above-mentioned catalytic element into the source / drain regions by means such as an ion implantation method. Alternatively, by depositing a film of the catalytic element alone or a compound thereof on the source / drain regions and performing thermal annealing, the crystallinity can be improved while diffusing the catalytic element into the source / drain regions.

As a method of adding the catalytic element to the amorphous silicon film, specifically, there is a method of forming a film, particles, clusters or the like having the catalytic element substantially under or over the amorphous silicon film. Can be adopted. Alternatively, a method of introducing these catalytic elements into the amorphous silicon film by a method such as an ion implantation method can be adopted. As the catalyst element, nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), palladium (Pd), or a compound thereof is suitable.

After that, the amorphous silicon film can be crystallized by the action of the catalytic element by thermally annealing the amorphous silicon film at an appropriate temperature (typically a temperature of 580 ° C. or less). As a matter of course, there is a relationship that the higher the annealing temperature, the shorter the time required for crystallization. Further, the higher the concentration of the catalytic element such as nickel, iron, cobalt and platinum, the lower the temperature required for crystallization and the shorter the time required for crystallization. According to the research conducted by the present inventor, in order to promote crystallization of amorphous silicon, the concentration of at least one of the above catalytic elements needs to exceed 1 × 10 ¹⁷ atoms / cm ³ in the amorphous silicon film. Became clear. However, since all of the above catalyst elements are materials unfavorable to silicon, it is desirable that their concentration be as low as possible. In the study of the present inventors, it is desired that the total concentration of these catalyst materials does not exceed 10 ²⁰ atoms / cm ³ .

To manufacture a crystalline thin film transistor according to the present invention, the following steps may be provided. Forming a low concentration impurity region (to a crystalline silicon film having a catalyst element concentration of less than 1 × 10 ¹⁷ atoms / cm ³ ). Step of forming source / drain regions (by ion implantation or ion doping method). A step of forming a substance having a catalytic element on a region substantially the same as the source / drain regions. Step of activating the source / drain regions by thermal annealing (400 to 580 ° C.).

Alternatively, a step of forming a low-concentration impurity region (in the crystalline silicon film having a catalyst element concentration of less than 1 × 10 ¹⁷ atoms / cm ³ ). Step of forming source / drain regions (by ion implantation or ion doping method). A step of introducing a catalytic element into the substantially same region as the source / drain regions (by ion implantation or ion doping method). Step of activating the source / drain regions by thermal annealing (400 to 580 ° C.).

In these steps, the order of steps and can be exchanged. For example, the source / drain regions may be formed first, and then the low-concentration impurity regions may be formed, or the source / drain regions may be formed after first introducing the catalytic element. In the present invention, in the above process, the catalytic element or the substance having the catalytic element is intentionally introduced into a portion of the active layer other than the source / drain regions, for example, the channel forming region or the low concentration impurity region. It is characterized in that it is not formed or formed into a film.

The structure of the TFT obtained through the above steps is as shown in FIG. 1A shows an example of a coplanar type, and FIG. 1B shows an example of an inverted stagger type. FIG.
(A) will be described. A crystalline silicon active layer is provided on the insulating surface 101, and the silicon active layer includes a channel forming region 104, a source region 105, and a drain region 1.
08, low concentration impurity regions 106 and 107 between the source / drain regions 105 and 108 and the channel formation region 104
And is constituted by. A gate insulating film 102 and a gate electrode 103 are formed on the active layer. An interlayer insulator 109 is provided so as to cover the gate electrode 103.
Electrodes 110 and 111 of the source / drain regions 105 and 108 are formed in the contact holes of the interlayer insulator 109.

In the present invention, the catalytic element is mainly introduced into the source / drain regions 105 and 108 to improve the crystallinity of that portion. Source / drain region 10
The concentration of the catalytic element in 5, 108 is 1 × 10 ¹⁷ atoms /
It is characterized by exceeding cm ³ . Although a part of the catalytic element is thermally diffused into the low concentration impurity regions 106 and 107,
The concentration is sufficiently low, and in particular, the channel formation region 104
At the boundaries 112 and 113 with 1 × 10 ¹⁷ atoms / cm ³
It is characterized in that the concentration is less than. Naturally, the concentration of the catalytic element in the channel formation region 104 is less than 1 × 10 ¹⁷ atoms / cm ³ . Here, the concentration of the catalytic element in the source / drain regions 105 and 108 is a value when the silicon film is measured by secondary ion mass spectrometry (SIMS), and the catalytic element is distributed in the film thickness direction. Is its minimum value. The concentration of the catalytic element in the channel forming region 104 and the boundaries 112 and 113 is an average value in the thickness direction of the silicon film.

FIG. 1B will be described. Insulating surface 1
21, a gate electrode 122 and a gate insulating film 123 are provided on the gate electrode 122, and a crystalline silicon active layer is provided on the gate electrode 122. The silicon active layer includes a channel forming region 124, a source region 125, a drain region 128,
Then, the low-concentration impurity regions 126 and 12 between the source / drain regions 125 and 128 and the channel formation region 124.
7 are formed. And the source / drain region 1
Electrodes 129 and 130 are formed on 25 and 128. An interlayer insulator may be provided on the active layer.

Also in this case, the catalytic element is mainly the source /
It is introduced into the drain regions 125 and 128 to improve the crystallinity of that portion. Source / drain regions 125, 128
The concentration of the catalytic element in is over 1 × 10 ¹⁷ atoms / cm ³ . Although a part of the catalyst element is also thermally diffused into the low concentration impurity regions 126 and 127, the concentration thereof is sufficiently low, and in particular, the boundary 131 with the channel forming region,
132 is characterized by a concentration of less than 1 × 10 ¹⁷ atoms / cm ³ .

[0022]

In the present invention, the catalytic element mainly introduced into the source / drain regions by the above steps diffuses into the regions and promotes crystallization remarkably. for that reason,
Upon activation, 400-580 ° C, typically 450
A sufficient effect can be obtained by heating at a temperature of up to 550 ° C. Further, it is sufficient that the annealing time is within 8 hours, typically within 4 hours. In particular, when the catalytic element is introduced by the ion implantation method or the ion doping method as in the subsequent step, the catalytic element is evenly distributed from the beginning, so that the crystallization proceeds extremely easily.

Further, the concentration of the catalytic element is extremely low in the low-concentration impurity region, and the crystallinity improvement due to the catalytic element for that purpose, except for the portion adjacent to the source / drain regions
Although hardly expected, the concentration of the introduced impurities is sufficiently low that the impurities are activated even at the above low temperature. The advantage of the present invention is that although a catalytic element harmful to silicon is added to the TFT, the concentration thereof is remarkably low (1 × 10 6) in the channel forming region or in the boundary between the channel forming region and the low concentration impurity region as described above. ¹⁷ atoms / c
m ³ )). Particularly, it is preferable for the TFT characteristics that the concentration of the catalyst element at the boundary between the channel forming region and the low concentration impurity region is sufficiently low.

At the boundary, in the case of the N channel type, N ⁻
In the case of the I-junction or P-channel type, a P ⁻ I junction is formed, and the current originally flows only in the direction from N ⁻ to I or from I to P ⁻ , and the current flowing in the opposite direction is sufficiently small. However, when many catalytic elements and the like are present in the vicinity of such a junction, a leak current in the opposite direction is generated due to the energy level generated by the element. This means that TFT
Is in a non-selected state (that is, a negative voltage is applied to the gate electrode in the case of the N-channel type, and vice versa in the case of the P-channel type), the leak current (off current) is large. means.

As in the present invention, an N ^-- I junction, or
When the concentration of the catalytic element in the vicinity of the P ^- I junction is sufficiently low, the reverse leak current (that is, off current) can be sufficiently reduced. This is extremely effective when the TFT of the present invention is used as a switching transistor or the like of an active matrix circuit.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in FIGS. [Embodiment 1] This embodiment relates to fabrication of a coplanar N-channel TFT used as a switching transistor of an active matrix circuit of a liquid crystal display device. In the switching transistor of the active matrix circuit, the source / drain regions are inverted at any time depending on the use environment, but for convenience, in the following description, the source / drain regions are connected to the data lines of the matrix. One is called a source, and one connected to a pixel electrode is called a drain.

FIG. 2 shows a cross-sectional view of the manufacturing process of this embodiment. An intrinsic (I-type) amorphous silicon film having a thickness of 300 to 2000 Å, for example, 1000 Å is deposited on the substrate (quartz) 201 by the plasma CVD method. The concentration of nickel, platinum, cobalt, iron, and palladium in this amorphous silicon film is set to 1 × 10 ¹⁷ atoms / cm ³ . Next, the amorphous silicon film was crystallized by thermal annealing at 600 ° C. for 48 hours in a nitrogen atmosphere. After thermal annealing, the crystallized silicon film is etched to form island-shaped silicon regions.

Then, a thickness of 1 is obtained by the sputtering method.
A 000Å silicon oxide film 205 is deposited as a gate insulating film. For sputtering, silicon oxide was used as a target, and the substrate temperature during sputtering was 200 to 400.
C., for example 350.degree. C., the sputtering atmosphere is a mixed atmosphere of oxygen and argon, and the argon / oxygen ratio is 0 to 0.
5, for example, 0.1 or less. Subsequently, low pressure CVD
Depending on the method, the thickness is 3000-8000Å, for example 600
A 0Å silicon film (containing 0.1 to 2% phosphorus) was deposited. Then, the silicon film is etched to form the gate electrode 206. Note that it is desirable that the steps of forming the silicon oxide film 205 and the silicon film be performed continuously.

Then, a low concentration N-type impurity (phosphorus) is implanted into the island-shaped silicon region by ion doping using the gate electrode 206 as a mask. The ion doping method is a doping method of impurities in which plasma is generated in a reduced-pressure atmosphere containing an impurity element to generate ions, which are accelerated with a high voltage to irradiate an object to be irradiated.

In this embodiment, phosphine (PH ₃ ) diluted with hydrogen (for example, 1% PH ₃ -99% H ₂ ) is used as the doping gas. Accelerating voltage 6
0 to 90 kV, for example, 80 kV, and the dose amount is 1 × 1
It is set to 0 ¹² to 8 × 10 ¹³ atoms / cm ² , for example, 5 × 10 ¹² atoms / cm ² . As a result, N-type low-concentration impurity regions 203 and 204 were formed. Also, the gate electrode 206
Impurities were not introduced into the portion immediately below the channel formation region 202, and the channel formation region 202 remained. After that, thickness 4000-12000
A silicon oxide film 207 of Å is formed by a plasma CVD method.
In this embodiment, the thickness of the silicon oxide film 207 is 6000 Å, which is the same as that of the gate electrode. (Fig. 2 (A))

Next, the silicon oxide films 207 and 205 are etched by an anisotropic dry etching method,
Side wall 20 on the side surface of the gate electrode 206
8 is formed. The width of the side wall 208 is determined by the height of the gate electrode 206 and the thickness of the silicon oxide film 207. In this example, it was approximately 6000Å. Then, nickel ions of 1 × 10 ¹² to 1 × 10 ^{14 are} added by an ion implantation method.
It was introduced at a dose amount of atoms / cm ² . Accelerating voltage is 10
20 kV was suitable. At this time, even in the same low concentration impurity regions 203 and 204, the region 21 below the side wall 208 is formed.
Nickel is not implanted in 1, 212, but is mainly implanted in the exposed portions 209, 210 (these are the portions where the source / drain regions will be formed later). (FIG. 2 (B))

After that, a high concentration N-type impurity (phosphorus) is implanted by ion doping using the gate electrode 206 and the sidewall 208 as a mask. In this embodiment, the doping gas is hydrogen diluted phosphine (for example, 5% PH ₃ -9).
5% H ₂ ) is used, the acceleration voltage is set to 10 to 30 kV, for example, 20 kV, and the dose amount is set to 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , for example, 2 × 10 ¹⁴ atoms / cm ² .
As a result, N-type impurities are implanted at a high concentration in regions not covered by the gate electrode 206 and the sidewalls 208, so that the source region 213 and the drain region 214 are formed. Further, since the impurity ions are not implanted into the region immediately below the gate electrode 206 and the side wall 208, they remain as the channel formation region 202 and the low concentration impurity regions 215 and 216. The regions where the source / drain regions 213 and 214 were formed were almost the same as the regions 209 and 210 into which nickel was implanted in the previous step. The regions where the low-concentration impurity regions 215 and 216 are formed are the regions 211 and 21 where nickel was not implanted in the previous step.
It is almost the same as 2. Then, by performing thermal annealing at 400 to 580 ° C., the source / drain regions 213,
214, the impurities in the low concentration impurity regions 215 and 216 are activated. In this embodiment, the thermal annealing condition is 550.
C. and 2 hours. (Fig. 2 (C))

Then, a silicon nitride film 217 having a thickness of 4000 to 8000 Å is deposited by the plasma CVD method. A contact hole with the source region 213 is formed in the silicon nitride film 217. Then, an aluminum film having a thickness of 6000Å is deposited on the contact hole by a sputtering method,
This is etched to form the source electrode 218.
(Fig. 2 (D))

Further, a silicon oxide film 219 having a thickness of 2000 to 4000 Å is deposited by the plasma CVD method.
The silicon oxide film 219 and the silicon nitride film 217 are each etched to form a contact hole with the drain region 214. Then, a thickness of 5 is obtained by the sputtering method.
A transparent conductive film (for example, indium tin oxide film) having a thickness of 00 to 1000 Å is deposited in the contact hole and etched to form the pixel electrode 220. Through the above steps, a thin film transistor of an active matrix circuit is manufactured. (Fig. 2 (E))

The source / drain regions 213 and 214 and the channel forming region 202 of the obtained thin film transistor.
The nickel concentration of was measured by the secondary ion mass spectrometry (SIMS) method. Source / drain regions 213, 21
4 is about 1 × 10 ^{18 to} 5 × 10 ¹⁸ atoms / cm ³ , and the channel formation region 202 has a measurement limit (1 × 10 ¹⁶ atoms / c 3).
m ³ ) or less. In particular, the source / drain region 21
In Nos. 3 and 214, a low nickel concentration was observed at the center of the film, and the minimum value was 1 × 10 ¹⁸ atoms /
It was cm ³ .

[Embodiment 2] This embodiment also relates to the manufacture of a coplanar type N-channel TFT used as a switching transistor of an active matrix circuit of a liquid crystal display device, and the source / drain regions are also called in the embodiment. Same as 1. FIG. 3 shows a cross-sectional view of the manufacturing process of this embodiment.

First, the substrate (Corning 7059) 301
An underlying film 302 of silicon oxide having a thickness of 2000 Å is formed thereon by a sputtering method. Furthermore, plasma CVD
Depending on the method, the thickness is 300-1000Å, for example 500Å
Intrinsic (I-type) amorphous silicon film is deposited.
Then, in a nitrogen atmosphere, this amorphous silicon film is
Thermal annealing is performed at 400 ° C. for 1 hour to remove hydrogen contained in the film.

Then, laser light was irradiated to crystallize. As a laser, a KrF excimer laser (wavelength 248 nm), an ArF excimer laser (wavelength 193n) is used.
m), XeCl excimer laser (wavelength 308 nm),
Excimer laser such as XeF excimer laser (wavelength 353 nm), or Nd: YAG laser (wavelength 1064 nm) or its second harmonic (wavelength 532 nm)
Alternatively, a pulsed laser such as a third harmonic (wavelength of 355 nm) or a continuous wave laser such as an Ar ion laser is preferable. In this embodiment, a KrF excimer laser is used. Energy density is 320-450mJ
/ Cm ² is suitable, but since the optimum energy density changes depending on the formed silicon film, the optimum energy density is determined by setting conditions in advance.

After that, the crystallized silicon film is etched to form island-shaped silicon regions 303. In addition, monosilane (SiH ₄ ) and dinitrogen monoxide (N ₂ O)
By using rf plasma CVD method as a raw material
A silicon oxide film 304 of 00Å is deposited as a gate insulating film. In this example, monosilane was introduced into the reaction chamber at 10 SCCM and dinitrogen monoxide at 100 SCCM, the substrate temperature was 430 ° C., the reaction pressure was 0.3 Torr, and the input power (13.
56 MHz) 250 W. These conditions will vary depending on the reactor used. The deposition rate of the silicon oxide film 304 produced under the above conditions is about 1000 Å / min, and the etching rate in a mixed solution of hydrofluoric acid 1, 50 acetic acid and 50 ammonium fluoride (20 ° C.) is about 1000 Å / min. It was

Subsequently, by the sputtering method,
An aluminum film having a thickness of 2000 to 8000Å, for example 4000Å, is deposited. Then, a photoresist is applied and a photoresist mask 306 is formed by a known photolithography method. In order to improve the adhesion of the photoresist, an extremely thin (50 to 200Å) anodic oxide film (not shown) is previously formed on the surface of the aluminum film. Using the photoresist mask 306, the aluminum film is etched to form the gate electrode 305. In order to suppress the occurrence of abnormal crystal growth (hillock) in the heating or the subsequent anodic oxidation process, 0.1 to 0.5% by weight of scandium (Sc) or yttrium (Y) is mixed in aluminum. ing. (Fig. 3 (A))

Next, while leaving the photoresist mask 306 used as an etching mask on the gate electrode 305, an electric current is applied to the gate electrode 305 in an electrolytic solution to perform anodic oxidation to obtain a thickness of 1
˜5 μm, for example 2 μm thick anodic oxide 307 is formed. A constant current of 10 to 30 V is applied to the electrolytic solution using an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like. In this embodiment, p
10 in an oxalic acid solution (30 ° C.) with H = 0.9 to 1.0
A current of V was applied to the gate electrode 305 for anodization. The thickness of the anodic oxide 307 is controlled by the anodic oxidation time. The anodic oxide 307 thus obtained was porous. In this anodic oxidation process, the thin anodic oxide film existing between the gate electrode 305 and the photoresist mask 306 can prevent the current from leaking from the photoresist mask 306, and the side surface of the gate electrode 307 can be suppressed. Only the anodic oxide 307 can be formed. (FIG. 3 (B))

Next, the photoresist mask 306 is peeled off, and a current is applied to the gate electrode 305 again in the electrolytic solution. As a result, the anodic oxide 308 is formed on the upper surface and the side surface of the gate electrode 305. The anodic oxide 308 is dense and hard, and is effective in protecting the gate electrode 305 in the subsequent heating process. As the electrolytic solution, an ethylene glycol ammonia solution having a pH of 6.9 to 7.1 and containing at least one of 3 to 10% tartar solution, boric acid and nitric acid is used. When the temperature of the solution is lower than room temperature around 10 ° C, a good oxide film can be obtained. Anodic oxide 3
The thickness of 08 is almost proportional to the applied voltage, and the applied voltage is 150
2000 V of anodic oxide 308 is formed.

After that, the silicon oxide film 304 is etched by the dry etching method. Porous anodic oxide 3
Since 07 is not etched, the silicon oxide film 3 below it is not etched.
04 is not etched and remains as a gate insulating film 309. (Fig. 3 (C))

After that, the anodic oxide 307 is etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 307 was etched, and the etching rate was about 600Å / min. The silicon oxide gate insulating film 309 remains as it is.

Next, an impurity (phosphorus) is implanted into the island-shaped silicon region 303 by plasma doping using the gate electrode 305 and the gate insulating film 309 as a mask. Using phosphine (PH ₃ ) as a doping gas, two-step doping is performed. The first doping is
The acceleration voltage is 80 kV and the dose is 5 × 10 ¹² atoms /
cm ² Since the acceleration is large in this doping, phosphorus ions pass through the gate insulating film 309 and are also implanted into the island-shaped silicon region 303 thereunder. However, since the dose amount at this time is small, the low-concentration impurity region 311, 31
2 is formed.

In the second doping, the acceleration voltage is made smaller and the dose amount is made larger than that in the first doping. Here, the acceleration voltage is 30 kV and the dose amount is 5 × 10 ^14.
Atom / cm ² . In this doping, since the acceleration is small, phosphorus ions cannot pass through the gate insulating film 309, and are mainly injected into the exposed portion of the island-shaped silicon region 303 to form the source region 310 and the drain region 313. Impurities are injected into the source / drain regions 310 and 313 both in the second doping and the dose amount in the second doping is larger than that in the first doping, so that the regions become high-concentration impurity regions. On the other hand, immediately below the gate insulating film 309, impurities are not injected by the second doping, so that they remain as low-concentration impurity regions 311 and 312. In particular, immediately below the gate electrode 305, no impurity is injected by the second doping. , The channel formation region.

Then, by the spin coating method,
Form a very thin coating 314 of nickel acetate. Here, a 10 ppm aqueous solution of nickel acetate is used, and this is spin-coated and spin-dried to form an extremely thin nickel acetate film 314 on the entire surface of the substrate. Prior to spin coating, a thin silicon oxide film is formed on the surfaces of the source / drain regions 310 and 313 by treatment with hydrogen peroxide solution (or a mixed solution of ammonia and ammonia) or the like. Prevent it from being flipped. (Fig. 3 (D))

After that, thermal annealing is performed at 450 ° C. for 4 hours in a nitrogen atmosphere to form the source / drain regions 310 and 31.
3 and the impurities in the low concentration impurity regions 311 and 312 are activated. At this time, the source / drain regions 31
0 and 313 have a nickel acetate coating 314 substantially adhered thereto (strictly, a thin silicon oxide film exists between them, but this does not hinder nickel diffusion during thermal annealing). However, nickel acetate easily decomposes at a temperature of 400 ° C. or higher to form metallic nickel, and the source region 3
10 and diffuse into the drain region 313. Due to this nickel catalysis, the source / drain regions 310, 313
Recrystallizes easily. Further, the low-concentration impurity regions 311 and 312 are simultaneously activated by this thermal annealing.

Subsequently, as an interlayer insulator, a thickness of 4000Å
Of the silicon oxide film 315 of the plasma C using TEOS as a raw material.
It is deposited by the VD method. Source / on the silicon oxide film 315
Contact holes with the drain regions 310 and 313 are formed respectively, and a source electrode / wiring 316 is formed with a multilayer film of titanium and aluminum. Drain region 3
No electrode is formed in the contact hole 13 at this stage. Then, a thickness of 2 is obtained by the plasma CVD method.
A 000Å silicon nitride film 315 is deposited, and again inside the contact hole with the drain region 313 formed earlier,
A contact hole is formed and a pixel electrode 31 of a transparent conductive film is formed.
8 is formed and connected to the drain region 313. Through the above steps, a thin film transistor of an active matrix circuit is manufactured. (Fig. 3 (E))

[Embodiment 3] FIG. 4 shows a manufacturing process of the N-channel TFT shown in this embodiment. First, a base film 402 of silicon oxide having a thickness of 2000 Å is formed on a substrate (Corning 7059) 401 by a sputtering method. Next, by plasma CVD method, 500 Å thick intrinsic (I type)
Deposit an amorphous silicon film. This amorphous silicon film is thermally annealed at 400 ° C. for 1 hour in a nitrogen atmosphere to remove hydrogen contained in the film. Next, the amorphous silicon film was irradiated with laser light to be crystallized. A KrF excimer laser (wavelength 248 nm) is used as the laser. The irradiation energy density is 350 mJ / cm ² . Then, the crystallized silicon film is etched to form island-shaped silicon regions 403.
To form.

Further, a silicon oxide film 404 having a thickness of 1000 Å to be a gate insulating film is deposited by the plasma CVD method. Subsequently, by the sputtering method, 400
Deposit a 0Å thick aluminum film. On the surface of the aluminum film, in order to improve the adhesion of the photoresist, an anodic oxide film (not shown) is formed to an extremely thin thickness of 50 to 200Å. Then, the photoresist mask 406
Then, the aluminum film is etched to form a gate electrode 405. In order to suppress the occurrence of abnormal crystal growth (hillock) in the heating or the subsequent anodic oxidation step, aluminum is added. 1 to 0.5 wt% of scandium (Sc) or yttrium (Y) is mixed. (Fig. 4 (A))

With the photoresist mask 406 used as the etching mask left on the gate electrode 405, an electric current is applied to the gate electrode 405 in an electrolytic solution and anodization is performed to obtain a thickness of 1 to 5 μm, for example. A anodic oxide 407 having a thickness of 2 μm is formed. A constant current of 10 to 30 V is applied to the electrolytic solution using an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like. In this example, an oxalic acid solution (30
The temperature is set to 10 V in (° C.). Also, anodic oxide 407
Is controlled by the anodic oxidation time. The anodic oxide 407 thus obtained was porous.
In this anodic oxidation process, the thin anodic oxide film existing between the gate electrode 405 and the photoresist mask 406 can suppress the leakage of current from the photoresist mask 406, and the side surface of the gate electrode 405 can be suppressed. Anodization can be selectively advanced. (Fig. 4 (B))

Next, the photoresist mask 406 was peeled off, and a current was applied to the gate electrode 405 again in the electrolytic solution. Therefore, the anodic oxide 408 was formed on the upper surface and the side surface of the gate electrode. 3 to the electrolyte
An ethylene glycol ammonia solution having a pH of 6.9 to 7.1 and containing at least one of 10% tartar solution, boric acid and nitric acid is used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. The thickness of the anodic oxide 408 is almost proportional to the applied voltage, and when the applied voltage is 150 V, the thickness is 20
A 00Å anodic oxide 408 is formed. This anodic oxide 408 is dense and hard, and is effective in protecting the gate electrode 405 in the subsequent heating process.

Then, the silicon oxide film 404 is etched by the dry etching method. As a result, part of the island-shaped silicon region 403 was exposed. Further, since the porous anodic oxide 407 is not etched in this etching, the silicon oxide film 409 below is not etched,
It remains as the gate insulating film 409. After that, after forming an extremely thin oxide film (not shown), by spin coating,
Form a very thin coating 410 of nickel acetate. At this time, nickel comes into contact with the exposed surface of the island-shaped silicon region 403, and the island-shaped silicon region 403 below the gate insulating film 409 does not come into contact with nickel.
(Fig. 4 (C))

In this state, heat treatment at 350 ° C. is applied,
A nickel silicide layer is formed on the surface of the exposed island-shaped silicon region 403. Next, the porous anodic oxide 407 is removed by etching. Thus, the state shown in FIG. 4D is obtained.

Next, an impurity (phosphorus) is implanted into the island-shaped silicon region 403 by plasma doping using the gate electrode 405 and the gate insulating film 409 as masks. Phosphine (PH ₃ ) is used as a doping gas to perform two-step doping. The first doping was performed at an acceleration voltage of 80 kV and a dose of 5 × 10 ¹² atoms / cm 3.
^{Assume 2} . Since the acceleration is large in this doping, phosphorus ions pass through the gate insulating film 409 and are also implanted into the island-shaped silicon region 403 thereunder, but since the dose amount at this time is small, the low-concentration impurity region 412, 413 is formed respectively.

Subsequently, the second doping is performed. In the second doping, the acceleration voltage is made smaller and the dose amount is made larger than in the first doping. here,
The acceleration voltage is 30 kV and the dose is 5 × 10 ¹⁴ atoms /
cm ² In this doping, since the acceleration is small, phosphorus ions cannot pass through the gate insulating film 409 and are mainly injected into the exposed portion of the island-shaped silicon region 403 to form the source region 411 and the drain region 414. Impurities are implanted into the source / drain regions 411 and 414 in both dopings, and the dose amount in the second doping is larger than that in the first doping, so that the regions become high-concentration impurity regions. On the other hand, immediately below the gate insulating film 409, 2
Since impurities are not implanted in the second doping, they remain as the low-concentration impurity regions 412 and 413. Particularly, immediately below the gate electrode 405, no impurities are implanted in the second doping, so that they become channel formation regions.

Then, the source / drain regions 4 are formed by thermal annealing at 450 ° C. for 4 hours in a nitrogen atmosphere.
The impurities in the low concentration impurity regions 412 and 413 are activated. Source / drain regions 411, 4
A coating film 415 of a nickel acetate film is substantially adhered to 14 (strictly speaking, although a thin silicon oxide film exists between them,
(This does not hinder the diffusion of nickel during thermal annealing.) However, nickel acetate is easily decomposed at a temperature of 400 ° C. or higher to metallic nickel, and the source region 411,
Diffuse into the drain region 414. Due to the catalytic action of nickel, the source / drain regions 411 and 414 are easily recrystallized. Moreover, the low-concentration impurity regions 412 and 413 are simultaneously activated by the thermal annealing.

Then, as an interlayer insulator, a thickness of 4000Å
Of the silicon oxide film 416 of the plasma C using TEOS as a raw material
The source / drain regions 4 are deposited on this by the VD method.
Contact holes 11 and 414 are formed respectively. Then, the source electrode / wiring 417 is formed by a multilayer film of titanium and aluminum. At this stage, no electrode is formed in the contact hole of the drain region 414.

Subsequently, a thickness of 2 is obtained by the plasma CVD method.
A 000Å silicon nitride film 418 is deposited, a contact hole is further formed inside the contact hole of the drain region 414 previously formed, and the pixel electrode 419 of the transparent conductive film is formed.
And is connected to the drain region 414. A thin film transistor is manufactured through the above steps. (Fig. 4
(E))

[0061]

[Effects] According to the present invention, the source / drain regions can be favorably activated by the catalytic element, so that a crystalline thin film transistor having excellent characteristics can be obtained.

Further, according to the present invention, since the catalyst element is added to the source / drain regions at a predetermined concentration, the source / drain regions are doped at a low temperature such as 450 ° C. for 4 hours and in a short time. It becomes possible to activate the impurities that impart the conductivity type. Therefore, the throughput can be improved. In addition, the conventional 6
When a process at a temperature of 00 ° C. or higher is adopted, shrinkage of the glass substrate has been a problem as a cause of reduction in yield, but by using the present invention, such a problem can be solved at once. When applied to a manufacturing process of a thin film transistor of a liquid crystal display device, mass productivity and characteristics can be improved.

Further, the fact that processing can be carried out at low temperature in a short time is
This means that a large area substrate can be processed at one time. Therefore, by forming a large number of thin film transistors over a large-sized substrate, a large number of semiconductor circuits (matrix circuits or the like) can be cut out from one substrate, so that the unit cost of a circuit or a device is significantly reduced. You can As described above, the present invention is an industrially useful invention.

[Brief description of drawings]

FIG. 1 shows a conceptual diagram of a TFT of the present invention.

2A to 2C are cross-sectional views of a manufacturing process of Example 1.

3A to 3C are cross-sectional views illustrating a manufacturing process of Example 2.

4A to 4C are cross-sectional views illustrating a manufacturing process of Example 3.

[Explanation of symbols]

101 ... Substrate 102 ... Gate insulating film 103 ... Gate electrode 104 ... Channel formation region 105 ... Source 106, 107 ... Low concentration impurity region 108 ... Drain 109 ... Interlayer Insulator 110 ... Source electrode 111 ... Drain electrode 112, 113 ... Boundary between low-concentration impurity region and channel forming region 121 ... Substrate 122 ... Gate electrode 123 ... Gate insulating film 124. .. Channel forming region 125 ... Source 126, 127 ... Low concentration impurity region 128 ... Drain 129 ... Source electrode 130 ... Drain electrode 131, 132 ... Low concentration impurity region and channel formation Area boundaries

Claims (6)

[Claims] 1. A crystalline silicon film formed on an insulating surface, a channel forming region, a source / drain region provided outside the channel forming region, the channel forming region and the source / drain region. In a thin film transistor having at least two low-concentration impurity regions sandwiched between, the concentration of impurities imparting N-type or P-type conductivity to the low-concentration impurity regions is higher than that of the source / drain regions. And a source / drain region has a catalytic element that promotes crystallization of the amorphous silicon film at a concentration exceeding 1 × 10 ¹⁷ atoms / cm ³ , The thin film transistor, wherein the concentration of the catalytic element at the boundary is less than 1 × 10 ¹⁷ atoms / cm ³ . 2. A crystalline silicon film formed on an insulating surface, a channel forming region, a source / drain region provided outside the channel forming region, the channel forming region and the source / drain region. In a thin film transistor having at least two low-concentration impurity regions sandwiched between, the concentration of impurities imparting N-type or P-type conductivity to the low-concentration impurity regions is higher than that of the source / drain regions. A thin film transistor in which a catalytic element for promoting crystallization of an amorphous silicon film is added to a region substantially lower than the source / drain regions. 3. The thin film transistor according to claim 1, wherein the catalytic element is at least one of nickel, iron, cobalt, palladium, and platinum. 4. The method according to claim 1, wherein the N-type or P-type impurity in the source / drain region and the low-concentration impurity region is introduced by irradiating accelerated ions. Thin film transistor. 5. The thin film transistor according to claim 1, wherein the concentration of the catalytic element in the source / drain region is the minimum value in the silicon film measured by secondary ion mass spectrometry. 6. The concentration of the catalytic element for promoting crystallization of amorphous silicon on the insulating surface is 1 × 10 ¹⁷ atoms / cm 3.
A step of introducing into the crystalline silicon film of less than ³ a low-concentration impurity imparting an N-type or P-type conductivity type by using accelerated ions; and a higher concentration in the crystalline silicon film than the above step. Forming a source / drain region by introducing an impurity imparting the N-type or P-type conductivity type by using accelerated ions, and forming the source / drain region in substantially the same region as the catalyst. The step of introducing an element or forming a coating film containing the catalytic element by substantially adhering to the source / drain regions, and thermally annealing the silicon film at a temperature of 400 to 580 ° C. And a step of activating the impurities introduced into the drain region.