JPH08213595A - Semiconder device - Google Patents

Abstract

PURPOSE: To have a specific thickness of a gate insulating film besides having a specific gate length to improve reliability under hot carrier stress together with reducing a tunnel current from source/drain electrodes to a gate electrode. CONSTITUTION: A gate electrode 2 is formed on a p-type semiconductor substrate 1 through an insulating film 3. On each side of a channel forming region 4 directly under this gate electrode 2, n<+> heavily doped diffusion layers to become a source region 5 and a drain region 6 are formed. Thereby, a thickness of the insulating film 3 is made not to exceed 2.0nm and a gate length of the gate electrode 2 is made not to exceed 0.3μm. By making the insulating film 3 not to exceed 2.0nm, reliability under hot carrier stress is sharply improved. Further, by making the gate length not to exceed 0.3μm, a gate current is sharply decreased to obtain a good transistor characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a fine and high performance MOS type transistor suitable for use under a low power supply voltage.

[0002]

2. Description of the Related Art MOS transistors are especially
With the improvement of FET integration technology, gate length 0.5 μm
The following areas are being examined in various places. MOSFETs by RL Dennard and others in 1974
A so-called scaling law has been proposed for the miniaturization of. This is a rule that when the size of a certain constituent element (for example, channel length) of an element is reduced, the other constituent elements are also reduced at the same ratio to ensure the operating characteristics as a transistor. Basically 1970
MOSLSI that continued from the 1980s to the early 90s
High integration has been realized based on this law.

However, with further miniaturization, a limit value called "physical limit value" approaches in various components, and it is becoming difficult to reduce the limit value beyond the limit value. For example, it is generally said that the thickness of the gate insulating film is about 3 to 4 nm, and below this thickness, the tunneling current between the gate electrode and the source / drain electrodes increases, and the transistor normally operates. Is known to be unrealizable.

Therefore, a method of fixing the gate insulating film to about 3 nm and considering reduction of other constituent elements has been proposed.
Proposed by Fiena et al. In 1993 (author
C.Fiegna, H.Iwai, T.Wada, T.Saito, E.Sangiorgio, and
B.Ricco ； Paper name A new scaling methodology for the
0.1-0.025 um MOSFET, 'Dig. Of Tech. Papers, VLSISym
p .; Source Technol., Kyoto, pp.33-34, 1993.). With that method, Ono et al. Realized a transistor with a gate length of 0.04 μm in the same year (author M.Ono, M.Sa.
ito, T.Yoshitomi, C.Fiegna, T.Ohguro, and H.Iwai; Paper name Sub-50 nm gate length n-MOSFETs with 10 nm phosp
horus source and drain junction ； Source IEDMTech.Di
g., pp. 119-122, 1993).

Gate insulating film thickness 3 nm and gate length 0.0
The 4 μm transistor is manufactured as follows. First,
After forming an element region and an element isolation region on a p-type silicon substrate by the LOCOS method, a p-type impurity (for example, B) is formed in a channel formation region so that a desired threshold voltage can be obtained.
(Boron)) is introduced.

After that, a 3 nm oxide film as a gate oxide film is formed on the surface of the silicon substrate in a DryO ₂ atmosphere, for example.
It is formed by oxidation at 00 ° C. for 10 minutes. After that, for example, polysilicon is deposited to a thickness of 100 nm under P (phosphorus) -containing conditions, a resist is applied, and the gate electrode is processed into a desired length by patterning. The n-type impurity is introduced into the source / drain formation region by removing the PSG left on the side wall of the gate electrode.
It is formed by solid phase diffusion of P from a film (P (phosphorus) -containing silicon oxide film). For the purpose of making a good connection with the metal wiring portion and reducing the resistance of the diffusion layer in the portion that does not affect the short channel effect of the transistor, an n-type impurity is then ion-implanted to, for example, 5 × 10 ¹⁵ cm 2. ^{-2 to} introduce. Annealing for impurity diffusion and activation at this time is performed at 1000 ° C. for 10 seconds, for example. After that, the contact portion is opened and metal wiring is provided.

The transistor thus manufactured has a sheet resistance (ρ of the source / drain diffusion layer below the gate sidewall portion).
s) was 6.2 kΩ / □, and the diffusion length (that is, the depth of the source / drain region) was 10 nm as a result of SIMS analysis.

[0008]

However, the above-mentioned conventional transistor has a relatively large parasitic resistance due to the shallow source / drain regions. for that reason,
The driving force could not be improved corresponding to the gate length reduction.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a MOS semiconductor device having an improved driving force.

[0010]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via an insulating film, and a second conductivity type formed on both sides of a channel formation region located directly below the gate electrode of the semiconductor substrate. A source / drain region is provided, the thickness of the insulating film is less than 2.5 μm, preferably 2.0 nm or less, and the gate length of the gate electrode is 0.3 μm or less.

Further, this semiconductor device has a power supply voltage of 1.
More desirable characteristics are obtained when used in a circuit of 5 V or less.

[0012]

According to the present invention, the gate insulating film has a thickness of 2.5 nm.
When it is less than the range, the reliability under hot carrier stress is significantly improved as shown in FIG. 2 nm
It will be further improved by the following.

Further, as shown in FIG. 4, by setting the channel length to 0.3 μm or less, the gate current is greatly reduced, and good transistor characteristics are obtained.

Therefore, the gate length of the present invention is 0.3 μm.
When the gate insulating film thickness is less than 2.5 nm below, a transistor having good transistor operation and high hot carrier reliability can be realized.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows an M according to an embodiment of the present invention.
1 shows a structure of an OS type transistor. In this figure, 1 is a semiconductor substrate of the first conductivity type (for example, p type), and a gate electrode 2 is formed on the substrate 1 with an oxide film 3 interposed. On each side of the channel formation region 4 immediately below the gate electrode 2 in the substrate 1, a conductivity type opposite to the first conductivity type (for example, n +
(Type) high-concentration diffusion layer is formed. A power source 7 is connected to the gate electrode 2 and a power source 8 is connected to the drain region 6 for use. The gate length Lg, which is the dimension in the lengthwise direction of the channel formation region 4 of the gate electrode 2, is 0.3 μm.
and the thickness Tox of the gate insulating film 3 is 2.5 nm.
Less than The transistor having the gate length Lg of the present invention is intended to improve the conductance gm and at the same time reduce the tunnel current Id2 flowing into the gate among the currents Id1 and Id2 to flow into the drain region 6.

FIG. 1 (b) shows a typical structure of the embodiment of the present invention and the dimensions of each part. Gate length of gate electrode (L
g) is 0.09 μm, and gate insulating film thickness (Tox) is 1.5
nm, effective channel length between source / drain (Leff)
Is 0.05 μm, and the diffusion depth (Xj) near the channel is 30 nm, which is shallower than the other regions of the source and drain. In this embodiment, the diffusion layer in the vicinity of the channel is formed by solid phase diffusion from the PSG film formed on the gate side wall, so-called SPDD (Solid Phase Diffused D).
It is a MOS transistor with a rain structure.

Here, a method of manufacturing a main part of the transistor of the present invention will be described first. The gate oxide film is formed by forming a device region and a device isolation region on the semiconductor substrate 1 by a conventional method, and then performing oxidation by a rapid lamp heating method at 800 ° C. for 10 seconds. As a result, it was possible to form the gate insulating film 3 having a film thickness of 1.5 nm that was suitable for the above conditions. Further, the gate insulating film 1.8 was formed under the condition of 850 ° C. for 10 seconds.
nm could be formed. A gate insulating film having a thickness of 2.0 nm could be formed under the conditions of 900 ° C. for 5 seconds. By selecting the temperature and time, it was possible to form a gate insulating film having a desired film thickness of less than 2.5 nm. After that, a phosphorus-containing polysilicon film is deposited to a thickness of about 100 nm and patterned by anisotropic etching to form a gate electrode having a desired gate length Lg.

After the HF treatment, source / drain regions 5 and 6 having a diffusion length of 30 nm could be formed by solid phase diffusion from the PSG film (phosphorus-containing silicon oxide film). FIG. 2 shows the impurity concentration profile at that time. The sheet resistance ρs of such a diffusion layer is 1.4 kΩ.
I was able to change to / □. The value was 6.2 kΩ / □ when the HF treatment was not performed.

Subsequent steps are manufactured by the same method as the conventional example. With the above method, the minimum gate length is 0.
06μm is realized, and 10μm or less to 0.06μm,
A transistor having a desired gate length could be manufactured.
In addition, the gate oxide film has a thickness of 1.5 nm and a thickness of 2.5
A desired film thickness of less than nm was achieved. The values of the gate length and the gate insulating film thickness are as shown in the transmission electron microscope:
It can be confirmed by TEM (Transmission Electron Microscope) observation.

Results of various characteristic evaluations of the MIS type FET formed as described above will be described below.

FIG. 3 shows hot carrier stress (Vd =
It shows the gate oxide film thickness dependence of the transconductance deterioration under 2.5 V and Isubmax conditions. As shown in this figure, when the gate oxide film thickness is less than 2.5 mm, the deterioration of the transconductance gm is 1% of the deterioration amount in the case of 3 nm, which is conventionally called the limit value at which tunnel current occurs.
Since it becomes / 2, and the life of the transistor is more than doubled, it is desirable to use the thickness of less than 2.5 nm.

Further, if used at 2.0 nm or less,
The lifetime of the transistor is improved by more than 3 times. Therefore,
More preferably it is used at 2.0 nm. When the thickness Tox of the gate oxide film 3 is 2 nm or less, the gate length Lg =
10% or less at 0.10 μm, gate Lg = 0.14 μm
Although it settles at 6% or less in m, a sharp deterioration was observed when it became larger than 2.5 nm.

FIG. 4 shows the dependence of the tunnel current Ig on the gate length Lg. In this figure, gate length Lg
In the case of 0.3 μm or less, the gate width W = 10 μm, the oxide film thickness Tox = less than 0.5 μA at 1.5 nm, and the oxide film thickness Tox =
It stabilized below 0.1 at 1.8 nm. On the other hand, when the gate length Lg exceeds 0.3 μm, a drastic increase in the gate current was observed.

FIG. 5 shows the dependency of the drain current Id0 on the gate length Lg. In this figure, Tox = 1.
When 5 nm and xj = 30 nm (invention), Tox = 1.
When 8 nm and xj = 30 nm (invention), Tox = 3.
The case of 0 nm and xj = 12 nm (conventional example) are shown respectively. As shown in this figure, it can be seen that the driving force is approximately doubled as compared with the conventional one.

FIG. 6 shows the dependence of the tunnel current Ig on the gate length Lg, and FIG. 7 shows the dependence of the conductance gm on the gate length Lg. In these figures, gate oxide film thickness Tox = 1.5 nm, diffusion length xj = 3
In the case of 0 nm (invention), Tox = 1.8 nm, diffusion length x
The case of j = 30 nm (the present invention), the case of Tox = 3.0 nm and the diffusion length xj = 12 nm (prior art) are shown respectively. As is clear from these figures, the transistor of the present invention has a driving force and transconductance that are 1.5 to 2 times better than those of the conventional transistor having the same gate length. Further, the gate current at this time is 10 μm less than the driving force when Lg is 0.3 μm or less.
^{It was 4} or less (4 digits smaller), and it was confirmed that there was no problem in operation.

FIG. 8 shows the dependence of the substrate current Isub on the gate length Lg, and FIG. 9 shows the gate length L of the substrate current impact ionization rate.
It shows the g-dependence, which is one of the indicators for the reliability of the transistor.
Particularly, the substrate current Isub is shown as Vg-Isub characteristic with the gate length Lg as a parameter in FIG. 8B. Here, the gate oxide film thickness Tox = 1.5n
m, diffusion length xj = 30 nm (invention), Tox =
1.8 nm, diffusion length xj = 30 nm (invention),
The case of Tox = 3.0 nm and diffusion length xj = 12 nm (conventional) are shown respectively. The transistor of the present invention has a larger substrate current and impact ionization rate than conventional transistors.

FIG. 17 shows the deterioration characteristic of the transconductance gm (deterioration of the transconductance with respect to the stress time). Here, as a conventional transistor, the oxide film thickness Tox = 3.0 nm, the diffusion length xj =
12 nm, gate length Lg = 0.10 μm, oxide film thickness Tox and diffusion length xj are the same size, and gate length Lg =
For the transistor of the present invention, the oxide film thickness Tox = 1.5 nm and the diffusion length xj =
30 nm, gate length Lg = 0.09 μm, oxide film thickness Tox and diffusion length xj are the same size, and gate length Lg =
The result of having conducted the test for 0.14 micrometers is shown. Although the conventional transistor and the transistor of the present invention have approximately the same time dependence, the transistor of the present invention has a low Δgm / gm value itself, which is gm / gm.
It was confirmed that the deterioration characteristics of (1) were improved.

FIG. 16 shows the dependence of carrier mobility on the effective electric field, which is also an index of the reliability of the transistor. Y.Toyoshima, H.Iwai, F.Matusoka, H.Haya
shida, K, Maeguchi, and K. Kanzaki, 'Analysis on gate-o
xidethickness dependence of hot-carrior-induceddeg
radation in thin-gate oxide nMOSFETs, 'IEEETrans.El
ectron Devices, vol.37, No.6, pp.1496-1503, 1990.) Factors that determine the carrier mobility (1 / μeff) are
Surface roughness scattering (1 / μsr), phonon scattering (1 / μ
ph) and Coulomb scattering (1 / μc), and the overall mobility (1 / μeff) is ln (1 / μeff) = ln ((1 / μc) + (1 / μs)
r) + (1 / μph)). The broken line in the graph indicates the carrier mobility due to each factor, and the solid line indicates the carrier mobility that is the sum of them.

This is because, in FIG. 17, the transistor of the present invention was superior in hot carrier reliability to the transistor of the conventional invention, namely, the deterioration amount (Δgm / gm).
) Was small, as shown in FIG. 12, the effect that the increase of the interface state caused by the hot carrier stress causes the decrease of the driving force due to the deterioration of mobility,
This is because it becomes difficult to see as the gate oxide film thickness becomes thinner. When the oxide film thickness is thin, the electric field in the vertical direction of the channel is very strong, so the mobility is mainly dominated by surface roughness scattering, and the effect of Coulomb scattering due to interface states is
It becomes difficult to appear in mobility.

Therefore, the thin gate oxide film MOSFE
In the case of T, it can be seen that the transistor has good reliability with little deterioration after stress even though the substrate current and the impact ionization rate are large.

FIG. 10 shows the power source voltage Vd of the currents Ig and Id =
It shows Vg dependence. Here, the oxide film thickness Tox
= 1.5 nm, gate length Lg = 0.14 μm, diffusion length x
The case where j = 30 nm is shown. The transistor of the present invention further has an Ig / Id ratio of 1 at 2.0 V or less.
It is less than × 10 ^-4, which shows that there is no problem in operation. Further, when the voltage is 1.5 V or less, the above ratio becomes about 6 × 10 ⁻⁵ or less, and a highly reliable transistor can be realized.

FIG. 11 shows the gate voltage V of the drain current Id.
It shows g dependence. This is measured for the same transistor as the transistor having the characteristics shown in FIG. It was confirmed that the transistor of the present invention obtained a driving force which is 3 to 5 times better than that of the conventionally reported example even under a low voltage.

FIG. 12 shows the dependency of Ig / Id on the drain voltage Vd. As shown in this figure, when the drain voltage Vd was 1.5 V or less, a good value of 6.0 × 10 ⁻⁵ or less was obtained. On the other hand, the drain voltage Vd is 1.5
It can be seen that when V exceeds V, the tunnel current Ig rapidly increases and the characteristics are deteriorated.

Therefore, it can be seen that the transistor of the present invention has good characteristics when used in a circuit of 1.5 V or less.

When the transistor of the present invention is used in a circuit of 1.2V or less, the gate current Ig / Id with respect to the channel current is reduced by about 25% as compared with the 1.5V power supply, and the performance is remarkably improved. In FIG. 10, Ig / I
The value of d is 1.5V, but it is reduced to 4.5 × 10 ^-5 by lowering it to 1.2V from about 6 × 10 ^-5 . The value of the gate current Ig was also reduced by about 50%.

However, the value of the transconductance, which is the performance of the transistor, is 1.5 V as shown in FIG.
Even if the voltage is lowered to 1.2 V with respect to 1.010 ms / mm, it has a value of 995 ms / mm, which is a decrease of 1.5%. Therefore, if used in a circuit of 1.2V or less,
25% improvement in Ig / Id compared to when using a 1.5V power supply will further improve performance dramatically.

The transistor of the present invention has a voltage of 0.5V.
When used in the following circuit, as shown in FIG. 10, it can be seen that the gate leak current is reduced to 1/20 or less as compared with the time of 1.5 V operation. Also, the gate current with respect to the channel current is reduced by about 80%. Therefore, if the transistor of the present invention is used in a circuit of 0.5 V or less, a high-performance transistor with lower power consumption can be realized.

FIG. 13 shows the dependence of the Id-Vd characteristics on the gate length, and FIG. 14 shows the dependence of the conductance gm on the gate length. Here, the gate length Lg is 10 μm
(A), 0.14 μm (b), 0.09 μm (c) Id-Vd characteristics, gm subthreshold characteristics are shown, respectively. The remarkable gate leakage current found in the conventional transistor having a gate length of 10 μm is suppressed in the fine device of the present invention, and Lg = 0.09 μ.
It can be seen that, in m, a high performance of gm = 1010 mS / mm is obtained.

FIG. 15 shows transistor characteristics at a power supply voltage of 0.5 V or less. The power supply voltage at this time is 0.5V. The main characteristics of the present invention and the conventional transistor are shown in comparison with each other. The figure (a) is the transistor characteristic of the present invention, (b) is the conventional transistor characteristic, and the driving force (Id-Vd characteristic, subthreshold characteristic, (log Id -Vg), transconductance (gm) for each. As is clear from this figure, the transistor of the present invention has a large drain current Id flowing with a smaller power supply voltage and a larger conductance gm than that of the conventional transistor. The characteristics of the transistor of the present invention are improved overall, and an excellent transconductance of 746 mS / mm is obtained even at the low power supply voltage of 0.5 V.

FIG. 20 shows the power supply voltage dependence of the transconductance of the transistor of the present invention when the gate length is 0.09 μm and the gate oxide film thickness is 1.5 nm. A very good transconductance of 860 ms / mm is obtained even at 0.5 V operation.

21 and 22 compare the transconductance and the current driving power of the transistor of the present invention with the power supply voltage, in comparison with a conventional transistor having a gate length of 0.4 μm. Gate thickness of 0.4 μm transistor is 9 nm
Is.

In a general-purpose microprocessor operating at 150 MHz, a MOSF having a gate length of about 0.4 μm is currently used.
ET is used, and this FET has a transconductance of about 200 mS / mm under a 3.3 V power supply. Therefore, if the wiring capacitance and resistance are not reduced, the speed cannot be increased, but by analogy with the transconductance of the element, the high driving force M
The OSFET has a possibility of speeding up by about 5.7 times under the low voltage of 1.5 as compared with the current 3.3V operating transistor. Since it has a transconductance of 860 mS / mm even at a low voltage of 0.5 V, the power consumption is about 1/9 compared to the current 3.3 V operation, and it is 5 times faster than the transconductance ratio. There is a possibility of

Currently commercialized LSIs (for example, M
PU microprocessor, etc.) With the power supply voltage of V,
It operates at a clock frequency of 200 MHz.

The transistor of the present invention has a high current driving capability even at a low power supply voltage (for example, 1.5 V or 0.5 V). Therefore, lowering the power supply voltage by lowering the power supply voltage (Note: Power consumption (P) is proportional to the square of the voltage (V), so lowering the power supply voltage is effective for low power consumption operation. However, in general, the voltage drop is
This results in a reduction in the current driving force of the transistor, which leads to a reduction in the operating speed of the LSI. ), L
It is possible to further speed up the SI operation.

The power consumption of the LSI can be expressed by the following equation. P = kfcV _dd ² + (I _ls + I _lg ) V _dd Where, P: power consumption f: clock frequency c: capacitance V _dd : power supply voltage I _ls : leak current I _lg : gate leak current that can be used for subthreshold characteristics In the equation, the first term kfcV _dd ² is power consumed by charge accumulation and erasing (charge-discharge), and the second term (I _ls + I _lg ) is power consumed by the leakage current component of the transistor. Is.

The clock frequency f is a value determined by the current driving force I of the transistor.

The charge storage time t is

T = Q / I = CV / I and can be represented by f = I / CV.

Here, the power consumption per chip is 10
The relationship between the power consumption and the clock frequency of the transistor of the present invention and the transistor of the conventional structure is shown with W and the number of chip transistors is 3 × 10 ⁶ (FIG. 25).

Here, the threshold voltage of each transistor is designed such that the threshold voltage is 1 μA / μm, 0.6 V at 3.3 V power supply, 0.4 V at 2.0 V power supply, and 0.3 V at 1.5 V power supply. It was set to 0.2V with a 1.0V power supply, 0.15V with a 0.5V power supply, and 0.1V with a 0.3V power supply.

The relationship between the power consumption (P) and the clock frequency (f) can be divided into a region determined by charge accumulation and erase and a region determined by leak current.

Then, as shown in FIG. 25B, the component of the leak current determined by the subthreshold characteristic is
From each threshold voltage, the threshold voltage is 0.3 V at the value of 1.5 V power supply voltage, and the power consumption due to the leak current is 4.5 mW. Similarly, it is 30 mW at 1.0 V power supply voltage, 45 mW at 0.5 V power supply voltage, and 100 mW at 0.3 V power supply voltage.

On the other hand, when the tunnel gate oxide film of the present invention is used (Lg = 0.14 μm, Tox = 1.5 nm), the leak current is 6 × 10 ⁻⁸ A / μm at 1.5 V power supply. The gate width of each transistor is 10μ
When m and the number of transistors are 3 × 10 ⁶ , the power consumption component due to the leak current is 2.7 W.

In each case, when the gate oxide film thickness is 1.5 nm and Lg = 0.14 μm, the power supply voltage is 1.5 V, 2.7 mW, 1.0 V power supply voltage, 600 mW, and 0.5 V power supply voltage. 45mW, 0.3mW at 0.3V power supply voltage Lg = 0.09μm, 1.5V power supply voltage at 540mW, 1.0V power supply voltage at 120mW, 0.5V power supply voltage at 9mW, 0.3V power supply voltage at 1 It is 0.3 mW.

On the other hand, as shown in FIG. 25A, the power consumption determined by charge accumulation and erasure is the normal Lg = 0.
Based on 3.3V operation of a 4 μm, Tox = 9 nm transistor, the drive of this transistor is 0.40 mA.
/ Μm.

The transistor of the present invention has Lg = 0.14.
1.5V for a transistor with μm and Tox = 1.5nm
Power consumption is 1.2 times and clock frequency is 5.7
It is twice. In 0.5V operation, power consumption is 0.047
And the clock frequency is 2.1 times.

Lg = 0.09 μm, Tox = 1.5
In the case of a 1.5 nm transistor, the power consumption becomes 1.8 times and the clock frequency becomes 8.6 times. With 0.5V operation, the power consumption is 0.11 times and the clock frequency is 4.9 times.

Further, the above-mentioned gate leak current component is about one order of magnitude smaller than the essential power consumption component consumed by charge storage / erasure, and is not a problem.

Therefore, as shown in FIG.
Compared to an LSI operating at 200 MHz and 3.3 V, the transistor of the present invention consumes 5 times as much high frequency power (about 1000 GHz) at 1.5 V and consumes 1/9 less power at 0.5 V. Five times higher clock operation is possible.

If it is operated at 200 MHz,
The power supply voltage can be reduced to 0.3 V, and the power consumption can be reduced to 1/100 of 100 mW or less.

Further, this transistor has a high transconductance even under a low voltage (1,0 at 1.5 V).
(10 mS / mm, 860 mS / mm at 0.5 V, and about 200 mS / mm at 3.3 V in the past), so high-frequency analog operation of about 5 times that of the current is possible under low voltage.

For example, a high frequency analog IC for communication of 1 to several tens GHz operation mainly uses a transistor such as bipolar or GaAs, which is a CMO of the present invention.
It becomes possible to replace with S.

In order to achieve high integration and high speed of LSI, miniaturization of MOS type transistors has been conventionally performed. Of course, in order to increase the speed, it is important to reduce the wiring capacitance and resistance, and to reduce the parasitic capacitance and parasitic resistance of the element, but miniaturization of the element itself is also a key to high driving force. . In the future, in order to reduce the power consumption, it is required to use the device under a lower voltage, but how to form a transistor with a high driving force under a low voltage is an important issue.

In addition, usually, for example, in the literature (author GG.
Shahidi, J.Warnock, A.Acovic, P.Agnello, C.Blair, C.Bu
celot, A.Burghartz, E.Crabbe, J.Cressler, P.Coane, J.Co
mfort, B.Davarl, S.Fischer, E.Ganin, S.Gittleman, J.Kel
ler, K.Jenkins, D.Klans, K.Kiewtniak, T.Lu, PAMcFarla
nd, T.Ning, M.Polcari, S.Subbana, JYSun, D.Sunderlan
d, ACWarren, C.Wong ； Paper name A HIGH PERFORMANCE 0.15
μm CMOS ； Source Dig. of Tech. Papers, VLSI Symp. on
Tech., Kyoto, PP.93-94,1993 = hereinafter referred to as document [a])
As shown in FIG.
480 ms / mm or less, pMOS 250 ms / mm
The following transconductance gm is only obtained. Therefore, with the transistor of this reference [a], even with a 1.5 V power supply, the above-mentioned 480 ms /
Only values of mm, 250 ms / mm are obtained. On the other hand, the literature (author Y.Taur, S.Wind, YJMii, Y.Lii, D.Moy, K.
A.Jenkins, CLChen, PJCoane, D.Klaus, J.Bucchignan
o, M.Rosenfield, MGRThomson, and M.Polcari; Paper name High Performance 0.1μm CMOS Device with 1.5VP
ower Supply ； Source IEDM Tech.Dig., pp.127-130,1993
= 1.5V in the case shown in the following document [C])
Power source nMOS is 620 ms / mm, pMOS is 290
Only values of ms / mm have been obtained. In addition, literature (authors Y.Mii.S.Rishton, Y.Teur, D.Kern, T.Lii, K.Lee, K.
Jenkins, D.Quinlan, T.Brown Jr., D.Danner, F.Sewell, an
d M. Polcari; Paper name High Performance 0.1 μm nMOSF
ET's with10ps / stage Delay (85K) at 1.5V Power Supp
ly; Source Dig. of Tech.Pater, VLSI Symp. on Tech., Ky
oto, pp91-92,1993) does not describe the power supply voltage, but n
It is shown that a value of 740 ms / mm is obtained with the MOS. Also, for example, in the literature (author Y.Mii, S.Wind,
Y.Lii, D.Klaus, and J.Bucchignano ； Paper name An Ultra-Lo
w Power 0.1 μm CMOS; Source Dig. of Tech.Papers, VLS
I Symp. On Tech., Hawaii, pp.9-10,1994 = hereinafter referred to as reference [B]) shows that the nMOS is 340 ms / mm and the pMOS is 140 ms at 0.5 V power supply.
Only a transconductance gm of less than / mm is obtained. Therefore, with a power supply of 1.5 V or more, nMOS is 620 ms / mm or more, pMOS is 290 ms / mm or more, and with a power supply of 1.2 V or more, nMOS is 540 ms / mm or more.
As described above, in order for the pMOS to have the performance of 245 ms / mm or more, the power supply of 0.5 V or more, the nMOS to have the performance of 340 ms / mm or more, and the pMOS to have the performance of 140 ms / mm or more, it is necessary to have the configuration of the present invention as the structure of the transistor. Is.

Similarly, with respect to the current driving force, as shown in the document [B], for example, nM is normally obtained with a 0.5 V power supply.
OS is 0.052mA / μm, pMOS is 0.032m
It remains at A / μm. Also, with a 1.5 V power supply, as shown in the literature [C], nMOS has 0.65 mA / μ.
m and pMOS remain at 0.3 mA / μm. Therefore, with a power supply of 1.5 V or more, nMOS is 0.65 mA.
/ Μm or more, pMOS is 0.30 mA / μm or more, 1.
NMOS is 0.47mA / μm or more with a power supply of 2V or more,
In order to obtain a driving force of nMOS of 0.052 mA / μm or more and pMOS of 0.032 mA / μm or more with a power supply of pMOS of 0.22 mA / μm or more and 0.5 V or more, the structure of the present invention is adopted as a transistor structure. It is necessary to have.

The values of the mutual conductance and the current driving force described above are characteristic values at room temperature.

Therefore, under a certain power supply voltage (VDD), n
A feature of the present invention is a structure in which gm ≧ 280 VDD + 200 in MOS and gm ≧ 150 VDD + 65 in pMOS. The unit is VDD (V),
It is gm (ms / mm).

The present invention is characterized in that the current driving capability of the nMOS is Id ≥0.598 VDD-0.247 and that of the pMOS Id ≥0.268 VDD-0.102. The unit is VDD (V),
Id (mA).

Regarding these values, the values of the gate length are not particularly described, but the values are all around 0.1 μm.

The driving force of the MOSFET is effective in improving the driving force by shortening the gate length and increasing the electric field of the channel to increase the speed of electrons and holes.
As is well known, in the method of shortening the gate length and strengthening the channel electric field, when the gate length is 0.1 μm or less, in principle, velocity saturation (when the electric field of the channel becomes strong to some extent, , The phenomenon that the speed of electrons and holes saturates and does not improve even when the electric field becomes stronger.), And the speedup was becoming saturated.

As a fine-gate MOSFET last year,
We manufactured the world's smallest nMOSFET with a gate length of 0.04 μm and reported its room temperature operation.
The improvement was only 20 to 30% of that of a transistor having a gate length of 0.1 μm.

Therefore, the values of the transconductance and the driving force described above cannot be realized by the conventional method, even if the gate length is not specified, and can be realized by the transistor having the structure of the present invention.

As described above, according to the present invention, it is possible to realize a transistor having better driving force and reliability than the conventional one.

Although the silicon oxide film is used as the gate insulating film in the above description, the present invention has the same effect even if an insulating film having a gate capacitance equivalent to that is used. As the insulating film, for example, a silicon nitride film (Si3 N4),
Silicon nitride oxide film (SiOx Ny) Laminated film of silicon nitride film and silicon oxide film (SiO2 / Si3 N4, Si)
3 N4 / SiO2, SiO2 / Si3 N4 / SiO2,
SiN4 / SiO2 / N4) or tantalum oxide (Ta Ox), strontium titanate film (TiSr)
xOy) There is a laminated film of them and a silicon oxide film or a silicon nitride film. If the gate capacitance of these insulating films is equivalent to a silicon oxide film thickness of less than 2.5 nm, the effect of the present invention can be obtained. For example, the relative dielectric constant 7.9 of the silicon nitride film is about twice that of the silicon oxide film 3.9, and when the silicon nitride film is used, the film thickness is 5n.
When it is less than m, the effect of the present invention can be obtained. In the case of using any of the above-mentioned insulating films, even if a tunnel leak current flows in this gate insulating film, it is consistent with the gist that a transistor is configured with an insulating film thickness through which a tunnel current flows in a silicon oxide film, Has the same effect. Further, if the insulating film has a gate capacitance equivalent to that of the above-described silicon oxide film of less than 2.5 nm, tunnel current does not flow, power consumption is reduced, and a high-performance transistor with low power consumption can be realized.

For example, 10 ^-8 per transistor
100 MOSFETs with gate tunnel leakage of A
If 10,000 pieces are integrated, 10 mA of power will be consumed. On the other hand, when a transistor through which a tunnel current does not flow is used, the power consumption of 10 mA is suppressed, and the performance of the LSI can be improved.

When the transistor of the present invention is used as a part of a semiconductor device, a high-performance and inexpensive semiconductor device can be realized.

FIG. 18 is a schematic view of a semiconductor device in which the transistor of the present invention is used as a part of the semiconductor device. Especially in the peripheral circuits that are required to be driven with a large current,
It is preferable to use the transistor of the present invention as shown in FIG. Such a semiconductor device can be manufactured by the following manufacturing method.

After the element region and the element isolation region are formed on the semiconductor substrate by the conventional method, the element region and the element isolation region are formed by, for example, a furnace oxidation method.
Oxide the silicon surface in an oxygen atmosphere at 0 ° C.
Forming a silicon oxide film. After that, the first silicon oxide film is removed only in the transistor formation region of the present invention. After that, a second silicon oxide film having a desired film thickness is formed by a rapid lamp heating method. Subsequent steps are manufactured through the same steps as the method for forming a transistor of the present invention described above.

In the semiconductor device thus manufactured, the high-performance transistor manufactured according to the present invention is formed in a region where a transistor driven by a large current is required, so that the semiconductor device becomes an excellent semiconductor device as a whole. Conventionally, for example, in a high-speed logic device, as shown in FIG.
(O portion) is formed by a bipolar transistor, and an internal logic circuit is formed by a CMOS transistor to increase the speed.

By using the present invention, it is possible to manufacture the semiconductor device only by the CMOS process, and it is possible to realize a high-performance element at a low cost.

In the present embodiment, especially nMOSFET
However, this structure is similar to pMOSFE.
It can also be applied to T. In this case, the gate sidewall is BSG
(Formed of B (boron) -containing silicon oxide film) and has a shallow p
The source / drain regions of the mold may be formed. This is in the literature (author M. Saito, T. Yoshitomi, H. Hara, M. Ono, Y. Akasak
a, H.Nii, S.Matsuda, HS Momose, Y.Katsumata, and H.Iwa
i; Paper name P-MOSFETs with Ultra-Shallow Solid-Phase-
Diffused Drain StructureProduced by Diffusion from
BSG Gate-Sidewall ； Source IEEE Trans.Electron Devic
es, vol.ED-40, no.12, pp.2264-2272, December, 1993).

Further, as described above, the source / drain diffusion layer may be formed by a usual B (boron) atom ion implantation method instead of the solid-phase diffusion technique from the BSG side wall.

FIG. 24 shows the electrical characteristics of the p-type MOSFET in which the source / drain diffusion layers are formed by the ion implantation method. At this time, the gate oxide film thickness is 1.5 nm and the gate length is 0.2 μm. PMOSFE produced by the present invention
T is a 1.5V power supply, 0.41 mA / μm current driving force,
And a transconductance of 408 ms / mm, and the literature (authors Y.Taur, S.Wind, YJMii, Y.Lii, D.Moy, KAJenk).
ins, CLChen, PJCoane, D.Klaus, J.Bucchignano, MG
R. Thomson, and M. Polcari; Paper name “High Performance
0.1μm CMOS Devices with 1.5V Power Supply; Source IED
M Tech. Dig., Pp.127-130, 1993), the performance value of the 0.2 μm gate length pMOSFET is about 200.
It has a high performance that greatly exceeds ms / mm. Also this T
For r, a driving force of 0.06 mA / μm and a transconductance of about 350 ms / mm are obtained with a 0.5 V power supply.

In this embodiment, the diffusion layer depth is 3
Although the description has been given using the example of 0 nm, the desired diffusion layer depth can be freely selected by appropriately selecting the temperature and time of the annealing conditions for diffusion and activation between 700 ° C. and 1,100 ° C. be able to.

In FIG. 23, the ratio Ig / Id of the gate current Ig to the channel current Id is the oxide film thickness Tox and the gate length L.
This shows how g changes. Ratio Ig / Id
Are the same when compared to the case where the oxide film thickness is 1.5 nm.
In the case of 0% thick 1.8 nm, the gate length is 1.5
It can be seen that the same amount of leak current is generated when shortening to 1/2 of nm.

As shown in FIG. 12, when 6 × 10 ^-5 , which is the point at which Ig / Id rapidly increases, is set as the limit value, and the gate length Lg and the insulating film thickness Tox that have the following characteristics are preferable, The following formula is established. Limit of 6 × 10 ^-5
When there is an Ig / Id ratio, Tox (nm) = logLg (μm) +2.02 Therefore, the allowable gate length Lg (μm) for a certain insulating film thickness Tox (nm) is Lg ≦ 10 ^{(Tox- 2.02) When the} gate current, which is the power consumption, is further reduced to improve the integration degree of the LSI and it is applied to 1 million (1M (mega) bit) memory, the influence on the power consumption of the LSI is about 10 mA. And Assuming that the transistor gate current per transistor is 10 ^-8 A / μm, FIG. 6 shows that this diagram is described by the gate current per 10 μm gate width, so 10 ^-8 A / μm When Tox = 1.5 nm, 0.15 μm and Tox = 1.
When it is 8 nm, it is 0.30 μm.

Tox (nm) = logLg (μm) +2.32 Therefore, the allowable gate length Lg (μ
If the value of m) is Lg ≤ 10 ^(Tox-2.32) , the performance is further improved and it can be applied to an LSI having a high degree of integration.

[0088]

As described above, according to the present invention, by making the thickness of the gate insulating film less than 2.5 nm,
By improving the reliability under hot carrier stress and reducing the gate length to 0.3 μm or less,
The tunnel current Ig from the drain electrode to the gate electrode can be reduced, and the transistor characteristics can be improved. Further, if it is used at a power supply voltage of 1.5 V or less, a transistor with higher reliability can be realized.

[Brief description of drawings]

FIG. 1 is an element sectional view showing a structure of a MOS transistor according to an embodiment of the present invention.

FIG. 2 is an impurity concentration profile diagram of the transistor shown in FIG.

FIG. 3 shows hot carrier stress (V
The curve figure which shows the gate oxide film thickness dependence of the deterioration amount of transconductance under d = 2.5V, Isubmax, and 1000 second stress application.

FIG. 4 is a curve diagram (W = 10 μm) showing the gate length Lg dependence of the tunnel current Ig of the transistor.

FIG. 5 is a curve diagram (W = 10 μm) showing the gate length Lg dependence of the drain current Id0 of the transistor.

FIG. 6 is a curve diagram (W = 10 μm) showing the dependence of the tunnel current Ig of the same transistor on the gate length Lg.

FIG. 7 is a curve diagram (W = 10 μm) showing the dependence of the conductance gm of the transistor on the gate length Lg.

FIG. 8 is a curve diagram (W = 10 μm) showing the gate length Lg dependence of the substrate maximum current Isubmax of the same transistor (a) and a curve diagram (W = 10 μm) (W = 10 μm) (a) showing the gate voltage dependence of the substrate current Isub of the transistor. b).

FIG. 9 is a curve diagram (W = 10 μm) showing the dependence of the impact ionization rate of the same transistor on the gate length Lg.

FIG. 10 is a curve diagram (Lg = 0.14 μm, showing the dependence of the currents Ig and Id of the transistor on the power supply voltage Vd = Vg).
W = 10 μm).

FIG. 11 is a curve diagram showing the dependency of the drain current Id of the transistor on the power supply voltage Vd = Vg.

FIG. 12 is a diagram showing a power supply voltage (V) of Ig / Id of the transistor.
The curve figure which shows d = Vg) dependence.

FIG. 13 is a curve diagram showing the gate length dependence of Id-Vd characteristics of the transistor.

FIG. 14 is a curve diagram showing the gate length dependence of the conductance gm of the transistor.

FIG. 15 is a curve diagram showing the main characteristics of the transistor of the present invention in comparison with the characteristics of a conventional transistor (power supply voltage 0.5 V).

FIG. 16 is a curve diagram showing the dependence of carrier mobility on the effective electric field.

FIG. 17 is a curve diagram showing characteristics of deterioration of conductance gm (degradation of transconductance with respect to stress time) of a MOS transistor according to an example of the present invention.

FIG. 18 is an example of a semiconductor device according to the present invention, a semiconductor device (a) in which a semiconductor device in the entire region is manufactured using the MOSFET of the present invention, a semiconductor device (b) in which the MOSFET of the present invention is manufactured in a partial region, and MOSF of the present invention in the peripheral region
The schematic explanatory drawing which shows the structure of the semiconductor device (c) which produced ET.

FIG. 19 is a schematic explanatory diagram showing a configuration of a conventional example of a high-speed semiconductor device formed of a bipolar transistor and a CMOS transistor.

FIG. 20 is a curve diagram showing the voltage dependence of the transconductance of a transistor having Lg = 0.09 μm and Tox = 1.5 nm.

FIG. 21 is a curve diagram showing the power supply voltage dependence of mutual conductance.

FIG. 22 is a curve diagram showing the power supply voltage dependency of the current driving force per unit.

FIG. 23 is a curve diagram showing the gate current ratio Ig / Id with respect to the channel current with respect to the gate length Lg.

FIG. 24: Tox = 1.5 nm, Lg = 0.2 μm pM
Characteristics of OS transistor (Id-Vd characteristics (a), gm
The curve figure which shows -Vg characteristic (b).

FIG. 25 shows Lg = 0.4 μm, Tox = 9 nm transistor (conventional example), Lg = 0.1 μm, Tox = 3 nm transistor (conventional example), Lg = 0.14 μm and Lg = 0.
For a 09 μm, Tox = 1.5 nm transistor (present invention), the relationship between the clock frequency and the power consumption determined by charge storage / erasure and subthreshold leakage (a), and the relationship between the clock frequency and the power consumption component determined by the gate leakage current FIG. 6B is a curve diagram showing the relationship between power consumption and clock frequency when all transistors have the same power consumption or the same clock frequency condition, and FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 gate electrode 3 gate oxide film 4 channel formation region 5 source region 6 drain region 7 gate power supply 8 drain power supply

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Tatsuya Oguro, Inventor Tatsuya Oguro, Komukai-shi Toshiba-cho, Kawasaki-shi, Kanagawa 1 Within Toshiba R & D Center, Inc. Komukai Toshiba Town 1 Co., Ltd. Toshiba Research and Development Center (72) Inventor Takashi Yoshitomi Komukai Toshiba Town 1 Kawakami City, Kanagawa Prefecture Komukai Toshiba Research and Development Center (72) Inventor Shinichi Nakamura Kanagawa Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Japan Stock Company Toshiba Research and Development Center

Claims (14)

[Claims] 1. A semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via an insulating film, and formed on both sides of a channel formation region located immediately below the gate electrode of the semiconductor substrate. A semiconductor device comprising a source / drain region of the second conductivity type, wherein the insulating film has a thickness of 2.0 nm or less and the gate electrode has a gate length of 0.3 μm or less. 2. A semiconductor device comprising the semiconductor device according to claim 1 in a part of the semiconductor device. 3. The semiconductor device according to claim 1, wherein a tunnel current flows through the insulating film during operation of the semiconductor device. 4. The film thickness of the insulating film is 2.0 in terms of oxide film thickness.
The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of not more than nm. 5. A semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via a gate insulating film, and formed on both sides of a channel formation region located directly under the gate electrode of the semiconductor substrate. In a MOS semiconductor device having a second conductivity type source / drain region, the relationship between the length (Lg) of the gate electrode in the channel direction and the thickness (tox) of the gate insulating film has the following relationship. A semiconductor device characterized by satisfying. Lg ≤ 10 ^(Tox-2.02) At this time, the unit of Lg is (μm) and the unit of Tox is (nm) 6. A semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via an insulating film, and formed on both sides of a channel formation region located directly below the gate electrode of the semiconductor substrate. A source / drain region of the second conductivity type, the insulating film has a thickness of 2.0 nm or less, the gate length of the gate electrode is 0.3 μm or less, and a voltage applied to the gate electrode and the drain region. Is 1.5 V or less, a semiconductor device. 7. The semiconductor device according to claim 6, wherein the voltage applied to the gate electrode is 0.5 V or less. 8. A semiconductor device comprising the semiconductor device according to claim 6 as part of the semiconductor device. 9. The semiconductor device according to claim 6, wherein a tunnel current flows through the insulating film during operation of the semiconductor device. 10. The film thickness of the insulating film is 2.
7. The semiconductor device according to claim 6, wherein the thickness is 0 nm or less. 11. A semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via an insulating film, and formed on both sides of a channel formation region located directly below the gate electrode of the semiconductor substrate. A semiconductor having a source / drain region of the second conductivity type and having a mutual conductance (gm) of gm ≧ 280 VDD + 200 in nMOS and gm ≧ 150 VDD + 65 in pMOS where VDD (V) and gm (ms / mm) are units. apparatus. 12. The voltage applied to the gate electrode and the drain region is 1.5 V or less.
1. The semiconductor device according to 1. 13. The voltage applied to the gate electrode and the drain region is 0.5 V or less.
2. The semiconductor device according to 2. 14. The semiconductor device according to claim 11, wherein a tunnel current flows through the insulating film during operation of the semiconductor device.