JPH08211406A - Active matrix display element - Google Patents

Abstract

PURPOSE: To decrease the leakage current of a polycrystalline silicon TFT by relatively determining the values of the capacitance between light shielding films and respective inter- electrode wirings and between pixel electrodes in such a manner that the potential of the light shielding films enter in the range of the specific min. potential of the light shielding films. CONSTITUTION: The light shielding films 8 are formed separately by each of respective pixels and are insulated and are provided with the overlaps with insulating films 7 between the light shielding films 8 and gate electrodes 1a wirings, between the light shielding films 8 and source electrode wirings 3 and between the hight shielding film 8 and the pixel electrode 4. The capacitance between the light shielding films 8 and the gate electrode wirings is defined as C1 , the capacitance between the light shielding films 8 and the source electrode wirings 3 as C2 and the capacitance between the light shielding films 8 and the pixel electrodes 4 as C3 . The values of C1 to C3 are then relatively determined in such a manner that the potential VB of the light shielding films enters in the range of VBMIN±2V if the potential VB of the light shielding films at which the parasitic channel current of the polycrystal semiconductor TFTs is nearly minimized is defined as the min. potential VBMIN of the light shielding films at the time the thin-film transistors (TFTs) is brought into a non-selection state by impression of the max. effective voltage between the sources and the drains and impression of the off voltage on the gate electrodes 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device having a thin film transistor (hereinafter referred to as TFT) using a polycrystalline semiconductor as a channel. Specifically, it relates to a liquid crystal display device driven by a TFT.

[0002]

2. Description of the Related Art In recent years, flat panel display devices such as liquid crystal display devices have been widely used in various fields. Among them, the active matrix display element is superior to the simple matrix display element in terms of display density, viewing angle, contrast and the like. A TFT is usually used as a switching element of an active matrix display element.

Among TFTs having various structural forms, amorphous silicon TF is easy to form.
T is widely used. However, since the amorphous silicon TFT has a low carrier mobility, it is difficult to obtain a high-speed switching operation. Therefore, it is not possible to meet the demands for high aperture ratio and drive circuit integration, which are required for high-performance display elements.

Therefore, a polycrystalline silicon TFT, which has a relatively higher carrier mobility than an amorphous silicon TFT, is expected as a driving element for high performance display elements in the future.

Next, a conventional technique concerning light shielding (back surface light shielding) on the substrate side of the top gate type TFT will be described. First, in Conventional Example 1 (Japanese Patent Laid-Open No. 60-216377), the light-shielding film and the source electrode wiring are used in common for the element structure of the amorphous silicon TFT. In addition, conventional example 2
(JP-A-4-20935) is characterized in that the light-shielding film and the storage capacitor are formed in the same layer with the same material. In these conventional techniques, a polycrystalline semiconductor TFT is used.
In particular, the influence of the potential of the light-shielding film on the leak current, which is particularly problematic, is not considered.

Further, in Japanese Patent Application No. 6-201116, in order to reduce the leak current of the polycrystalline semiconductor TFT, a specific light-shielding film potential lower than the gate selection potential and higher than the gate non-selection potential is applied to the conductive light-shielding film. Has been shown to do.

[0007]

Generally, a polycrystalline silicon TFT has a characteristic that, when irradiated with light, a leak current increases when the gate is deselected (off state). Therefore, when used as a switching element for driving the pixels of the liquid crystal display element, it is preferable to provide some light shielding. However, in a top-gate type polycrystalline silicon TFT, a structure that blocks light from the back side of the TFT element structure and does not impair the TFT characteristics has not been heretofore known.

The top gate type of the present invention refers to a structure in which the gate electrode is provided on the side opposite to the substrate when viewed from the channel. A coplanar TFT, a forward stagger TFT, or the like has this structure.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and is provided with a pixel electrode and a top gate type polycrystalline semiconductor TFT as a driving element for driving the pixel electrode. A first substrate, a second substrate provided with a counter electrode facing the pixel electrode, and a light control layer provided between the first substrate and the second substrate are provided. An active matrix display element in which an insulating film and a conductive light-shielding film are provided between a channel of a crystalline semiconductor TFT and the insulating film is disposed between the channel and the light-shielding film, and the light-shielding film is provided for each pixel. Are formed separately and insulated from each other, and there is no overlap between the light-shielding film and the gate electrode wiring, between the light-shielding film and the source electrode wiring, and between the light-shielding film and the pixel electrode with the insulating film. Provided between the light shielding film and the gate electrode wiring C ₁ capacity, and the capacitance between the light shielding film and the source electrode wiring C _2, and the capacitance between the shielding film and the pixel electrode and C _3, the maximum effective voltage is applied between the source and the drain, and the gate electrode OFF voltage is applied and T
When the light-shielding film potential V _{B at} which the parasitic channel current of the polycrystalline semiconductor TFT is almost minimum when the FT non-selection state is set to the minimum light-shielding film potential V _BMIN , the light-shielding film potential V _B = the minimum light-shielding film potential V as fall within the _{BMIN ± 2V, C 1, C} 2
And a value of C ₃ are relatively determined, to provide an active matrix display device. This is called the first invention. When determining the capacitance values of C ₁ , C ₂ and C ₃ , the effective capacitive coupling portion is included in each region of the conductive potentials that are continuously connected on the pattern.

Normally, during operation of the TFT, a gate selection potential or a gate non-selection potential is applied to the gate electrode of the polycrystalline semiconductor TFT, and a source electrode is higher than the gate non-selection potential and higher than the gate selection potential. The source signal potential in the low range is applied, and the counter electrode potential higher than the gate non-selection potential and lower than the gate selection potential is applied to the counter electrode.

In the present invention, the light-shielding film is insulated from each electrode of the TFT, the storage capacitance line, or the potential of a specific circuit terminal. In other words, the light-shielding film has a floating potential as a conductor capacitively coupled to other circuit parts.
Then, the main parasitic capacitance structure on the back surface side of the TFT is set so that the potential V _{B of the} light-shielding film is higher than the gate non-selection potential and lower than the counter electrode potential and is a constant potential in the TFT non-selection state. To do. Then, when the gate is not selected during normal operation, the light-shielding film potential V _B is set within a certain range.

Further, in the first invention, C ₁ , C
Provided is an active matrix display device characterized in that ₂ and C ₃ satisfy the following relationship of the following expression 2. This is called the second invention.

[0013]

## EQU2 ## 0.6 × C ₁ ≦ C ₂ ≦ 5 × C ₁ 0.6 × C ₁ ≦ C ₃ ≦ 5 × C ₁ 0.8 × C ₂ ≦ C ₃ ≦ 1.2 × C ₂

The present invention will be described in detail below.
The thickness of the insulating film provided on the rear surface side of the channel portion of the polycrystalline semiconductor TFT of the present invention is 100 to 1000 n.
m, preferably 200-500 nm is used. The thicker the film thickness, the smaller the effect of the back surface MIS capacitance.

The material used for the insulating film is Si.
O ₂ (dielectric constant 3.9), Si ₃ N ₄ (dielectric constant 7.5),
An insulating film such as SiO _X N _Y (dielectric constant 4 to 7) or tantalum oxide may be used. Considering the magnitude of the back surface MIS capacitance effect, it is preferable that the dielectric constant of the insulating film is low.

The present invention will be described below with reference to the drawings. FIG. 1 schematically shows a cross section of a polycrystalline semiconductor TFT used in the active matrix display element of the present invention, and FIG. 2 is a partial plan view of the vicinity of the polycrystalline semiconductor TFT of the active matrix display element.

The polycrystalline silicon layer 5 of FIG. 2 is formed as an I-shaped silicon island. The gate electrode wiring 1 and the source electrode wiring 3 are arranged substantially orthogonal to each other. The gate electrode 1a is formed by extending from the gate electrode wiring 1. A connecting portion 3a for connecting to the source electrode of the TFT is formed by extending from the source electrode wiring 3. The pixel electrode 4 is connected to the drain electrode of the TFT. Then, there is a planar overlap between the source electrode wiring 3, the gate electrode wiring 1, and the pixel electrode 4 and the silicon island located below them.

In this polycrystalline semiconductor TFT, the gate electrode 1a, the gate insulating film 2, the source electrode wiring 3 (the connection portion 3a with the source electrode of the TFT), the pixel electrode 4 (the connection portion 4a with the drain electrode of the TFT). , A polycrystalline silicon layer 5 functioning as a channel, an interlayer insulating film 6, an insulating film 7, and a light shielding film 8
Are provided on the glass substrate 9. Gate electrode 1a
A gate offset structure is formed in the gate portion constituted by the gate insulating film 2 and the leak current can be reduced.

If the light-shielding film 8 is conductive, the TFT
On the non-gate side of the channel of the element structure (the lower side of the paper surface shown in FIG. 1, that is, the lower side of the channel), the capacitance structure 10 similar to the original gate portion is formed. Insulating films are also sandwiched between the gate electrode wiring 1 and the conductive light shielding film 8, between the source electrode wiring 3 and the conductive light shielding film 8, and between the pixel electrode 4 and the conductive light shielding film 8. Capacitive structure 11, 12, 1
3 are formed respectively.

FIG. 3 shows an example of examining the electrical contribution of the above-described capacitive structure 10 below the channel at the gate voltage of the polycrystalline silicon TFT when the gate is not selected (the TFT is in the off state as the operation). . The horizontal axis represents the light-shielding film potential, and the vertical axis represents the source / drain current.

That is, a constant rated voltage was applied to the source and drain, an off voltage was applied to the gate electrode, and a voltage was externally applied to the light-shielding film to measure the current between the source and drain. The source / drain current in this case means a leak current which is unnecessary for the desired operation of the TFT.

The TFT element structure was a dual gate, and its channel length was 10 μm, channel width was 4 μm, and gate offset was 2.4 μm in total. The insulating film 7 is S
formed by iO _2, film thickness was 800 nm.

The source-drain voltage is 14V,
When the gate potential was set to -5 V, which corresponds to the gate-off state, the potential of the light-shielding film 8 was varied and the leak current (source drain current) was measured. That is, when performing this measurement, a voltage is applied from the outside to determine the potential of the conductive light-shielding film. During the actual operation of the polycrystalline semiconductor TFT, the light shielding film 8 is in an insulated state in which it is not directly coupled to each potential of each external circuit and has a floating potential. The floating potential is determined by capacitively coupling with the potentials of other circuits.

It can be seen from FIG. 3 that the leak current greatly changes depending on the potential of the light shielding film 8. Then, there exists the minimum light-shielding film potential (V _BMIN (V)) that gives the minimum value. Alternatively, there is a range of the light-shielding film potential V _B that gives the saddle part of the characteristic curve. Further, it was found that the minimum light-shielding film potential V _BMIN that gives the minimum value of the leak current changes greatly depending on the gate voltage. The minimum value of the leak current becomes smaller as the capacitance of the capacitive structure 10 becomes smaller. Minimum light-shielding film potential V
The value of _B itself is the fixed charge in the insulating film 7 on the light shielding film 8,
Alternatively, it depends on the interface state with the silicon film 5. Since the characteristic curve has an almost monotonic tendency, the minimum value ≈ the minimum value of the saddle.

As described above, in the structure of the driving element of the pixel having the polycrystalline silicon TFT as a constituent element, in order to suppress the leakage current to a low level, the leakage current due to the capacitive structure 10 is caused at the off potential of the gate when the gate is not selected. It is preferable to suppress. It is preferable to set the floating potential of the light-shielding film 8 so as to be located at the saddle portion of the characteristic curve in which the contribution of the leakage current as shown in FIG. Specifically, it is provided so as to fall within the range of ± 2.0 V of the minimum light-shielding film potential V _BMIN which gives the minimum value of the characteristic curve or a value in the vicinity thereof.
Depending on the relationship with the operating voltage range used, etc., it is preferably set within ± 1.5 V, more preferably within ± 1.0 V.

In other words, in terms of the function as a display element,
When the TFT is turned off, the display is not affected within the range.
It is enough to suppress the current. In addition, the minimum light-shielding film potential V_BMINIs
Depending on the type of insulating film material, etc.
Exists. Minimum light-shielding film potential V _BMINC when = 1V₂ /
C₁ ≈0.6, minimum light-shielding film potential V_BMIN= 5V C
₂ / C₁ It is preferable to provide so that ≈5.

In the case of the TFT shown in FIGS. 1 and 2, this light-shielding film potential V _B is between the gate electrode wiring 1 and the conductive light-shielding film 8 and between the source electrode wiring 3 and the conductive light-shielding film. Capacitance structures 11, 12, 13 in which insulating films are sandwiched between the films 8 and between the pixel electrode 4 and the conductive light-shielding film 8 are also provided.
It is mainly determined by the effective ratio and the potential of each electrode. Further, although capacitive coupling can be provided in an oblique direction other than the substrate vertical direction, the amount of capacitive coupling in the substrate vertical direction may be mainly considered.

When the gate of the TFT is not selected, the leak current is most remarkable when the potential difference between the source electrode and the pixel electrode is maximum. Now, the non-selection potential of the gate is V
_GL (V), the potential of the source electrode is V _S (V), the potential of the pixel electrode is V _P (V), between the light shielding film 8 and the gate electrode wiring 1,
Capacitances between the light-shielding film 8 and the source electrode wiring 3 and between the light-shielding film 8 and the pixel electrode 4 are C ₁ (F) and C _{2 respectively.}
Assuming that (F) and C ₃ (F), the potential V _{B of the} light shielding film can be approximated by the following equation 3.

[0029]

[Formula 3] V _B = (V _GL × C ₁ + V _S × C ₂ + V _P × C
₃ ) / (C ₁ + C ₂ + C ₃ )

Therefore, when the gate of the TFT is not selected,
When the potential difference between the source electrode and the pixel electrode is the maximum, that is, under the condition that the leak current becomes the most prominent, this number 3
It is preferable to set the above ratio of the capacitances C ₁ , C ₂ and C ₃ so that V _B of the capacitor is located near the minimum V _BMIN shown in FIG.

At this time, it is preferable that the conditions of the respective capacitances C ₁ , C ₂ and C ₃ further satisfy the following range.
First, from the viewpoint of maintaining the equivalence of the source and the drain, the condition of Formula 4 can be mentioned.

[0032]

[Formula 4] 0.8 x C ₂ ≤ C ₃ ≤ 1.2 x C ₂

Further, V _BMIN (V) giving the minimum value
Depends on the fixed charges in the insulating film 7 on the light-shielding film 8 and the state of the interface with the silicon film 5, but it is known that the following formula 5 is generally established under general manufacturing conditions.

[0034]

[ _Formula 5] V _S -2 ≤ V _BMIN ≤ V _S +6 V _S +1 ≤ V _BMIN ≤ V _S +5

Therefore, it is preferable that the following condition (6) is satisfied. Capacitive coupling between the light-shielding film in FIG. 2 and the gate electrode wiring, source electrode wiring, and pixel electrode located in the upper surface direction can be adjusted by providing a dummy pattern. For example, in the vicinity of the contact hole (downward in the plane of FIG. 2), C ₁ can be determined by increasing the overlap area between the source electrode wiring and the insulating film. Examples will be described below.

[0036]

## EQU6 ## 0.6 × C ₁ ≤C ₂ ≤5 × C ₁ 0.6 × C ₁ ≤C ₃ ≤5 × C ₁

[0037]

【Example】

(Example 1) 50 nm on a non-alkali glass substrate
Cr light shielding film was formed and a 800 nm SiO ₂ insulating film was laminated. The material of the insulating film on the light shielding film is not limited to SiO ₂ . Moreover, the film thickness may be in a range having an insulating property. Alternatively, the range may be such that the minimum value of the contribution to the leakage current shown in FIG. 3 is sufficiently small.
In the case of SiO ₂ , 100 to 1000 n as described above.
About m can be used. The light-shielding film is not limited to Cr, and any conductive material can be applied to the present invention.

Further, an amorphous silicon film was laminated by plasma CVD and beam-annealed by an argon ion laser to obtain polycrystalline silicon. The obtained polycrystalline silicon is patterned to form a semiconductor island, and a 120 nm SiO ₂ gate insulating film is formed on the semiconductor island.
A 50 nm Cr gate electrode was formed by stacking and patterning. Further, P ions were implanted into the source and drain portions of the polycrystalline silicon layer using a non-mass separated ion shower device to form n-type regions.

As an interlayer insulating film, a Si ₃ N ₄ film 3 is formed thereon.
A stack of 00 nm was formed, contact holes were formed in the source and drain portions, and a composite metal electrode was formed by sequentially stacking Cr and Al to form a polycrystalline silicon TFT. Regarding the element size of each part of the TFT, the channel length is 1 with dual gate.
The channel offset was 0 μm, the channel width was 4 μm, and the total gate offset was 2.4 μm.

The capacitances between the light-shielding film and the gate electrode wiring, between the light-shielding film and the source electrode wiring, and between the light-shielding film and the pixel electrode are roughly parallel plates using the respective overlapping areas, the film thickness and the dielectric constant of the insulating film. The capacitance value can be calculated by approximating a capacitor. In this example, the design was such that C ₂ = C ₃ = 1.5 × C ₁ . Table 1 shows the result of the simulation. Each part is approximated as a parallel plate capacitor.

[0041]

[Table 1]

In the present invention, since the light-shielding film is formed on the glass substrate, it is usually difficult to use a high temperature process although it depends on the type of material used. A polycrystalline silicon TFT having light resistance and capable of high-speed operation when combined with a polycrystalline silicon forming method using laser annealing
Can be obtained with high productivity.

FIG. 4 schematically shows the method of beam annealing. The laser beam emitted from the continuous wave argon ion laser is adjusted by passing it through an optical system such as a cylindrical lens or an fθ lens. And the beam spot 2
The amorphous silicon layer 5A is irradiated with 0. The object to be annealed has a semiconductor silicon structure in which a light shielding film 8, an AR film 21 and the like are laminated on a glass substrate 9.

High-speed scanning of the beam spot 20 (for example,
Amorphous silicon layer 5A by irradiation at 12 ± 3 m / s)
Is formed on the polycrystalline silicon layer 5B, and a stripe 5C of polycrystalline silicon is finally obtained. Further, the device structure of the TFT is obtained through a process such as patterning.
Next, electrical measurement of the polycrystalline silicon TFT will be described.

The pixel driving method was frame inversion. At this time, with the lower limit value of the source signal as a reference (0 V), pixel selection was performed with a gate selection potential of 17 V, a gate non-selection potential of -5 V, a source signal potential of 0 to 12 V, and a counter electrode potential of 6 V.

Gate non-selection period (gate off voltage is-
5 V), the source electrode is 0 V, and the pixel electrode is 12 V, the light-shielding film potential is 3.25 V, _which is substantially equal to V _BMIN shown in FIG.

As a result of driving the pixel with this structure, the leak current in the gate non-selection period of the polycrystalline silicon TFT is 2
It was suppressed to pA or less, and both the reduction of the light leakage current due to the light shielding on the back surface side of the TFT and the reduction of the leakage current due to the MIS structure below the channel were achieved at the same time.

As a result, in the gate non-selection period, the potential fluctuation of the liquid crystal layer used as the light control layer was sufficiently small, and stable and high display quality was realized. The light control layer of the liquid crystal display element is a conventional TN or S
In addition to TN, a liquid crystal-matrix composite having a continuous capsule structure in which liquid crystal is encapsulated or partially connected and formed in a matrix such as a resin may be used.

[0049]

According to the present invention, the leak current of the polycrystalline silicon TFT used for the active matrix display element can be remarkably reduced. For example, even in the projection type display device, the defect phenomenon due to the leak current of the polycrystalline silicon TFT could be eliminated.

In other words, it has become possible to achieve light shielding in the TFT structure without impairing its electrical characteristics.

Further, even in the case of the normally white display format in which white is displayed when a voltage is applied, the gradation of black is correctly displayed, and the display with high contrast can be expressed.
Further, even when displaying a gray scale, the black portion did not stand out and the pattern could be displayed in a high contrast state.

Further, the present invention can be applied in various ways within a range not impairing its effect.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a polycrystalline semiconductor TFT according to the present invention.

FIG. 2 is a plan view in the vicinity of a polycrystalline semiconductor TFT according to the present invention.

FIG. 3 is a characteristic diagram showing a variation in source / drain current depending on a light shielding film potential in a polycrystalline silicon TFT.

FIG. 4 is a schematic diagram showing a method of beam annealing.

[Explanation of symbols]

 1a: Gate electrode 2: Gate insulating film 3: Source electrode wiring 4: Pixel electrode 5: Polycrystalline silicon layer 6: Interlayer insulating film 7: Insulating film 8: Light-shielding film 9: Glass substrate

Claims (4)

[Claims] 1. A first substrate provided with a pixel electrode, a top gate type polycrystalline semiconductor TFT as a driving element for driving the pixel electrode, and a second substrate provided with a counter electrode facing the pixel electrode. And a light control layer between the first substrate and the second substrate, and the first substrate and the polycrystalline semiconductor TFT.
Is an active matrix display device in which an insulating film and a conductive light-shielding film are provided between the channel and the channel, and the insulating film is arranged between the channel and the light-shielding film, and the light-shielding film is separated for each pixel. Are formed and insulated from each other, and an overlap between the light-shielding film and the gate electrode wiring, between the light-shielding film and the source electrode wiring, and between the light-shielding film and the pixel electrode is provided. When the capacitance between the light-shielding film and the gate electrode wiring is C ₁ , the capacitance between the light-shielding film and the source electrode wiring is C ₂ , and the capacitance between the light-shielding film and the pixel electrode is C ₃ , the maximum effective potential between the source and drain is obtained. When the voltage is applied and the OFF voltage is applied to the gate electrode to _bring the TFT into the non-selected state, the light-shielding film potential V _{B at} which the parasitic channel current of the polycrystalline semiconductor TFT is almost minimum is set to the minimum light-shielding film potential V _BMIN. Then, the light-shielding film potential V C ₁ , C ₂ and C ₃ so that _B falls within the range of the minimum light-shielding film potential V _BMIN ± 2V.
An active matrix display device characterized in that the value of is determined relatively. 2. The active matrix display device according to claim ₁ , wherein C ₁ , C ₂ and C ₃ satisfy the following relationship of the following formula 1. ## EQU1 ## 0.6 × C ₁ ≦ C ₂ ≦ 5 × C ₁ 0.6 × C ₁ ≦ C ₃ ≦ 5 × C ₁ 0.8 × C ₂ ≦ C ₃ ≦ 1.2 × C ₂ 3. The active matrix display device according to claim 1, wherein the insulating film has a thickness of 100 to 1000 nm. 4. The active matrix display element according to claim 1, wherein the polycrystalline semiconductor layer of the polycrystalline semiconductor TFT is formed by beam annealing.